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mmcm, pll: use full name for MMCM, and PLL sites 

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi 2021-02-26 17:04:03 +01:00
parent 13ffbcbf50
commit 7932de32d1
2 changed files with 10 additions and 10 deletions
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10
fuzzers/031-cmt-mmcm/write_mmcm_reg.py
View File

@ -171,7 +171,7 @@ def passthrough_non_register_segbits(seg_in):
Other features generated in fuzzing are passed through. Other features generated in fuzzing are passed through.
""" """
base_offset_register = 'CMT_LOWER_B.MMCME2.CLKOUT5_DIVIDE[1]' base_offset_register = 'CMT_LOWER_B.MMCME2_ADV.CLKOUT5_DIVIDE[1]'
bit_offset = None bit_offset = None
in_use = None in_use = None
@ -266,7 +266,7 @@ def output_registers(bit_offset, in_use):
continue continue
print( print(
'CMT_LOWER_B.MMCME2.{}_{}_{}[{}] {}'.format( 'CMT_LOWER_B.MMCME2_ADV.{}_{}_{}[{}] {}'.format(
register_name, layout, field, bit, register_name, layout, field, bit,
reg.next_bit())) reg.next_bit()))
else: else:
@ -279,7 +279,7 @@ def output_registers(bit_offset, in_use):
continue continue
print( print(
'CMT_LOWER_B.MMCME2.{}[{}] {}'.format( 'CMT_LOWER_B.MMCME2_ADV.{}[{}] {}'.format(
field, start_bit + bit, reg.next_bit())) field, start_bit + bit, reg.next_bit()))
assert bit_count == 16 assert bit_count == 16
@ -287,11 +287,11 @@ def output_registers(bit_offset, in_use):
for bit in range(16): for bit in range(16):
if register_name != layout or layout in ['CLKOUT1', 'CLKOUT2']: if register_name != layout or layout in ['CLKOUT1', 'CLKOUT2']:
print( print(
'CMT_LOWER_B.MMCME2.{}_{}[{}] {}'.format( 'CMT_LOWER_B.MMCME2_ADV.{}_{}[{}] {}'.format(
register_name, layout, bit, reg.next_bit())) register_name, layout, bit, reg.next_bit()))
else: else:
print( print(
'CMT_LOWER_B.MMCME2.{}[{}] {}'.format( 'CMT_LOWER_B.MMCME2_ADV.{}[{}] {}'.format(
register_name, bit, reg.next_bit())) register_name, bit, reg.next_bit()))
parts = in_use.split() parts = in_use.split()

10
fuzzers/032-cmt-pll/write_pll_reg.py
View File

@ -151,7 +151,7 @@ def passthrough_non_register_segbits(seg_in):
Other features generated in fuzzing are passed through. Other features generated in fuzzing are passed through.
""" """
base_offset_register = 'CMT_UPPER_T.PLLE2.CLKOUT5_DIVIDE[1]' base_offset_register = 'CMT_UPPER_T.PLLE2_ADV.CLKOUT5_DIVIDE[1]'
bit_offset = None bit_offset = None
in_use = None in_use = None
@ -244,7 +244,7 @@ def output_registers(bit_offset, in_use):
continue continue
print( print(
'CMT_UPPER_T.PLLE2.{}_{}_{}[{}] {}'.format( 'CMT_UPPER_T.PLLE2_ADV.{}_{}_{}[{}] {}'.format(
register_name, layout, field, bit, register_name, layout, field, bit,
reg.next_bit())) reg.next_bit()))
else: else:
@ -257,7 +257,7 @@ def output_registers(bit_offset, in_use):
continue continue
print( print(
'CMT_UPPER_T.PLLE2.{}[{}] {}'.format( 'CMT_UPPER_T.PLLE2_ADV.{}[{}] {}'.format(
field, start_bit + bit, reg.next_bit())) field, start_bit + bit, reg.next_bit()))
assert bit_count == 16 assert bit_count == 16
@ -265,11 +265,11 @@ def output_registers(bit_offset, in_use):
for bit in range(16): for bit in range(16):
if register_name != layout or layout in ['CLKOUT1', 'CLKOUT2']: if register_name != layout or layout in ['CLKOUT1', 'CLKOUT2']:
print( print(
'CMT_UPPER_T.PLLE2.{}_{}[{}] {}'.format( 'CMT_UPPER_T.PLLE2_ADV.{}_{}[{}] {}'.format(
register_name, layout, bit, reg.next_bit())) register_name, layout, bit, reg.next_bit()))
else: else:
print( print(
'CMT_UPPER_T.PLLE2.{}[{}] {}'.format( 'CMT_UPPER_T.PLLE2_ADV.{}[{}] {}'.format(
register_name, bit, reg.next_bit())) register_name, bit, reg.next_bit()))
parts = in_use.split() parts = in_use.split()