064-gtp-channel: add gtp_channel fuzzer

Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>

fuzzers/064-gtp-channel-conf/Makefile

@@ -0,0 +1,31 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+N ?= 40
+
+include ../fuzzer.mk
+
+database: build/segbits_gtp_channelx.db
+
+build/segbits_gtp_channelx.rdb: $(SPECIMENS_OK)
+	${XRAY_SEGMATCH} -o build/segbits_gtp_channelx.rdb $(addsuffix /segdata_gtp_channel_[0123].txt,$(SPECIMENS))
+
+build/segbits_gtp_channelx.db: build/segbits_gtp_channelx.rdb
+	${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
+	${XRAY_MASKMERGE} build/mask_gtp_channelx.db $(addsuffix /segdata_gtp_channel_[0123].txt,$(SPECIMENS))
+
+pushdb:
+	${XRAY_MERGEDB} gtp_channel_0 build/segbits_gtp_channelx.db
+	${XRAY_MERGEDB} gtp_channel_1 build/segbits_gtp_channelx.db
+	${XRAY_MERGEDB} gtp_channel_2 build/segbits_gtp_channelx.db
+	${XRAY_MERGEDB} gtp_channel_3 build/segbits_gtp_channelx.db
+	${XRAY_MERGEDB} mask_gtp_channel_0 build/mask_gtp_channelx.db
+	${XRAY_MERGEDB} mask_gtp_channel_1 build/mask_gtp_channelx.db
+	${XRAY_MERGEDB} mask_gtp_channel_2 build/mask_gtp_channelx.db
+	${XRAY_MERGEDB} mask_gtp_channel_3 build/mask_gtp_channelx.db
+
+.PHONY: database pushdb

fuzzers/064-gtp-channel-conf/generate.py

@@ -0,0 +1,95 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+import json
+import os
+from enum import Enum
+
+from prjxray.segmaker import Segmaker
+
+INT = "INT"
+BIN = "BIN"
+BOOL = "BOOL"
+STR = "STR"
+
+
+def bitfilter(frame, bit):
+    # Filter out interconnect bits.
+    if frame not in [28, 29, 30, 31]:
+        return False
+
+    return True
+
+
+def main():
+    segmk = Segmaker("design.bits")
+
+    fuz_dir = os.getenv("FUZDIR", None)
+    assert fuz_dir
+    with open(os.path.join(fuz_dir, "attrs.json"), "r") as attr_file:
+        attrs = json.load(attr_file)
+
+    print("Loading tags")
+    with open("params.json") as f:
+        params = json.load(f)
+
+    site = params["site"]
+    in_use = params["IN_USE"]
+
+    segmk.add_site_tag(site, "IN_USE", in_use)
+
+    for param, param_info in attrs.items():
+        value = params[param]
+        param_type = param_info["type"]
+        param_digits = param_info["digits"]
+        param_values = param_info["values"]
+
+        if param_type == INT:
+            param_encodings = param_info["encoding"]
+            param_encoding = param_encodings[param_values.index(value)]
+            bitstr = [
+                int(x) for x in "{value:0{digits}b}".format(
+                    value=param_encoding, digits=param_digits)[::-1]
+            ]
+
+            for i in range(param_digits):
+                segmk.add_site_tag(site, '%s[%u]' % (param, i), bitstr[i])
+        elif param_type == BIN:
+            bitstr = [
+                int(x) for x in "{value:0{digits}b}".format(
+                    value=value, digits=param_digits)[::-1]
+            ]
+
+            for i in range(param_digits):
+                segmk.add_site_tag(site, "%s[%u]" % (param, i), bitstr[i])
+        elif param_type == BOOL:
+            segmk.add_site_tag(site, param, value == "TRUE")
+        else:
+            assert param_type == STR
+
+            for param_value in param_values:
+                segmk.add_site_tag(site, "{}.{}".format(param, param_value), value == param_value)
+
+        for param, invert in [("TXUSRCLK", 1), ("TXUSRCLK2", 1), ("TXPHDLYTSTCLK", 1),
+                      ("SIGVALIDCLK", 1), ("RXUSRCLK", 1), ("RXUSRCLK2", 1),
+                      ("DRPCLK", 1), ("DMONITORCLK", 1), ("CLKRSVD0", 1),
+                      ("CLKRSVD1", 1)]:
+            if invert:
+                segmk.add_site_tag(site, "ZINV_" + param, 1 ^ params[param])
+            else:
+                segmk.add_site_tag(site, "INV_" + param, params[param])
+
+    segmk.compile(bitfilter=bitfilter)
+    segmk.write()
+
+
+if __name__ == '__main__':
+    main()

fuzzers/064-gtp-channel-conf/generate.tcl

@@ -0,0 +1,29 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+proc run {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+    set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
+    set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-48}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-47}]
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+}
+
+run

fuzzers/064-gtp-channel-conf/top.py

@@ -0,0 +1,119 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+import json
+import os
+import random
+from collections import namedtuple
+
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray import verilog
+from prjxray.db import Database
+
+INT = "INT"
+BIN = "BIN"
+BOOL = "BOOL"
+STR = "STR"
+
+
+def gen_sites():
+    db = Database(util.get_db_root(), util.get_part())
+    grid = db.grid()
+    for tile_name in sorted(grid.tiles()):
+        loc = grid.loc_of_tilename(tile_name)
+        gridinfo = grid.gridinfo_at_loc(loc)
+
+        if "GTP_CHANNEL" not in gridinfo.tile_type:
+            continue
+
+        for site_name, site_type in gridinfo.sites.items():
+            if site_type != "GTPE2_CHANNEL":
+                continue
+
+            return site_name
+
+
+def main():
+    print(
+        '''
+module top(
+    input wire in,
+    output wire out
+);
+
+assign out = in;
+''')
+
+    site_name = gen_sites()
+
+    params = dict()
+    params['site'] = site_name
+
+    verilog_attr = ""
+
+    verilog_attr = "#("
+
+    fuz_dir = os.getenv("FUZDIR", None)
+    assert fuz_dir
+    with open(os.path.join(fuz_dir, "attrs.json"), "r") as attrs_file:
+        attrs = json.load(attrs_file)
+
+    in_use = bool(random.randint(0, 9))
+    params["IN_USE"] = in_use
+
+    for param, param_info in attrs.items():
+        param_type = param_info["type"]
+        param_values = param_info["values"]
+        param_digits = param_info["digits"]
+
+        if param_type == INT:
+            value = random.choice(param_values)
+            value_str = value
+        elif param_type == BIN:
+            value = random.randint(0, param_values[0])
+            value_str = "{digits}'b{value:0{digits}b}".format(
+                value=value, digits=param_digits)
+        elif param_type in [BOOL, STR]:
+            value = random.choice(param_values)
+            value_str = verilog.quote(value)
+
+        params[param] = value
+
+        verilog_attr += """
+    .{}({}),""".format(param, value_str)
+
+    for param in ["TXUSRCLK", "TXUSRCLK2", "TXPHDLYTSTCLK",
+                  "SIGVALIDCLK", "RXUSRCLK", "RXUSRCLK2",
+                  "DRPCLK", "DMONITORCLK", "CLKRSVD0", "CLKRSVD1"]:
+        is_inverted = random.randint(0, 1)
+
+        params[param] = is_inverted
+
+        verilog_attr += """
+    .IS_{}_INVERTED({}),""".format(param, is_inverted)
+
+    verilog_attr = verilog_attr.rstrip(",")
+    verilog_attr += "\n)"
+
+    print("(* KEEP, DONT_TOUCH, LOC=\"{}\" *)".format(site_name))
+    print(
+            """GTPE2_CHANNEL {} gtp_channel ();
+    """.format(verilog_attr))
+
+    print("endmodule")
+
+    with open('params.json', 'w') as f:
+        json.dump(params, f, indent=2)
+
+
+if __name__ == '__main__':
+    main()