Merge pull request #10 from openXC7/merge-virtex7-support

Merge virtex7 support

.github/scripts/xilinx.sh

@@ -32,7 +32,7 @@ echo "----------------------------------------"
 (
 	set -e
 	cd /opt
-	if [ x"$XRAY_SETTINGS" = x"kintex7" ]; then
+	if [ x"$XRAY_SETTINGS" = x"kintex7" ] || [ x"$XRAY_SETTINGS" = x"virtex7" ]; then
 		echo "Using Xilinx Vivado Design Edition for $XRAY_SETTINGS build."
 		echo
 		ln -s /mnt/aux/Xilinx-design /opt/Xilinx

.github/workflows/Pipeline.yml

@@ -18,7 +18,7 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        family: ['artix7', 'zynq7', 'kintex7', 'spartan7']
+        family: ['artix7', 'zynq7', 'kintex7', 'spartan7', 'virtex7']
 
     env:
       GHA_SSH_TUNNEL_KEY: "${{ secrets.LICENSE_TUNNEL_KEY_DATA }}"

Makefile

@@ -136,7 +136,7 @@ check-license:
 # Targets related to Project X-Ray databases
 # ------------------------
 
-DATABASES=artix7 kintex7 zynq7 spartan7
+DATABASES=artix7 kintex7 zynq7 spartan7 virtex7
 
 define database
 
@@ -191,8 +191,9 @@ ARTIX_PARTS=artix7_50t artix7_200t
 ZYNQ_PARTS=zynq7010 zynq7030 zynq7045 zynq7100
 KINTEX_PARTS=kintex7_160t kintex7_325t kintex7_420t kintex7_480t
 SPARTAN_PARTS=
+VIRTEX_PARTS=
 
-XRAY_PARTS=${ARTIX_PARTS} ${ZYNQ_PARTS} ${KINTEX_PARTS} ${SPARTAN_PARTS}
+XRAY_PARTS=${ARTIX_PARTS} ${ZYNQ_PARTS} ${KINTEX_PARTS} ${SPARTAN_PARTS} ${VIRTEX_PARTS}
 
 define multiple-parts
 
@@ -245,6 +246,13 @@ db-extras-kintex7-roi: $(addprefix db-roi-only-,$(KINTEX_PARTS))
 db-extras-kintex7-harness:
 	@true
 
+db-extras-virtex7-parts: $(addprefix db-part-only-,$(VIRTEX_PARTS))
+
+db-extras-virtex7-roi: $(addprefix db-roi-only-,$(VIRTEX_PARTS))
+
+db-extras-virtex7-harness:
+	@true
+
 db-extras-spartan7-parts:
 	@true
 

README.md

@@ -9,6 +9,12 @@ Documenting the Xilinx 7-series bit-stream format.
 This repository contains both tools and scripts which allow you to document the
 bit-stream format of Xilinx 7-series FPGAs.
 
+> **Virtex-7 / VC707 users:** see [**Virtex-7 Port
+> Status**](#virtex-7-port-status-virtex7-support-branch) below for the
+> `virtex7-support` branch — different Vivado version, working open flow
+> on `xc7vx485tffg1761-2`, and device-specific patches. The Quickstart
+> Guide that follows assumes the upstream Artix-7 / 2017.2 path.
+
 More documentation can be found published on [prjxray ReadTheDocs site](https://prjxray.readthedocs.io/en/latest/) - this includes;
  * [Highlevel Bitstream Architecture](https://prjxray.readthedocs.io/en/latest/architecture/overview.html)
  * [Overview of DB Development Process](https://prjxray.readthedocs.io/en/latest/db_dev_process/index.html)
@@ -237,11 +243,218 @@ it.
 Current the focus has been on the Artix-7 50T part. This structure is common
 between all footprints of the 15T, 35T and 50T varieties.
 
-We have also started experimenting with the Kintex-7 parts.
+We have also started experimenting with the Kintex-7 and Virtex-7 parts.
 
 The aim is to eventually document all parts in the Xilinx 7-series FPGAs but we
 can not do this alone, **we need your help**!
 
+## Virtex-7 Port Status (`virtex7-support` branch)
+
+This branch ports the openXC7 prjxray flow to **Virtex-7 `xc7vx485tffg1761-2`**
+(VC707 board), modelled on the Kintex-7 sub-flow. The original goal — a fully
+open-source bit→DCP / fasm→bit round-trip on a Virtex-7 HP-only part — has
+been met for the four VC707 reference designs (`rst_to_led`, `counter`,
+`counter_bufr`, `telegraph`) and end-to-end for the PicoSoC UART demo running
+on real silicon.
+
+The work spans four sibling branches on the openXC7 GitHub:
+
+| Repo | Branch | Carries |
+|---|---|---|
+| openXC7/prjxray | `virtex7-support` | this DB tree + `fasm2frames.py` bank-glue rules |
+| openXC7/nextpnr-xilinx-meta | `virtex7-support` | per-site metadata + `wire_intents.json` |
+| openXC7/nextpnr-xilinx | `virtex7-support` | RAM128/256X1S packing + INT-tile constant-net bridge |
+| openXC7/demo-projects | `virtex7-branch` | VC707 reference `.bit` files + sources |
+
+> **Vivado version.** This port was developed and validated against
+> **Vivado 2020.1**. Other 2018+ releases may well work — the fuzzers and
+> Tcl helpers are not knowingly using any 2020.1-specific feature — but the
+> upstream-recommended **2017.2 is too old** for Virtex-7 here: it predates
+> the device support files we need (`xc7vx485tffg1761-2` HP-bank IOB18
+> behaviour, several `HCLK_IOI`/`CMT` properties the fuzzers query, the
+> `write_pip_txtdata` bulk-fetch paths the `utils.tcl` patch exercises).
+> Set `XRAY_VIVADO_SETTINGS` accordingly:
+>
+>     export XRAY_VIVADO_SETTINGS=/opt/Xilinx/Vivado/2020.1/settings64.sh
+
+### Achievements
+
+- **End-to-end open flow on real hardware (VC707):**
+  - 8-bit skew-tolerant counter blinks on VC707 with reset debounce.
+  - 200 MHz LVDS sysclk variant (`counter_bufr`) runs via IBUFDS + BUFR.
+  - `telegraph` UART smoke test prints `ABCDEFG` at 115200 baud on
+    `/dev/ttyUSB0`, bit-equivalent to the Vivado reference.
+  - **PicoSoC** (`picorv32/picosoc`) running on VC707 at 125 MHz from the
+    SGMIICLK crystal — BRAM-resident firmware prints
+    `PicoSoC alive on VC707 @ 125 MHz`, LEDs walk a pattern.
+- **All four reference designs at 0/0 bit-difference** vs Vivado, with **zero
+  `.frm` patches** — the bank-glue rules are now codified as DB entries plus
+  auto-inject in `utils/fasm2frames.py`.
+- **Cross-family segbits/ppips transplant** from the openXC7
+  [`prjxray-db`](https://github.com/openXC7/prjxray-db) Kintex-7 tree into
+  `database/virtex7/`: ~39 381 segbits + ~12 273 ppips entries, plus targeted
+  key copies for `clk_hrow_*`, `clk_bufg_*`, `hclk_cmt*`, `io_int_interface_*`
+  (≈51 k entries total). Pre-transplant tree backed up at
+  `database/virtex7.before_transplant/`.
+- **HP-bank glue codified — 7 new segbits entries + auto-inject:**
+  - `LIOB18.IOB_Y0.IBUF_HP_BANK_GLUE` (1 bit)
+  - `LIOB18.IOB_Y0.OBUF_HP_BANK_GLUE` (3 bits)
+  - `LIOB18.IOB_Y1.OBUF_HP_BANK_GLUE` (3 bits)
+  - `RIOB18.IOB_Y0.IBUFDS_BANK_GLUE` (7 bits, LVDS pair root)
+  - `INT_L.IOB_COL_OBUF_CASCADE_Y1` (3 bits, Y1 OBUF column carry)
+  - `INT_L.IOB_COL_BANK_ACTIVE` (3 bits, bank-active marker)
+  - `INT_L.GFAN_TIE_ROOT_GLUE` (1 bit, OBUF T-tie GND routing)
+  - `HCLK_L.HCLK_LEAF_BUFRCLK3_ACTIVE` (1 bit, BUFR clock leaf)
+  - Plus 14 silicon-default bits added as IOB18 `default` entries (`PUDC_B`
+    cascade, DCI cascade, slew/drive defaults Vivado emits unconditionally).
+- **`utils/fasm2frames.py` bank-glue auto-inject** — direction-aware
+  walk over the FASM stream classifies each LIOB18 site as input / output /
+  diff-input from feature names (`IN_ONLY`, `.IN`, `IBUFDISABLE` → in;
+  `.DRIVE.` → out; `IN_DIFF` → diff_in) and injects the matching glue
+  features before frame assembly. `PUDC_B` template emission rewritten for
+  HP-bank IOSTANDARDs (10 features cover Y0 + Y1 default state). The
+  `pudc_b_tile_site` is resolved unconditionally so the HP-bank walk skips it.
+- **11 fuzzers patched** for HP-bank / virtex7-grid awareness:
+  - `037-iob18-pips` — left-side mirror sites (LIOI / LIOI_TBYTESRC /
+    LIOI_TBYTETERM), `top.py` NOT_INCLUDED_TILES for `*_SING`, generate-side
+    tile-type normalization, `ioi_pip_list.tcl` LIOI emission.
+  - `039-hclk-config` — virtex7 split (HCLK_IOI vs HCLK_IOI3),
+    `XRAY_IOSTANDARD` env var, IOB18M / IOB33M alternation in `top.py`.
+  - `047a-hclk-idelayctrl-pips` — accepts both HCLK_IOI and HCLK_IOI3.
+  - `034 / 034b / 041 / 043 / 044 / 045 / 046` — removed local
+    `write_pip_txtdata` overrides that shadowed the patched `utils.tcl`
+    bulk-fetch (~4× faster per specimen on xc7vx485t).
+- **`utils/utils.tcl` bulk-fetch patch** for `write_pip_txtdata` —
+  per-net `foreach pip` → bulk `get_pips` + bulk `get_property IS_DIRECTIONAL`
+  + cached `dst_wire_to_num_pips`. ~4× speed-up; on
+  `xc7vx485tffg1761-2` cuts `041-clk-hrow-pips`/`045-hclk-cmt-pips` specimens
+  from ~1.5 h to ~25 min each.
+- **`utils/fasm2frames.py` HP-bank fix** — was hard-coded to `HCLK_IOI3_*`
+  tile prefix; now probes the grid for whichever of `HCLK_IOI_` / `HCLK_IOI3_`
+  exists. STEPDOWN bank-anchor check widened accordingly.
+- **`utils/mergedb.sh` extended** with LIOI / LIOI_TBYTESRC / LIOI_TBYTETERM
+  / LIOB18 / mask_liob18 cases.
+- **RapidWright `json2dcp.jar` rebuilt** against modern RapidWright (2025.2.1)
+  and patched for virtex7 — verified `rst_to_led_routed.json` → 1.38 MB DCP
+  that loads back cleanly on `xc7vx485tffg1761-2`.
+- **nextpnr-xilinx companion patches** (on its `virtex7-support` branch):
+  - `xilinx/pack_dram.cc` — RAM128X1S / RAM256X1S single-port distributed RAM
+    packing (mirrors the SPO half of the dual-port families); needed by
+    PicoSoC's BRAM-fallback synthesis.
+  - `xilinx/python/nextpnr_structs.py` — bridges `PSEUDO_GND_WIRE_ROW` /
+    `PSEUDO_VCC_WIRE_ROW` to the INT tile's `GND_WIRE` / `VCC_WIRE` via
+    `CONST_DRIVER` pseudo-pips, so the router can find a route for OBUF
+    T-tie nets to the global GND.
+
+### Virtex-7 architecture discoveries
+
+These are the things that turned out to be **different on Virtex-7**, not
+inherited automatically by transplanting the Kintex-7 sub-flow. Some are
+silicon-level facts that prjxray was never set up to capture; others are
+nextpnr-xilinx assumptions that broke at scale.
+
+- **HP-bank ≠ HR-bank silicon.** Virtex-7 `xc7vx485t` is HP-bank-only
+  (`IOB18` family using `INBUF_DCIEN` / `OUTBUF_DCIEN`), whereas Kintex-7
+  parts on the openXC7 path are mostly HR (`IOB33` family using
+  `IBUF` / `OBUF`). The HR and HP IO logic share the same prjxray feature
+  syntax but **encode different silicon bits**, and the surrounding clock
+  region differs:
+  - HR uses `HCLK_IOI3_*` tiles.
+  - HP uses `HCLK_IOI_*` tiles.
+  - The IO-related fasm tools were hard-coded to `HCLK_IOI3_*` and silently
+    dropped HP-bank features until probed; `fasm2frames.py` and several
+    fuzzers now branch on a runtime grid probe.
+- **L/R-side mirror.** The VC707 IO column lives on the **left** side
+  (`LIOB18_X81*` / `LIOI_X*`) — most Kintex-7 reference designs used the
+  right-side mirror. The 037-iob18-pips fuzzer had to learn left-side
+  emission (it had only ever exercised RIOB18).
+- **"Bank glue" — the silicon enables Vivado sets that no prjxray feature
+  emits.** A correct prjxray-driven bitstream for an HP-bank design is a
+  proper *subset* of what Vivado emits because Vivado writes ~14 extra bits
+  per bank-in-use that the prjxray feature schema never claimed. These are
+  not user-visible (no fasm feature corresponds to them) but the HP-bank
+  IOB silicon **will not drive** without them. Categories:
+  - **Tile-in-use markers** in `INT_L_X62Y*` and `INT_L_X32Y49` — three bits
+    that indicate "this bank's OBUF column is live" / "DCI cascade is live".
+  - **Y0 vs Y1 OBUF cascade** — `LIOB18.IOB_Y0.OBUF_HP_BANK_GLUE` and
+    `.IOB_Y1.OBUF_HP_BANK_GLUE` are independent 3-bit groups. Crucially the
+    Y1 column's 3 bits also have to be cascaded into the next INT_L row up
+    (`INT_L.IOB_COL_OBUF_CASCADE_Y1`).
+  - **`PUDC_B` cascade.** The HP-bank `PUDC_B` pin (`LIOB18_X81Y97` on
+    `xc7vx485tffg1761-2`) controls bank-wide auto-pullup behaviour at boot
+    and **always** appears in the bitstream with 10 silicon-default features,
+    even when the user never references it. We now emit those features
+    unconditionally from `fasm2frames.py`.
+  - **IBUFDS pair root.** A differential IBUFDS uses the Master IOB
+    (`Y0`) as the live pin and emits 7 silicon-enable bits there
+    (`RIOB18.IOB_Y0.IBUFDS_BANK_GLUE`). The Slave (`Y1`) stays in default
+    state. Without these the LVDS receiver does not enable.
+  - Heuristic gotcha: our first cut classified OBUFs by `.SLEW.`; that gave
+    false positives because Vivado emits `SLEW.SLOW` on default-state IBUFs
+    too. The reliable OBUF marker is `.DRIVE.`.
+- **`HCLK_L.HCLK_LEAF_BUFRCLK3_ACTIVE`** — a one-bit "this BUFR leaf is
+  live" marker that Vivado sets when a BUFR is the source for a clock
+  region. Required for the `counter_bufr` 200 MHz LVDS clocking path; we
+  inject it whenever the FASM stream mentions any BUFR feature.
+- **`INT_L.GFAN_TIE_ROOT_GLUE`** — OBUF `T` (tristate) input must be tied
+  to GND for non-tristate use. Vivado routes that GND from the **next
+  INT_L row up** via the `GFAN0.GND_WIRE` pseudo-pip; the routing-graph
+  signature requires one extra bit at `26_018` in `INT_L_X62Y(N+10)`. We
+  detect any `INT_L_X62Y*.GFAN0.GND_WIRE` in the FASM and inject the
+  root-row glue automatically. This is the last residual that brought all
+  four reference designs to 0/0 vs Vivado on raw open flow.
+- **`fasm2bels` chokes on `NOCLKINV`** — the `xc7vx485t` connection
+  database builds (14 min, 4.2 GB, 56.8 M wires), but `clb_models.py` does
+  not yet handle the `NOCLKINV` packer feature that nextpnr-xilinx emits
+  for HP-bank SLICEs. Asserted as `{NOCLKINV}`. Phase B (`fasm2bels`
+  virtex7 port) is paused on this.
+- **nextpnr-xilinx OBUF T-tie convergence.** Within nextpnr the router
+  cannot find a path from `NULL_X0Y364/PSEUDO_GND_WIRE_GLBL` to the LIOB18
+  OBUF `TRI` pin because the constant-net source lives outside the INT
+  tile graph. Fixed at chipdb-build time by `nextpnr_structs.py`:
+  emit `CONST_DRIVER` pseudo-pips that bridge `PSEUDO_GND_WIRE_ROW` /
+  `PSEUDO_VCC_WIRE_ROW` into each INT tile's `GND_WIRE` / `VCC_WIRE`.
+- **nextpnr-xilinx Y137/Y138 chipdb wire mapping** — still open. Two LIOB18
+  rows present in the chipdb point at wires that the architecture
+  assignment then loses track of. Functional impact zero (our
+  `fasm2frames.py` covers the silicon-enable side); but the bug is real and
+  filed at task #31.
+- **PicoSoC needed RAM128X1S / RAM256X1S packing.** PicoSoC's
+  default `picorv32_pcpi_div` synthesises into single-port distributed RAM.
+  nextpnr-xilinx had packers only for the dual-port `RAM128X1D` /
+  `RAM256X1D` variants; the SP packers are mirrors of the SPO half of
+  those, added on this branch.
+
+### Goals (remaining)
+
+- **Codify the 228-bit PicoSoC CLB-glue family** (relative offsets
+  `30_006 / 30_011 / 30_020 / 30_022 / 30_040 / 30_045 / 30_052 / 30_056`
+  + `31_040 / 31_043`) — per-SLICE "in use" bits that show up only when a
+  SLICE is occupied. Would push PicoSoC's bit-diff vs Vivado to zero.
+- **Restore the 236 missing IOI features** (IDELAY / OSERDES / OQ) into
+  `segbits_lioi.db` — currently we have HR-side coverage transplanted but
+  the HP-side variants need their own segdata.
+- **`fasm2bels` virtex7 port** — past the `NOCLKINV` block, then through
+  HP-bank IOB BEL substitutions (sketched in `models/iob_models.py`).
+- **Y137/Y138 chipdb wire mapping** in nextpnr-xilinx — for parity with
+  Vivado's checkpoint format.
+
+### Cross-cutting open TODOs
+
+- Expand the virtex7 ROI (small ROI was sufficient for the IO / HCLK
+  fuzzers but the CMT / DSP / GTX fuzzers will want more).
+- Vivado DRC cross-check of nextpnr output.
+- Exclude `GTX_INT_INTERFACE` pips from the virtex7 chipdb.
+- Bits info for `CFG_CENTER` / `*_SING` tiles.
+
+### Constraints
+
+- Patches must **not** regress other families (artix7 / kintex7 / zynq7 /
+  spartan7). The HP-bank additions are gated on tile-type prefix so the
+  HR-bank paths stay byte-identical.
+- Build artefacts under `fuzzers/*/build/` are **retained** for debugging
+  — `make clean` is not invoked between fuzzer iterations.
+
 ## Adding a new part to an existing family
 
 We have written a [detailed guide](https://f4pga.readthedocs.io/projects/prjxray/en/latest/db_dev_process/newpart.html) that walks through the process of adding a new part to an existing family.

VIRTEX7_OPENFLOW_REPRODUCE.md

@@ -0,0 +1,338 @@
+# Reproducing the first working VC707 open-flow bitstream
+
+This document captures the end-to-end recipe that produced the first
+confirmed-working open-flow bitstream on a real Virtex-7 VC707 board on
+**2026-06-01**.  The design — `IBUFDS + BUFG + FDRE + OBUF` — runs from
+SYSCLK_P/N at 200 MHz, toggles a flip-flop, and drives LED **D0** (silk
+`GPIO_LED_0`, pin `AM39`).  Observed hardware behaviour: D0 at half
+brightness from the FF toggling at 100 MHz, with reset (pin `AV40`)
+visibly controlling the LED state.
+
+This is the open-flow analogue of what Vivado would produce from the same
+RTL — nextpnr-xilinx places and routes, RapidWright converts to a DCP,
+Vivado writes the bitstream.
+
+---
+
+## What you need
+
+| Component | Where | Version / branch |
+|---|---|---|
+| prjxray (this repo) | https://github.com/openXC7/prjxray | `virtex7-support` branch |
+| nextpnr-xilinx | https://github.com/openXC7/nextpnr-xilinx | a branch with the patches from `xilinx/{fasm,pack_clocking_xc7,pack_io_xc7}.cc` listed below; develops out of the `atomic-carry4` tag |
+| RapidWright | https://github.com/Xilinx/RapidWright | `2025.2.1` standalone jar (`rapidwright-2025.2.1-standalone-lin64.jar`, ~95 MB) plus `gson-2.10.1.jar` |
+| json2dcp + WireOracle + BuildWireOracle | local glue | tracked in `deps/json_drc-portable` (git submodule) |
+| Vivado | for `write_bitstream` and as source of device data | **2020.1** (others 2018+ may work) |
+| SystemVerilog Suite (SVS) | `~/System-Verilog-suite/_build/default/sv_suite.exe` | Verilog → EDIF → nextpnr JSON |
+| openFPGALoader | https://github.com/trabucayre/openFPGALoader | built locally; loads via Digilent JTAG |
+
+> **Vivado version.**  `2020.1` is the validated target; the upstream
+> prjxray default of `2017.2` is too old for `xc7vx485tffg1761-2`
+> (HP-bank IOB18 behaviour, `HCLK_IOI` / `CMT` properties, several
+> Tcl helpers that the patched `utils.tcl` exercises).  Set
+> `XRAY_VIVADO_SETTINGS=/opt/Xilinx/Vivado/2020.1/settings64.sh`.
+
+---
+
+## The design (`min_ibufds_ff_led`)
+
+`top.v` — minimal IBUFDS + BUFG + FDRE + OBUF:
+
+```verilog
+module top (
+    input  wire sysclk_p, sysclk_n, rst,
+    output wire led
+);
+    wire clk_raw, clk;
+    IBUFDS #(.DIFF_TERM("TRUE"), .IBUF_LOW_PWR("FALSE"), .IOSTANDARD("LVDS"))
+        sysclk_ibufds (.I(sysclk_p), .IB(sysclk_n), .O(clk_raw));
+    BUFG sysclk_bufg (.I(clk_raw), .O(clk));
+    reg q = 1'b0;
+    always @(posedge clk) begin
+        if (rst) q <= 1'b0;
+        else     q <= ~q;
+    end
+    OBUF led_obuf (.I(q), .O(led));
+endmodule
+```
+
+`top.xdc` — VC707 pin map:
+
+```tcl
+set_property PACKAGE_PIN E19 [get_ports sysclk_p]
+set_property PACKAGE_PIN E18 [get_ports sysclk_n]
+set_property IOSTANDARD  LVDS [get_ports sysclk_p]
+set_property IOSTANDARD  LVDS [get_ports sysclk_n]
+create_clock -period 5.000 -name sysclk [get_ports sysclk_p]
+set_property PACKAGE_PIN AV40    [get_ports rst]
+set_property IOSTANDARD  LVCMOS18 [get_ports rst]
+set_property PACKAGE_PIN AM39    [get_ports led]
+set_property IOSTANDARD  LVCMOS18 [get_ports led]
+set_property CFGBVS GND          [current_design]
+set_property CONFIG_VOLTAGE 1.8  [current_design]
+```
+
+---
+
+## Build prerequisites
+
+### 1. nextpnr-xilinx
+
+```bash
+cd ~/nextpnr-xilinx
+cmake -B build -DARCH=xilinx -DBUILD_GUI=OFF
+cmake --build build --target nextpnr-xilinx -j$(nproc)
+```
+
+Critical patches (in this checkout, on the `virtex7-support` /
+`atomic-carry4` branch):
+
+- `xilinx/fasm.cc` — HP-bank glue (LIOB18 default emission, `IBUF_HP_BANK_GLUE`,
+  `OBUF_HP_BANK_GLUE`, `IBUFDS_BANK_GLUE`), and the phantom-BUFGCTRL
+  filter that suppresses `CLK_BUFG_*_R` features for unused slots.
+- `xilinx/pack_clocking_xc7.cc` — preserves `X_ORIG_TYPE=BUFG` and
+  `X_ORIG_PORT_I0=I` etc. when packing BUFG → BUFGCTRL so downstream
+  EDIF / DCP emission can re-create the BUFG cell.
+- `xilinx/pack_io_xc7.cc` — accept `LIOB18_` tiles in addition to
+  `RIOB18_` everywhere IOB18-specific placement was hardcoded;
+  expand `IBUFDS_GTE2` user check to allow BUFG / BUFH / BUFHCE / BUFR.
+
+The xc7vx485t chipdb must already be built from the `nextpnr-xilinx-meta`
+metadata tree (`xilinx/xc7vx485t.bin`).
+
+### 2. RapidWright + the glue jar
+
+The glue lives in `deps/json_drc-portable` and its Makefile fetches
+everything it needs — the RapidWright standalone jar, gson, and the
+device data for the one part:
+
+```bash
+make -C deps/json_drc-portable        # fetch + build all tool jars
+make -C deps/json_drc-portable verify # prove the result actually runs
+```
+
+Note it does NOT download `rapidwright_data.zip` (2.0 GB); it asks
+RapidWright for the single part instead, which is about 3.6 MB.
+
+### 3. Wire-name oracle (one-shot per part)
+
+The oracle is a static per-tile-type table answering PIP-direction,
+routethru, and site→tile questions that json2dcp consults at routing-
+import time.  Build it once for `xc7vx485tffg1761-2`:
+
+```bash
+make -C deps/json_drc-portable oracle/xc7vx485tffg1761-2.oracle.txt.gz
+```
+
+(`make deps` builds it too; the rule runs `BuildWireOracle` against the
+device database and is slow, so it is cached in `oracle/`.)
+
+Cost: ~1.5 s wall, ~2.5 MB gzipped output.  json2dcp auto-discovers
+the file by walking up from the JSON's directory looking for an
+`oracle/<part>.oracle.txt.gz` sibling, or via
+`XRAY_WIRE_ORACLE=<path>`.  json2dcp **bombs out** if the oracle
+file is missing (no fallback — silent fallback produced bitstreams
+that loaded but didn't clock on hardware).
+
+---
+
+## End-to-end flow
+
+```bash
+cd ~/min_ibufds_ff_led
+
+# 1) SVS:   top.v          -> top_vivado_synth.edif (via Vivado synthesis)
+#          top_vivado_synth.edif -> top.json (via SVS)
+# 2) nextpnr-xilinx: top.json -> top_routed.json + top.fasm
+~/System-Verilog-suite/_build/default/sv_suite.exe script nextpnr_pass/build.lua
+
+# 3) json2dcp: top_routed.json -> top_rw.dcp
+ethsoc/routedjson2dcp.sh nextpnr_pass/top_routed.json nextpnr_pass/top_rw.dcp
+# (wraps rapidwright_json2dcp.jar, sets RAPIDWRIGHT_PATH + XRAY_WIRE_ORACLE,
+#  and preprocesses the nextpnr JSON for json2dcp's strictness)
+```
+
+`build.lua` is the SVS script that drives the Verilog→EDIF→JSON→nextpnr
+pipeline.  See `nextpnr_pass/build.lua`.
+
+Expected json2dcp output (good run):
+
+```
+[wire-oracle] loaded …/xc7vx485tffg1761-2.oracle.txt.gz types=115 tiles=150380 pips=35126
+json2dcp ROUTING net=q:        imported=17 (oracle=10, oracle_rev_bidir=0) … lookup_failed=0
+json2dcp ROUTING net=rst_IBUF: imported=12 (oracle=6,  oracle_rev_bidir=0) … lookup_failed=0
+json2dcp ROUTING net=clk:      imported=13 (oracle=8,  oracle_rev_bidir=3) … lookup_failed=0
+json2dcp ROUTING net=clk_raw:  imported=20 (oracle=16, oracle_rev_bidir=2) … lookup_failed=0
+```
+
+`lookup_failed=0` on every user net is the success signal.  The
+`oracle_rev_bidir` count records how many PIPs needed
+`setIsReversed(true)` — those are exactly the bidir-direction cases
+that previously failed silently.
+
+### 4. Vivado: DCP → bitstream
+
+Vivado opens the DCP cleanly and reports `pre-route_design`:
+
+| Net | ROUTE_STATUS |
+|---|---|
+| `clk`, `clk_raw`, `q`, `rst_IBUF` | ROUTED |
+| `sysclk_n` | UNROUTED (Vivado fills in) |
+| `led`, `rst`, `sysclk_p`, `q_i_1_n_0` | INTRASITE |
+| `<const0>`, `<const1>` | ROUTED |
+
+We lock the four good user nets, route `sysclk_n` only, downgrade a few
+non-essential DRC checks, and write the bitstream:
+
+```tcl
+# /tmp/write_bit_force.tcl
+open_checkpoint /home/jonathan/min_ibufds_ff_led/nextpnr_pass/top_rw.dcp
+
+foreach n [get_nets -hier] {
+    if {[get_property ROUTE_STATUS $n] == "ROUTED"} {
+        set_property IS_ROUTE_FIXED 1 $n
+    }
+}
+catch {route_design -nets [get_nets sysclk_n]} rerr
+puts "route_design (sysclk_n only): $rerr"
+
+foreach chk {UCIO-1 RTSTAT-5 RTSTAT-2 RTSTAT-1 NSTD-1 LUTLP-1 CFGBVS-1} {
+    catch { set_property IS_ENABLED 0 [get_drc_checks $chk] }
+}
+
+write_bitstream -force /home/jonathan/min_ibufds_ff_led/nextpnr_pass/top_rw.bit
+exit
+```
+
+```bash
+vivado -mode batch -nojournal -nolog -source /tmp/write_bit_force.tcl
+```
+
+Why these flags:
+
+- `IS_ROUTE_FIXED 1` on ROUTED nets prevents `route_design` from
+  unrouting them while it works on `sysclk_n`.  Without the lock,
+  `route_design` regresses `q` and `rst_IBUF` to `ANTENNAS` because
+  of a separate SLICE pin-assignment CRITICAL (`[Route 35-557]
+  q_i_1/I0 A5LUT/A3 not found in siteAssignment`).  That's an open
+  bug, not load-bearing for this design.
+- `route_design -nets [get_nets sysclk_n]` is a per-net route so it
+  doesn't touch the others.
+- `IS_ENABLED 0` disables four DRC checks that fire on cosmetic
+  issues we know about (XDC LOC application timing, CFGBVS prop,
+  LUT loop default, no-IOSTD).
+
+Result: a ~20 MB bitstream at `nextpnr_pass/top_rw.bit`.
+
+### 5. Load on the board
+
+```bash
+~/openFPGALoader/build/openFPGALoader \
+    --freq 15000000 --cable digilent \
+    ~/min_ibufds_ff_led/nextpnr_pass/top_rw.bit
+```
+
+`--freq 15000000` is the validated VC707 JTAG clock; the openFPGALoader
+default of 6 MHz works too but is slower.  The board must be powered
+and the Digilent JTAG cable enumerated (`lsusb` shows a Digilent device).
+
+Expected progress: `Load SRAM: 100.00%` → `Done` → `done 1`.  No errors.
+
+Expected hardware:
+
+- **LED D0** (`GPIO_LED_0`, AM39) dimly oscillating — the FF toggles at
+  `sysclk / 2` ≈ 100 MHz, far too fast to see as discrete blinks but
+  at ~50 % duty cycle so the LED is at roughly half brightness.
+- **Reset** (`CPU_RESET`, AV40) holds the FF in `0` while pressed;
+  release returns to the toggling state.
+
+If LED is stuck on, stuck off, or D1 (the next LED over) lights up
+too, see [Known issues](#known-issues) below.
+
+---
+
+## What's actually doing the heavy lifting
+
+Three pieces of glue, layered:
+
+1. **`xilinx/fasm.cc` phantom-BUFGCTRL filter (this is what made the
+   FASM path work earlier, separately from the DCP work).**  Without
+   it, the FASM emits unused-BUFGCTRL features at
+   `CLK_BUFG_BOT_R_X192Y204` that program contending clock paths and
+   the FF never clocks.
+2. **The wire-name oracle (`build/BuildWireOracle.java`,
+   `build/WireOracle.java`).**  Without it, json2dcp can't resolve
+   bidir-direction PIPs in the clock spine (`CLK_BUFG_REBUF` BIDIR
+   pips at Y221 / Y194 / Y169 / Y142) — silently picks the wrong
+   direction, route ends up incomplete.
+3. **The SITEWIRE→SITEWIRE SitePIP handler in `json2dcp.java`.**
+   Without it, the implicit intra-site selections
+   (`AOUTMUX:A5Q -> AMUX`, `CLKINV:CLK -> OUT`, `A5FFMUX:IN_A -> OUT`,
+   ...) aren't bound on the SiteInst, so the cell pin and the site
+   pin are disconnected and Vivado reports `ANTENNAS` on every
+   affected net.
+
+---
+
+## Known issues (do not block this design, will trip other designs)
+
+1. **SLICE pin-assignment CRITICAL** —
+   `[Route 35-557] resultsCompare: q_i_1/I0 A5LUT/A3 is not found in
+   the siteAssignment results from RuleRoute`.  Vivado's
+   `route_design` aborts mid-route on `SLICE_X46Y122` because the
+   cell-pin → BEL-pin mapping it computes disagrees with what we
+   wrote.  Workaround: lock ROUTED nets before `route_design`.
+
+2. **IOB sitetype-net overwrite CRITICALs** — `[Constraints
+   18-4866]` fires on `IOB_X0Y124` and `IOB_X1Y276` for paths like
+   `OUTBUF_DCIEN_OUT`, `DIFFI_IN`, `PADOUT`.  Default SitePIPs that
+   `createAndPlaceCell` binds (e.g. `OUSED:0 -> OUT` on a pure
+   IBUF) overlap with our explicit nets.  Cosmetic for this
+   design.
+
+3. **UCIO-1 not auto-applied** — XDC LOCs are present in
+   `top_rw.dcp/top.xdc` and on the placed cells (`property LOC` in
+   EDIF), but Vivado's port-LOC DRC didn't pick them up.  Worked
+   around by disabling the DRC; root-cause likely an XDC
+   application-order issue.
+
+---
+
+## Glue tree
+
+The json2dcp / WireOracle / BuildWireOracle sources are tracked in
+`deps/json_drc-portable/src/` (submodule, github.com/jrrk2/json_drc-portable),
+together with dcp2fasm, the opendcp XML tools, and a Makefile that fetches
+the upstream jars and device data:
+
+```
+build/
+  build.sh                  # one-shot compile-and-jar
+  manifest.mf
+  WireOracle.java           # in-process reader for the oracle file
+  BuildWireOracle.java      # offline generator: Device.getDevice() -> oracle
+  json2dcp.java             # nextpnr JSON -> RapidWright Design -> DCP
+  oracle_classes/           # compiled classes
+  rapidwright_json2dcp.jar  # the deliverable
+```
+
+That directory is **not** yet in a git repository.  Plan: move it into
+this repo under `tools/rapidwright_glue/` (or its own repo on the
+openXC7 organisation) so future bisects of the open flow have all
+three layers under version control.
+
+---
+
+## Provenance
+
+- Test design lives at `~/min_ibufds_ff_led/`.
+- Bitstream artefact: `~/min_ibufds_ff_led/nextpnr_pass/top_rw.bit` (20 MB).
+- Oracle artefact: `~/min_ibufds_ff_led/oracle/xc7vx485tffg1761-2.oracle.txt.gz` (2.5 MB).
+- Hardware: VC707 Rev1.1 (`xc7vx485tffg1761-2`).
+- Vivado: 2020.1.
+- nextpnr-xilinx: `virtex7-support` derivative; key commits include
+  `4e6663e` (BUFGCTRL default emission), `10c7372` (atomic CARRY4
+  packer, also tagged `atomic-carry4`), and the in-tree changes to
+  `fasm.cc` + `pack_clocking_xc7.cc` + `pack_io_xc7.cc` referenced
+  above.
+- RapidWright: `2025.2.1`.

database/virtex7/segbits_clbll_l.db

@@ -0,0 +1,714 @@
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+CLBLL_L.SLICEL_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
+CLBLL_L.SLICEL_X0.BOUTMUX.O5 30_20 !30_21 30_22 !30_23
+CLBLL_L.SLICEL_X0.BOUTMUX.O6 30_20 !30_21 !30_22 !30_23
+CLBLL_L.SLICEL_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
+CLBLL_L.SLICEL_X0.C5FFMUX.IN_A 31_45
+CLBLL_L.SLICEL_X0.C5FFMUX.IN_B 30_39
+CLBLL_L.SLICEL_X0.C5FF.ZINI 31_41
+CLBLL_L.SLICEL_X0.C5FF.ZRST 01_47
+CLBLL_L.SLICEL_X0.CARRY4.ACY0 30_15
+CLBLL_L.SLICEL_X0.CARRY4.BCY0 01_15
+CLBLL_L.SLICEL_X0.CARRY4.CCY0 30_48
+CLBLL_L.SLICEL_X0.CARRY4.DCY0 30_49
+CLBLL_L.SLICEL_X0.CEUSEDMUX 01_39
+CLBLL_L.SLICEL_X0.CFFMUX.CX !30_35 30_36 !30_37 !30_38
+CLBLL_L.SLICEL_X0.CFFMUX.CY 30_35 !30_36 30_37 !30_38
+CLBLL_L.SLICEL_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37
+CLBLL_L.SLICEL_X0.CFFMUX.F7 30_35 30_36 !30_37 !30_38
+CLBLL_L.SLICEL_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
+CLBLL_L.SLICEL_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38
+CLBLL_L.SLICEL_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
+CLBLL_L.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
+CLBLL_L.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37
+CLBLL_L.SLICEL_X0.CFF.ZINI 31_33
+CLBLL_L.SLICEL_X0.CFF.ZRST 30_33
+CLBLL_L.SLICEL_X0.CLKINV 01_51
+CLBLL_L.SLICEL_X0.CLUT.INIT[00] 32_47
+CLBLL_L.SLICEL_X0.CLUT.INIT[01] 33_47
+CLBLL_L.SLICEL_X0.CLUT.INIT[02] 32_46
+CLBLL_L.SLICEL_X0.CLUT.INIT[03] 33_46
+CLBLL_L.SLICEL_X0.CLUT.INIT[04] 32_45
+CLBLL_L.SLICEL_X0.CLUT.INIT[05] 33_45
+CLBLL_L.SLICEL_X0.CLUT.INIT[06] 32_44
+CLBLL_L.SLICEL_X0.CLUT.INIT[07] 33_44
+CLBLL_L.SLICEL_X0.CLUT.INIT[08] 35_47
+CLBLL_L.SLICEL_X0.CLUT.INIT[09] 34_47
+CLBLL_L.SLICEL_X0.CLUT.INIT[10] 35_46
+CLBLL_L.SLICEL_X0.CLUT.INIT[11] 34_46
+CLBLL_L.SLICEL_X0.CLUT.INIT[12] 35_45
+CLBLL_L.SLICEL_X0.CLUT.INIT[13] 34_45
+CLBLL_L.SLICEL_X0.CLUT.INIT[14] 35_44
+CLBLL_L.SLICEL_X0.CLUT.INIT[15] 34_44
+CLBLL_L.SLICEL_X0.CLUT.INIT[16] 32_43
+CLBLL_L.SLICEL_X0.CLUT.INIT[17] 33_43
+CLBLL_L.SLICEL_X0.CLUT.INIT[18] 32_42
+CLBLL_L.SLICEL_X0.CLUT.INIT[19] 33_42
+CLBLL_L.SLICEL_X0.CLUT.INIT[20] 32_41
+CLBLL_L.SLICEL_X0.CLUT.INIT[21] 33_41
+CLBLL_L.SLICEL_X0.CLUT.INIT[22] 32_40
+CLBLL_L.SLICEL_X0.CLUT.INIT[23] 33_40
+CLBLL_L.SLICEL_X0.CLUT.INIT[24] 35_43
+CLBLL_L.SLICEL_X0.CLUT.INIT[25] 34_43
+CLBLL_L.SLICEL_X0.CLUT.INIT[26] 35_42
+CLBLL_L.SLICEL_X0.CLUT.INIT[27] 34_42
+CLBLL_L.SLICEL_X0.CLUT.INIT[28] 35_41
+CLBLL_L.SLICEL_X0.CLUT.INIT[29] 34_41
+CLBLL_L.SLICEL_X0.CLUT.INIT[30] 35_40
+CLBLL_L.SLICEL_X0.CLUT.INIT[31] 34_40
+CLBLL_L.SLICEL_X0.CLUT.INIT[32] 32_39
+CLBLL_L.SLICEL_X0.CLUT.INIT[33] 33_39
+CLBLL_L.SLICEL_X0.CLUT.INIT[34] 32_38
+CLBLL_L.SLICEL_X0.CLUT.INIT[35] 33_38
+CLBLL_L.SLICEL_X0.CLUT.INIT[36] 32_37
+CLBLL_L.SLICEL_X0.CLUT.INIT[37] 33_37
+CLBLL_L.SLICEL_X0.CLUT.INIT[38] 32_36
+CLBLL_L.SLICEL_X0.CLUT.INIT[39] 33_36
+CLBLL_L.SLICEL_X0.CLUT.INIT[40] 35_39
+CLBLL_L.SLICEL_X0.CLUT.INIT[41] 34_39
+CLBLL_L.SLICEL_X0.CLUT.INIT[42] 35_38
+CLBLL_L.SLICEL_X0.CLUT.INIT[43] 34_38
+CLBLL_L.SLICEL_X0.CLUT.INIT[44] 35_37
+CLBLL_L.SLICEL_X0.CLUT.INIT[45] 34_37
+CLBLL_L.SLICEL_X0.CLUT.INIT[46] 35_36
+CLBLL_L.SLICEL_X0.CLUT.INIT[47] 34_36
+CLBLL_L.SLICEL_X0.CLUT.INIT[48] 32_35
+CLBLL_L.SLICEL_X0.CLUT.INIT[49] 33_35
+CLBLL_L.SLICEL_X0.CLUT.INIT[50] 32_34
+CLBLL_L.SLICEL_X0.CLUT.INIT[51] 33_34
+CLBLL_L.SLICEL_X0.CLUT.INIT[52] 32_33
+CLBLL_L.SLICEL_X0.CLUT.INIT[53] 33_33
+CLBLL_L.SLICEL_X0.CLUT.INIT[54] 32_32
+CLBLL_L.SLICEL_X0.CLUT.INIT[55] 33_32
+CLBLL_L.SLICEL_X0.CLUT.INIT[56] 35_35
+CLBLL_L.SLICEL_X0.CLUT.INIT[57] 34_35
+CLBLL_L.SLICEL_X0.CLUT.INIT[58] 35_34
+CLBLL_L.SLICEL_X0.CLUT.INIT[59] 34_34
+CLBLL_L.SLICEL_X0.CLUT.INIT[60] 35_33
+CLBLL_L.SLICEL_X0.CLUT.INIT[61] 34_33
+CLBLL_L.SLICEL_X0.CLUT.INIT[62] 35_32
+CLBLL_L.SLICEL_X0.CLUT.INIT[63] 34_32
+CLBLL_L.SLICEL_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
+CLBLL_L.SLICEL_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
+CLBLL_L.SLICEL_X0.COUTMUX.F7 30_40 30_43 !30_44 !30_45
+CLBLL_L.SLICEL_X0.COUTMUX.O5 30_40 !30_43 !30_44 30_45
+CLBLL_L.SLICEL_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
+CLBLL_L.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
+CLBLL_L.SLICEL_X0.D5FFMUX.IN_A 30_55
+CLBLL_L.SLICEL_X0.D5FFMUX.IN_B 30_54
+CLBLL_L.SLICEL_X0.D5FF.ZINI 31_51
+CLBLL_L.SLICEL_X0.D5FF.ZRST 01_55
+CLBLL_L.SLICEL_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
+CLBLL_L.SLICEL_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
+CLBLL_L.SLICEL_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
+CLBLL_L.SLICEL_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61
+CLBLL_L.SLICEL_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
+CLBLL_L.SLICEL_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62
+CLBLL_L.SLICEL_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
+CLBLL_L.SLICEL_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59
+CLBLL_L.SLICEL_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
+CLBLL_L.SLICEL_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60
+CLBLL_L.SLICEL_X0.DFF.ZINI 31_58
+CLBLL_L.SLICEL_X0.DFF.ZRST 30_50
+CLBLL_L.SLICEL_X0.DLUT.INIT[00] 32_63
+CLBLL_L.SLICEL_X0.DLUT.INIT[01] 33_63
+CLBLL_L.SLICEL_X0.DLUT.INIT[02] 32_62
+CLBLL_L.SLICEL_X0.DLUT.INIT[03] 33_62
+CLBLL_L.SLICEL_X0.DLUT.INIT[04] 32_61
+CLBLL_L.SLICEL_X0.DLUT.INIT[05] 33_61
+CLBLL_L.SLICEL_X0.DLUT.INIT[06] 32_60
+CLBLL_L.SLICEL_X0.DLUT.INIT[07] 33_60
+CLBLL_L.SLICEL_X0.DLUT.INIT[08] 35_63
+CLBLL_L.SLICEL_X0.DLUT.INIT[09] 34_63
+CLBLL_L.SLICEL_X0.DLUT.INIT[10] 35_62
+CLBLL_L.SLICEL_X0.DLUT.INIT[11] 34_62
+CLBLL_L.SLICEL_X0.DLUT.INIT[12] 35_61
+CLBLL_L.SLICEL_X0.DLUT.INIT[13] 34_61
+CLBLL_L.SLICEL_X0.DLUT.INIT[14] 35_60
+CLBLL_L.SLICEL_X0.DLUT.INIT[15] 34_60
+CLBLL_L.SLICEL_X0.DLUT.INIT[16] 32_59
+CLBLL_L.SLICEL_X0.DLUT.INIT[17] 33_59
+CLBLL_L.SLICEL_X0.DLUT.INIT[18] 32_58
+CLBLL_L.SLICEL_X0.DLUT.INIT[19] 33_58
+CLBLL_L.SLICEL_X0.DLUT.INIT[20] 32_57
+CLBLL_L.SLICEL_X0.DLUT.INIT[21] 33_57
+CLBLL_L.SLICEL_X0.DLUT.INIT[22] 32_56
+CLBLL_L.SLICEL_X0.DLUT.INIT[23] 33_56
+CLBLL_L.SLICEL_X0.DLUT.INIT[24] 35_59
+CLBLL_L.SLICEL_X0.DLUT.INIT[25] 34_59
+CLBLL_L.SLICEL_X0.DLUT.INIT[26] 35_58
+CLBLL_L.SLICEL_X0.DLUT.INIT[27] 34_58
+CLBLL_L.SLICEL_X0.DLUT.INIT[28] 35_57
+CLBLL_L.SLICEL_X0.DLUT.INIT[29] 34_57
+CLBLL_L.SLICEL_X0.DLUT.INIT[30] 35_56
+CLBLL_L.SLICEL_X0.DLUT.INIT[31] 34_56
+CLBLL_L.SLICEL_X0.DLUT.INIT[32] 32_55
+CLBLL_L.SLICEL_X0.DLUT.INIT[33] 33_55
+CLBLL_L.SLICEL_X0.DLUT.INIT[34] 32_54
+CLBLL_L.SLICEL_X0.DLUT.INIT[35] 33_54
+CLBLL_L.SLICEL_X0.DLUT.INIT[36] 32_53
+CLBLL_L.SLICEL_X0.DLUT.INIT[37] 33_53
+CLBLL_L.SLICEL_X0.DLUT.INIT[38] 32_52
+CLBLL_L.SLICEL_X0.DLUT.INIT[39] 33_52
+CLBLL_L.SLICEL_X0.DLUT.INIT[40] 35_55
+CLBLL_L.SLICEL_X0.DLUT.INIT[41] 34_55
+CLBLL_L.SLICEL_X0.DLUT.INIT[42] 35_54
+CLBLL_L.SLICEL_X0.DLUT.INIT[43] 34_54
+CLBLL_L.SLICEL_X0.DLUT.INIT[44] 35_53
+CLBLL_L.SLICEL_X0.DLUT.INIT[45] 34_53
+CLBLL_L.SLICEL_X0.DLUT.INIT[46] 35_52
+CLBLL_L.SLICEL_X0.DLUT.INIT[47] 34_52
+CLBLL_L.SLICEL_X0.DLUT.INIT[48] 32_51
+CLBLL_L.SLICEL_X0.DLUT.INIT[49] 33_51
+CLBLL_L.SLICEL_X0.DLUT.INIT[50] 32_50
+CLBLL_L.SLICEL_X0.DLUT.INIT[51] 33_50
+CLBLL_L.SLICEL_X0.DLUT.INIT[52] 32_49
+CLBLL_L.SLICEL_X0.DLUT.INIT[53] 33_49
+CLBLL_L.SLICEL_X0.DLUT.INIT[54] 32_48
+CLBLL_L.SLICEL_X0.DLUT.INIT[55] 33_48
+CLBLL_L.SLICEL_X0.DLUT.INIT[56] 35_51
+CLBLL_L.SLICEL_X0.DLUT.INIT[57] 34_51
+CLBLL_L.SLICEL_X0.DLUT.INIT[58] 35_50
+CLBLL_L.SLICEL_X0.DLUT.INIT[59] 34_50
+CLBLL_L.SLICEL_X0.DLUT.INIT[60] 35_49
+CLBLL_L.SLICEL_X0.DLUT.INIT[61] 34_49
+CLBLL_L.SLICEL_X0.DLUT.INIT[62] 35_48
+CLBLL_L.SLICEL_X0.DLUT.INIT[63] 34_48
+CLBLL_L.SLICEL_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
+CLBLL_L.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
+CLBLL_L.SLICEL_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
+CLBLL_L.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
+CLBLL_L.SLICEL_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
+CLBLL_L.SLICEL_X0.FFSYNC 00_48
+CLBLL_L.SLICEL_X0.LATCH 30_32
+CLBLL_L.SLICEL_X0.NOCLKINV !01_51
+CLBLL_L.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
+CLBLL_L.SLICEL_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
+CLBLL_L.SLICEL_X0.PRECYINIT.C1 00_12 !30_13 !30_14
+CLBLL_L.SLICEL_X0.PRECYINIT.C1 !30_13 !30_14 00_12
+CLBLL_L.SLICEL_X0.PRECYINIT.CIN !00_12 30_13 !30_14
+CLBLL_L.SLICEL_X0.PRECYINIT.CIN !00_12 !30_14 30_13
+CLBLL_L.SLICEL_X0.SRUSEDMUX 01_35
+CLBLL_L.SLICEL_X1.A5FFMUX.IN_A 31_08
+CLBLL_L.SLICEL_X1.A5FFMUX.IN_B 31_11
+CLBLL_L.SLICEL_X1.A5FF.ZINI 31_05
+CLBLL_L.SLICEL_X1.A5FF.ZRST 01_03
+CLBLL_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 31_01 !31_02
+CLBLL_L.SLICEL_X1.AFFMUX.CY !30_04 31_00 !31_01 31_02
+CLBLL_L.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02
+CLBLL_L.SLICEL_X1.AFFMUX.F7 !30_04 31_00 31_01 !31_02
+CLBLL_L.SLICEL_X1.AFFMUX.O5 30_04 31_00 !31_01 !31_02
+CLBLL_L.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00
+CLBLL_L.SLICEL_X1.AFFMUX.O6 30_04 !31_00 !31_01 !31_02
+CLBLL_L.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04
+CLBLL_L.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
+CLBLL_L.SLICEL_X1.AFF.ZINI 31_04
+CLBLL_L.SLICEL_X1.AFF.ZRST 31_15
+CLBLL_L.SLICEL_X1.ALUT.INIT[00] 26_15
+CLBLL_L.SLICEL_X1.ALUT.INIT[01] 27_15
+CLBLL_L.SLICEL_X1.ALUT.INIT[02] 26_14
+CLBLL_L.SLICEL_X1.ALUT.INIT[03] 27_14
+CLBLL_L.SLICEL_X1.ALUT.INIT[04] 26_13
+CLBLL_L.SLICEL_X1.ALUT.INIT[05] 27_13
+CLBLL_L.SLICEL_X1.ALUT.INIT[06] 26_12
+CLBLL_L.SLICEL_X1.ALUT.INIT[07] 27_12
+CLBLL_L.SLICEL_X1.ALUT.INIT[08] 29_15
+CLBLL_L.SLICEL_X1.ALUT.INIT[09] 28_15
+CLBLL_L.SLICEL_X1.ALUT.INIT[10] 29_14
+CLBLL_L.SLICEL_X1.ALUT.INIT[11] 28_14
+CLBLL_L.SLICEL_X1.ALUT.INIT[12] 29_13
+CLBLL_L.SLICEL_X1.ALUT.INIT[13] 28_13
+CLBLL_L.SLICEL_X1.ALUT.INIT[14] 29_12
+CLBLL_L.SLICEL_X1.ALUT.INIT[15] 28_12
+CLBLL_L.SLICEL_X1.ALUT.INIT[16] 26_11
+CLBLL_L.SLICEL_X1.ALUT.INIT[17] 27_11
+CLBLL_L.SLICEL_X1.ALUT.INIT[18] 26_10
+CLBLL_L.SLICEL_X1.ALUT.INIT[19] 27_10
+CLBLL_L.SLICEL_X1.ALUT.INIT[20] 26_09
+CLBLL_L.SLICEL_X1.ALUT.INIT[21] 27_09
+CLBLL_L.SLICEL_X1.ALUT.INIT[22] 26_08
+CLBLL_L.SLICEL_X1.ALUT.INIT[23] 27_08
+CLBLL_L.SLICEL_X1.ALUT.INIT[24] 29_11
+CLBLL_L.SLICEL_X1.ALUT.INIT[25] 28_11
+CLBLL_L.SLICEL_X1.ALUT.INIT[26] 29_10
+CLBLL_L.SLICEL_X1.ALUT.INIT[27] 28_10
+CLBLL_L.SLICEL_X1.ALUT.INIT[28] 29_09
+CLBLL_L.SLICEL_X1.ALUT.INIT[29] 28_09
+CLBLL_L.SLICEL_X1.ALUT.INIT[30] 29_08
+CLBLL_L.SLICEL_X1.ALUT.INIT[31] 28_08
+CLBLL_L.SLICEL_X1.ALUT.INIT[32] 26_07
+CLBLL_L.SLICEL_X1.ALUT.INIT[33] 27_07
+CLBLL_L.SLICEL_X1.ALUT.INIT[34] 26_06
+CLBLL_L.SLICEL_X1.ALUT.INIT[35] 27_06
+CLBLL_L.SLICEL_X1.ALUT.INIT[36] 26_05
+CLBLL_L.SLICEL_X1.ALUT.INIT[37] 27_05
+CLBLL_L.SLICEL_X1.ALUT.INIT[38] 26_04
+CLBLL_L.SLICEL_X1.ALUT.INIT[39] 27_04
+CLBLL_L.SLICEL_X1.ALUT.INIT[40] 29_07
+CLBLL_L.SLICEL_X1.ALUT.INIT[41] 28_07
+CLBLL_L.SLICEL_X1.ALUT.INIT[42] 29_06
+CLBLL_L.SLICEL_X1.ALUT.INIT[43] 28_06
+CLBLL_L.SLICEL_X1.ALUT.INIT[44] 29_05
+CLBLL_L.SLICEL_X1.ALUT.INIT[45] 28_05
+CLBLL_L.SLICEL_X1.ALUT.INIT[46] 29_04
+CLBLL_L.SLICEL_X1.ALUT.INIT[47] 28_04
+CLBLL_L.SLICEL_X1.ALUT.INIT[48] 26_03
+CLBLL_L.SLICEL_X1.ALUT.INIT[49] 27_03
+CLBLL_L.SLICEL_X1.ALUT.INIT[50] 26_02
+CLBLL_L.SLICEL_X1.ALUT.INIT[51] 27_02
+CLBLL_L.SLICEL_X1.ALUT.INIT[52] 26_01
+CLBLL_L.SLICEL_X1.ALUT.INIT[53] 27_01
+CLBLL_L.SLICEL_X1.ALUT.INIT[54] 26_00
+CLBLL_L.SLICEL_X1.ALUT.INIT[55] 27_00
+CLBLL_L.SLICEL_X1.ALUT.INIT[56] 29_03
+CLBLL_L.SLICEL_X1.ALUT.INIT[57] 28_03
+CLBLL_L.SLICEL_X1.ALUT.INIT[58] 29_02
+CLBLL_L.SLICEL_X1.ALUT.INIT[59] 28_02
+CLBLL_L.SLICEL_X1.ALUT.INIT[60] 29_01
+CLBLL_L.SLICEL_X1.ALUT.INIT[61] 28_01
+CLBLL_L.SLICEL_X1.ALUT.INIT[62] 29_00
+CLBLL_L.SLICEL_X1.ALUT.INIT[63] 28_00
+CLBLL_L.SLICEL_X1.AOUTMUX.A5Q 30_05 !31_07 !31_09 !31_10
+CLBLL_L.SLICEL_X1.AOUTMUX.CY !30_05 31_07 !31_09 31_10
+CLBLL_L.SLICEL_X1.AOUTMUX.F7 30_05 !31_07 !31_09 31_10
+CLBLL_L.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
+CLBLL_L.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 31_09 !31_10
+CLBLL_L.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
+CLBLL_L.SLICEL_X1.B5FFMUX.IN_A 31_19
+CLBLL_L.SLICEL_X1.B5FFMUX.IN_B 31_18
+CLBLL_L.SLICEL_X1.B5FF.ZINI 31_23
+CLBLL_L.SLICEL_X1.B5FF.ZRST 00_16
+CLBLL_L.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
+CLBLL_L.SLICEL_X1.BFFMUX.CY !31_24 31_25 31_26 !31_27
+CLBLL_L.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26
+CLBLL_L.SLICEL_X1.BFFMUX.F8 !31_24 31_25 !31_26 31_27
+CLBLL_L.SLICEL_X1.BFFMUX.O5 31_24 31_25 !31_26 !31_27
+CLBLL_L.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25
+CLBLL_L.SLICEL_X1.BFFMUX.O6 31_24 !31_25 !31_26 !31_27
+CLBLL_L.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24
+CLBLL_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
+CLBLL_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26
+CLBLL_L.SLICEL_X1.BFF.ZINI 31_29
+CLBLL_L.SLICEL_X1.BFF.ZRST 31_30
+CLBLL_L.SLICEL_X1.BLUT.INIT[00] 26_31
+CLBLL_L.SLICEL_X1.BLUT.INIT[01] 27_31
+CLBLL_L.SLICEL_X1.BLUT.INIT[02] 26_30
+CLBLL_L.SLICEL_X1.BLUT.INIT[03] 27_30
+CLBLL_L.SLICEL_X1.BLUT.INIT[04] 26_29
+CLBLL_L.SLICEL_X1.BLUT.INIT[05] 27_29
+CLBLL_L.SLICEL_X1.BLUT.INIT[06] 26_28
+CLBLL_L.SLICEL_X1.BLUT.INIT[07] 27_28
+CLBLL_L.SLICEL_X1.BLUT.INIT[08] 29_31
+CLBLL_L.SLICEL_X1.BLUT.INIT[09] 28_31
+CLBLL_L.SLICEL_X1.BLUT.INIT[10] 29_30
+CLBLL_L.SLICEL_X1.BLUT.INIT[11] 28_30
+CLBLL_L.SLICEL_X1.BLUT.INIT[12] 29_29
+CLBLL_L.SLICEL_X1.BLUT.INIT[13] 28_29
+CLBLL_L.SLICEL_X1.BLUT.INIT[14] 29_28
+CLBLL_L.SLICEL_X1.BLUT.INIT[15] 28_28
+CLBLL_L.SLICEL_X1.BLUT.INIT[16] 26_27
+CLBLL_L.SLICEL_X1.BLUT.INIT[17] 27_27
+CLBLL_L.SLICEL_X1.BLUT.INIT[18] 26_26
+CLBLL_L.SLICEL_X1.BLUT.INIT[19] 27_26
+CLBLL_L.SLICEL_X1.BLUT.INIT[20] 26_25
+CLBLL_L.SLICEL_X1.BLUT.INIT[21] 27_25
+CLBLL_L.SLICEL_X1.BLUT.INIT[22] 26_24
+CLBLL_L.SLICEL_X1.BLUT.INIT[23] 27_24
+CLBLL_L.SLICEL_X1.BLUT.INIT[24] 29_27
+CLBLL_L.SLICEL_X1.BLUT.INIT[25] 28_27
+CLBLL_L.SLICEL_X1.BLUT.INIT[26] 29_26
+CLBLL_L.SLICEL_X1.BLUT.INIT[27] 28_26
+CLBLL_L.SLICEL_X1.BLUT.INIT[28] 29_25
+CLBLL_L.SLICEL_X1.BLUT.INIT[29] 28_25
+CLBLL_L.SLICEL_X1.BLUT.INIT[30] 29_24
+CLBLL_L.SLICEL_X1.BLUT.INIT[31] 28_24
+CLBLL_L.SLICEL_X1.BLUT.INIT[32] 26_23
+CLBLL_L.SLICEL_X1.BLUT.INIT[33] 27_23
+CLBLL_L.SLICEL_X1.BLUT.INIT[34] 26_22
+CLBLL_L.SLICEL_X1.BLUT.INIT[35] 27_22
+CLBLL_L.SLICEL_X1.BLUT.INIT[36] 26_21
+CLBLL_L.SLICEL_X1.BLUT.INIT[37] 27_21
+CLBLL_L.SLICEL_X1.BLUT.INIT[38] 26_20
+CLBLL_L.SLICEL_X1.BLUT.INIT[39] 27_20
+CLBLL_L.SLICEL_X1.BLUT.INIT[40] 29_23
+CLBLL_L.SLICEL_X1.BLUT.INIT[41] 28_23
+CLBLL_L.SLICEL_X1.BLUT.INIT[42] 29_22
+CLBLL_L.SLICEL_X1.BLUT.INIT[43] 28_22
+CLBLL_L.SLICEL_X1.BLUT.INIT[44] 29_21
+CLBLL_L.SLICEL_X1.BLUT.INIT[45] 28_21
+CLBLL_L.SLICEL_X1.BLUT.INIT[46] 29_20
+CLBLL_L.SLICEL_X1.BLUT.INIT[47] 28_20
+CLBLL_L.SLICEL_X1.BLUT.INIT[48] 26_19
+CLBLL_L.SLICEL_X1.BLUT.INIT[49] 27_19
+CLBLL_L.SLICEL_X1.BLUT.INIT[50] 26_18
+CLBLL_L.SLICEL_X1.BLUT.INIT[51] 27_18
+CLBLL_L.SLICEL_X1.BLUT.INIT[52] 26_17
+CLBLL_L.SLICEL_X1.BLUT.INIT[53] 27_17
+CLBLL_L.SLICEL_X1.BLUT.INIT[54] 26_16
+CLBLL_L.SLICEL_X1.BLUT.INIT[55] 27_16
+CLBLL_L.SLICEL_X1.BLUT.INIT[56] 29_19
+CLBLL_L.SLICEL_X1.BLUT.INIT[57] 28_19
+CLBLL_L.SLICEL_X1.BLUT.INIT[58] 29_18
+CLBLL_L.SLICEL_X1.BLUT.INIT[59] 28_18
+CLBLL_L.SLICEL_X1.BLUT.INIT[60] 29_17
+CLBLL_L.SLICEL_X1.BLUT.INIT[61] 28_17
+CLBLL_L.SLICEL_X1.BLUT.INIT[62] 29_16
+CLBLL_L.SLICEL_X1.BLUT.INIT[63] 28_16
+CLBLL_L.SLICEL_X1.BOUTMUX.B5Q !30_28 30_29 !31_20 !31_21
+CLBLL_L.SLICEL_X1.BOUTMUX.CY 30_28 !30_29 !31_20 31_21
+CLBLL_L.SLICEL_X1.BOUTMUX.F8 !30_28 30_29 !31_20 31_21
+CLBLL_L.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
+CLBLL_L.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 31_20 !31_21
+CLBLL_L.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
+CLBLL_L.SLICEL_X1.C5FFMUX.IN_A 31_44
+CLBLL_L.SLICEL_X1.C5FFMUX.IN_B 31_39
+CLBLL_L.SLICEL_X1.C5FF.ZINI 31_42
+CLBLL_L.SLICEL_X1.C5FF.ZRST 00_44
+CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_14
+CLBLL_L.SLICEL_X1.CARRY4.BCY0 00_08
+CLBLL_L.SLICEL_X1.CARRY4.CCY0 31_48
+CLBLL_L.SLICEL_X1.CARRY4.DCY0 31_49
+CLBLL_L.SLICEL_X1.CEUSEDMUX 00_36
+CLBLL_L.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
+CLBLL_L.SLICEL_X1.CFFMUX.CY 31_35 !31_36 31_37 !31_38
+CLBLL_L.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37
+CLBLL_L.SLICEL_X1.CFFMUX.F7 31_35 !31_36 !31_37 31_38
+CLBLL_L.SLICEL_X1.CFFMUX.O5 31_35 31_36 !31_37 !31_38
+CLBLL_L.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36
+CLBLL_L.SLICEL_X1.CFFMUX.O6 !31_35 31_36 !31_37 !31_38
+CLBLL_L.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36
+CLBLL_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
+CLBLL_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37
+CLBLL_L.SLICEL_X1.CFF.ZINI 31_34
+CLBLL_L.SLICEL_X1.CFF.ZRST 30_34
+CLBLL_L.SLICEL_X1.CLKINV 00_52
+CLBLL_L.SLICEL_X1.CLUT.INIT[00] 26_47
+CLBLL_L.SLICEL_X1.CLUT.INIT[01] 27_47
+CLBLL_L.SLICEL_X1.CLUT.INIT[02] 26_46
+CLBLL_L.SLICEL_X1.CLUT.INIT[03] 27_46
+CLBLL_L.SLICEL_X1.CLUT.INIT[04] 26_45
+CLBLL_L.SLICEL_X1.CLUT.INIT[05] 27_45
+CLBLL_L.SLICEL_X1.CLUT.INIT[06] 26_44
+CLBLL_L.SLICEL_X1.CLUT.INIT[07] 27_44
+CLBLL_L.SLICEL_X1.CLUT.INIT[08] 29_47
+CLBLL_L.SLICEL_X1.CLUT.INIT[09] 28_47
+CLBLL_L.SLICEL_X1.CLUT.INIT[10] 29_46
+CLBLL_L.SLICEL_X1.CLUT.INIT[11] 28_46
+CLBLL_L.SLICEL_X1.CLUT.INIT[12] 29_45
+CLBLL_L.SLICEL_X1.CLUT.INIT[13] 28_45
+CLBLL_L.SLICEL_X1.CLUT.INIT[14] 29_44
+CLBLL_L.SLICEL_X1.CLUT.INIT[15] 28_44
+CLBLL_L.SLICEL_X1.CLUT.INIT[16] 26_43
+CLBLL_L.SLICEL_X1.CLUT.INIT[17] 27_43
+CLBLL_L.SLICEL_X1.CLUT.INIT[18] 26_42
+CLBLL_L.SLICEL_X1.CLUT.INIT[19] 27_42
+CLBLL_L.SLICEL_X1.CLUT.INIT[20] 26_41
+CLBLL_L.SLICEL_X1.CLUT.INIT[21] 27_41
+CLBLL_L.SLICEL_X1.CLUT.INIT[22] 26_40
+CLBLL_L.SLICEL_X1.CLUT.INIT[23] 27_40
+CLBLL_L.SLICEL_X1.CLUT.INIT[24] 29_43
+CLBLL_L.SLICEL_X1.CLUT.INIT[25] 28_43
+CLBLL_L.SLICEL_X1.CLUT.INIT[26] 29_42
+CLBLL_L.SLICEL_X1.CLUT.INIT[27] 28_42
+CLBLL_L.SLICEL_X1.CLUT.INIT[28] 29_41
+CLBLL_L.SLICEL_X1.CLUT.INIT[29] 28_41
+CLBLL_L.SLICEL_X1.CLUT.INIT[30] 29_40
+CLBLL_L.SLICEL_X1.CLUT.INIT[31] 28_40
+CLBLL_L.SLICEL_X1.CLUT.INIT[32] 26_39
+CLBLL_L.SLICEL_X1.CLUT.INIT[33] 27_39
+CLBLL_L.SLICEL_X1.CLUT.INIT[34] 26_38
+CLBLL_L.SLICEL_X1.CLUT.INIT[35] 27_38
+CLBLL_L.SLICEL_X1.CLUT.INIT[36] 26_37
+CLBLL_L.SLICEL_X1.CLUT.INIT[37] 27_37
+CLBLL_L.SLICEL_X1.CLUT.INIT[38] 26_36
+CLBLL_L.SLICEL_X1.CLUT.INIT[39] 27_36
+CLBLL_L.SLICEL_X1.CLUT.INIT[40] 29_39
+CLBLL_L.SLICEL_X1.CLUT.INIT[41] 28_39
+CLBLL_L.SLICEL_X1.CLUT.INIT[42] 29_38
+CLBLL_L.SLICEL_X1.CLUT.INIT[43] 28_38
+CLBLL_L.SLICEL_X1.CLUT.INIT[44] 29_37
+CLBLL_L.SLICEL_X1.CLUT.INIT[45] 28_37
+CLBLL_L.SLICEL_X1.CLUT.INIT[46] 29_36
+CLBLL_L.SLICEL_X1.CLUT.INIT[47] 28_36
+CLBLL_L.SLICEL_X1.CLUT.INIT[48] 26_35
+CLBLL_L.SLICEL_X1.CLUT.INIT[49] 27_35
+CLBLL_L.SLICEL_X1.CLUT.INIT[50] 26_34
+CLBLL_L.SLICEL_X1.CLUT.INIT[51] 27_34
+CLBLL_L.SLICEL_X1.CLUT.INIT[52] 26_33
+CLBLL_L.SLICEL_X1.CLUT.INIT[53] 27_33
+CLBLL_L.SLICEL_X1.CLUT.INIT[54] 26_32
+CLBLL_L.SLICEL_X1.CLUT.INIT[55] 27_32
+CLBLL_L.SLICEL_X1.CLUT.INIT[56] 29_35
+CLBLL_L.SLICEL_X1.CLUT.INIT[57] 28_35
+CLBLL_L.SLICEL_X1.CLUT.INIT[58] 29_34
+CLBLL_L.SLICEL_X1.CLUT.INIT[59] 28_34
+CLBLL_L.SLICEL_X1.CLUT.INIT[60] 29_33
+CLBLL_L.SLICEL_X1.CLUT.INIT[61] 28_33
+CLBLL_L.SLICEL_X1.CLUT.INIT[62] 29_32
+CLBLL_L.SLICEL_X1.CLUT.INIT[63] 28_32
+CLBLL_L.SLICEL_X1.COUTMUX.C5Q 30_41 !30_42 !31_40 !31_43
+CLBLL_L.SLICEL_X1.COUTMUX.CY !30_41 30_42 31_40 !31_43
+CLBLL_L.SLICEL_X1.COUTMUX.F7 30_41 !30_42 31_40 !31_43
+CLBLL_L.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
+CLBLL_L.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
+CLBLL_L.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
+CLBLL_L.SLICEL_X1.D5FFMUX.IN_A 31_55
+CLBLL_L.SLICEL_X1.D5FFMUX.IN_B 31_54
+CLBLL_L.SLICEL_X1.D5FF.ZINI 31_52
+CLBLL_L.SLICEL_X1.D5FF.ZRST 00_56
+CLBLL_L.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
+CLBLL_L.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
+CLBLL_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 31_61 !31_62
+CLBLL_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61
+CLBLL_L.SLICEL_X1.DFFMUX.O5 30_58 31_60 !31_61 !31_62
+CLBLL_L.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60
+CLBLL_L.SLICEL_X1.DFFMUX.O6 !30_58 31_60 !31_61 !31_62
+CLBLL_L.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60
+CLBLL_L.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
+CLBLL_L.SLICEL_X1.DFF.ZINI 31_59
+CLBLL_L.SLICEL_X1.DFF.ZRST 31_50
+CLBLL_L.SLICEL_X1.DLUT.INIT[00] 26_63
+CLBLL_L.SLICEL_X1.DLUT.INIT[01] 27_63
+CLBLL_L.SLICEL_X1.DLUT.INIT[02] 26_62
+CLBLL_L.SLICEL_X1.DLUT.INIT[03] 27_62
+CLBLL_L.SLICEL_X1.DLUT.INIT[04] 26_61
+CLBLL_L.SLICEL_X1.DLUT.INIT[05] 27_61
+CLBLL_L.SLICEL_X1.DLUT.INIT[06] 26_60
+CLBLL_L.SLICEL_X1.DLUT.INIT[07] 27_60
+CLBLL_L.SLICEL_X1.DLUT.INIT[08] 29_63
+CLBLL_L.SLICEL_X1.DLUT.INIT[09] 28_63
+CLBLL_L.SLICEL_X1.DLUT.INIT[10] 29_62
+CLBLL_L.SLICEL_X1.DLUT.INIT[11] 28_62
+CLBLL_L.SLICEL_X1.DLUT.INIT[12] 29_61
+CLBLL_L.SLICEL_X1.DLUT.INIT[13] 28_61
+CLBLL_L.SLICEL_X1.DLUT.INIT[14] 29_60
+CLBLL_L.SLICEL_X1.DLUT.INIT[15] 28_60
+CLBLL_L.SLICEL_X1.DLUT.INIT[16] 26_59
+CLBLL_L.SLICEL_X1.DLUT.INIT[17] 27_59
+CLBLL_L.SLICEL_X1.DLUT.INIT[18] 26_58
+CLBLL_L.SLICEL_X1.DLUT.INIT[19] 27_58
+CLBLL_L.SLICEL_X1.DLUT.INIT[20] 26_57
+CLBLL_L.SLICEL_X1.DLUT.INIT[21] 27_57
+CLBLL_L.SLICEL_X1.DLUT.INIT[22] 26_56
+CLBLL_L.SLICEL_X1.DLUT.INIT[23] 27_56
+CLBLL_L.SLICEL_X1.DLUT.INIT[24] 29_59
+CLBLL_L.SLICEL_X1.DLUT.INIT[25] 28_59
+CLBLL_L.SLICEL_X1.DLUT.INIT[26] 29_58
+CLBLL_L.SLICEL_X1.DLUT.INIT[27] 28_58
+CLBLL_L.SLICEL_X1.DLUT.INIT[28] 29_57
+CLBLL_L.SLICEL_X1.DLUT.INIT[29] 28_57
+CLBLL_L.SLICEL_X1.DLUT.INIT[30] 29_56
+CLBLL_L.SLICEL_X1.DLUT.INIT[31] 28_56
+CLBLL_L.SLICEL_X1.DLUT.INIT[32] 26_55
+CLBLL_L.SLICEL_X1.DLUT.INIT[33] 27_55
+CLBLL_L.SLICEL_X1.DLUT.INIT[34] 26_54
+CLBLL_L.SLICEL_X1.DLUT.INIT[35] 27_54
+CLBLL_L.SLICEL_X1.DLUT.INIT[36] 26_53
+CLBLL_L.SLICEL_X1.DLUT.INIT[37] 27_53
+CLBLL_L.SLICEL_X1.DLUT.INIT[38] 26_52
+CLBLL_L.SLICEL_X1.DLUT.INIT[39] 27_52
+CLBLL_L.SLICEL_X1.DLUT.INIT[40] 29_55
+CLBLL_L.SLICEL_X1.DLUT.INIT[41] 28_55
+CLBLL_L.SLICEL_X1.DLUT.INIT[42] 29_54
+CLBLL_L.SLICEL_X1.DLUT.INIT[43] 28_54
+CLBLL_L.SLICEL_X1.DLUT.INIT[44] 29_53
+CLBLL_L.SLICEL_X1.DLUT.INIT[45] 28_53
+CLBLL_L.SLICEL_X1.DLUT.INIT[46] 29_52
+CLBLL_L.SLICEL_X1.DLUT.INIT[47] 28_52
+CLBLL_L.SLICEL_X1.DLUT.INIT[48] 26_51
+CLBLL_L.SLICEL_X1.DLUT.INIT[49] 27_51
+CLBLL_L.SLICEL_X1.DLUT.INIT[50] 26_50
+CLBLL_L.SLICEL_X1.DLUT.INIT[51] 27_50
+CLBLL_L.SLICEL_X1.DLUT.INIT[52] 26_49
+CLBLL_L.SLICEL_X1.DLUT.INIT[53] 27_49
+CLBLL_L.SLICEL_X1.DLUT.INIT[54] 26_48
+CLBLL_L.SLICEL_X1.DLUT.INIT[55] 27_48
+CLBLL_L.SLICEL_X1.DLUT.INIT[56] 29_51
+CLBLL_L.SLICEL_X1.DLUT.INIT[57] 28_51
+CLBLL_L.SLICEL_X1.DLUT.INIT[58] 29_50
+CLBLL_L.SLICEL_X1.DLUT.INIT[59] 28_50
+CLBLL_L.SLICEL_X1.DLUT.INIT[60] 29_49
+CLBLL_L.SLICEL_X1.DLUT.INIT[61] 28_49
+CLBLL_L.SLICEL_X1.DLUT.INIT[62] 29_48
+CLBLL_L.SLICEL_X1.DLUT.INIT[63] 28_48
+CLBLL_L.SLICEL_X1.DOUTMUX.CY 30_53 !31_53 !31_56 31_57
+CLBLL_L.SLICEL_X1.DOUTMUX.D5Q !30_53 31_53 !31_56 !31_57
+CLBLL_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
+CLBLL_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
+CLBLL_L.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
+CLBLL_L.SLICEL_X1.FFSYNC 01_31
+CLBLL_L.SLICEL_X1.LATCH 31_32
+CLBLL_L.SLICEL_X1.NOCLKINV !00_52
+CLBLL_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
+CLBLL_L.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
+CLBLL_L.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
+CLBLL_L.SLICEL_X1.PRECYINIT.C1 !31_12 !31_13 01_11
+CLBLL_L.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
+CLBLL_L.SLICEL_X1.PRECYINIT.CIN !01_11 !31_13 31_12
+CLBLL_L.SLICEL_X1.SRUSEDMUX 00_32

database/virtex7/segbits_clbll_r.db

@@ -0,0 +1,714 @@
+CLBLL_R.SLICEL_X0.A5FFMUX.IN_A 30_09
+CLBLL_R.SLICEL_X0.A5FFMUX.IN_B 30_10
+CLBLL_R.SLICEL_X0.A5FF.ZINI 31_06
+CLBLL_R.SLICEL_X0.A5FF.ZRST 01_07
+CLBLL_R.SLICEL_X0.AFFMUX.AX !30_00 30_01 !30_02 !30_03
+CLBLL_R.SLICEL_X0.AFFMUX.CY 30_00 !30_01 30_02 !30_03
+CLBLL_R.SLICEL_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02
+CLBLL_R.SLICEL_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
+CLBLL_R.SLICEL_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
+CLBLL_R.SLICEL_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03
+CLBLL_R.SLICEL_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
+CLBLL_R.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
+CLBLL_R.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02
+CLBLL_R.SLICEL_X0.AFF.ZINI 31_03
+CLBLL_R.SLICEL_X0.AFF.ZRST 30_12
+CLBLL_R.SLICEL_X0.ALUT.INIT[00] 32_15
+CLBLL_R.SLICEL_X0.ALUT.INIT[01] 33_15
+CLBLL_R.SLICEL_X0.ALUT.INIT[02] 32_14
+CLBLL_R.SLICEL_X0.ALUT.INIT[03] 33_14
+CLBLL_R.SLICEL_X0.ALUT.INIT[04] 32_13
+CLBLL_R.SLICEL_X0.ALUT.INIT[05] 33_13
+CLBLL_R.SLICEL_X0.ALUT.INIT[06] 32_12
+CLBLL_R.SLICEL_X0.ALUT.INIT[07] 33_12
+CLBLL_R.SLICEL_X0.ALUT.INIT[08] 35_15
+CLBLL_R.SLICEL_X0.ALUT.INIT[09] 34_15
+CLBLL_R.SLICEL_X0.ALUT.INIT[10] 35_14
+CLBLL_R.SLICEL_X0.ALUT.INIT[11] 34_14
+CLBLL_R.SLICEL_X0.ALUT.INIT[12] 35_13
+CLBLL_R.SLICEL_X0.ALUT.INIT[13] 34_13
+CLBLL_R.SLICEL_X0.ALUT.INIT[14] 35_12
+CLBLL_R.SLICEL_X0.ALUT.INIT[15] 34_12
+CLBLL_R.SLICEL_X0.ALUT.INIT[16] 32_11
+CLBLL_R.SLICEL_X0.ALUT.INIT[17] 33_11
+CLBLL_R.SLICEL_X0.ALUT.INIT[18] 32_10
+CLBLL_R.SLICEL_X0.ALUT.INIT[19] 33_10
+CLBLL_R.SLICEL_X0.ALUT.INIT[20] 32_09
+CLBLL_R.SLICEL_X0.ALUT.INIT[21] 33_09
+CLBLL_R.SLICEL_X0.ALUT.INIT[22] 32_08
+CLBLL_R.SLICEL_X0.ALUT.INIT[23] 33_08
+CLBLL_R.SLICEL_X0.ALUT.INIT[24] 35_11
+CLBLL_R.SLICEL_X0.ALUT.INIT[25] 34_11
+CLBLL_R.SLICEL_X0.ALUT.INIT[26] 35_10
+CLBLL_R.SLICEL_X0.ALUT.INIT[27] 34_10
+CLBLL_R.SLICEL_X0.ALUT.INIT[28] 35_09
+CLBLL_R.SLICEL_X0.ALUT.INIT[29] 34_09
+CLBLL_R.SLICEL_X0.ALUT.INIT[30] 35_08
+CLBLL_R.SLICEL_X0.ALUT.INIT[31] 34_08
+CLBLL_R.SLICEL_X0.ALUT.INIT[32] 32_07
+CLBLL_R.SLICEL_X0.ALUT.INIT[33] 33_07
+CLBLL_R.SLICEL_X0.ALUT.INIT[34] 32_06
+CLBLL_R.SLICEL_X0.ALUT.INIT[35] 33_06
+CLBLL_R.SLICEL_X0.ALUT.INIT[36] 32_05
+CLBLL_R.SLICEL_X0.ALUT.INIT[37] 33_05
+CLBLL_R.SLICEL_X0.ALUT.INIT[38] 32_04
+CLBLL_R.SLICEL_X0.ALUT.INIT[39] 33_04
+CLBLL_R.SLICEL_X0.ALUT.INIT[40] 35_07
+CLBLL_R.SLICEL_X0.ALUT.INIT[41] 34_07
+CLBLL_R.SLICEL_X0.ALUT.INIT[42] 35_06
+CLBLL_R.SLICEL_X0.ALUT.INIT[43] 34_06
+CLBLL_R.SLICEL_X0.ALUT.INIT[44] 35_05
+CLBLL_R.SLICEL_X0.ALUT.INIT[45] 34_05
+CLBLL_R.SLICEL_X0.ALUT.INIT[46] 35_04
+CLBLL_R.SLICEL_X0.ALUT.INIT[47] 34_04
+CLBLL_R.SLICEL_X0.ALUT.INIT[48] 32_03
+CLBLL_R.SLICEL_X0.ALUT.INIT[49] 33_03
+CLBLL_R.SLICEL_X0.ALUT.INIT[50] 32_02
+CLBLL_R.SLICEL_X0.ALUT.INIT[51] 33_02
+CLBLL_R.SLICEL_X0.ALUT.INIT[52] 32_01
+CLBLL_R.SLICEL_X0.ALUT.INIT[53] 33_01
+CLBLL_R.SLICEL_X0.ALUT.INIT[54] 32_00
+CLBLL_R.SLICEL_X0.ALUT.INIT[55] 33_00
+CLBLL_R.SLICEL_X0.ALUT.INIT[56] 35_03
+CLBLL_R.SLICEL_X0.ALUT.INIT[57] 34_03
+CLBLL_R.SLICEL_X0.ALUT.INIT[58] 35_02
+CLBLL_R.SLICEL_X0.ALUT.INIT[59] 34_02
+CLBLL_R.SLICEL_X0.ALUT.INIT[60] 35_01
+CLBLL_R.SLICEL_X0.ALUT.INIT[61] 34_01
+CLBLL_R.SLICEL_X0.ALUT.INIT[62] 35_00
+CLBLL_R.SLICEL_X0.ALUT.INIT[63] 34_00
+CLBLL_R.SLICEL_X0.AOUTMUX.A5Q !30_06 30_07 !30_08 !30_11
+CLBLL_R.SLICEL_X0.AOUTMUX.CY 30_06 !30_07 30_08 !30_11
+CLBLL_R.SLICEL_X0.AOUTMUX.F7 30_06 30_07 !30_08 !30_11
+CLBLL_R.SLICEL_X0.AOUTMUX.O5 30_06 !30_07 !30_08 30_11
+CLBLL_R.SLICEL_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
+CLBLL_R.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
+CLBLL_R.SLICEL_X0.B5FFMUX.IN_A 30_19
+CLBLL_R.SLICEL_X0.B5FFMUX.IN_B 30_18
+CLBLL_R.SLICEL_X0.B5FF.ZINI 31_22
+CLBLL_R.SLICEL_X0.B5FF.ZRST 01_19
+CLBLL_R.SLICEL_X0.BFFMUX.BX !30_24 !30_25 30_26 !30_27
+CLBLL_R.SLICEL_X0.BFFMUX.CY !30_24 30_25 !30_26 30_27
+CLBLL_R.SLICEL_X0.BFFMUX.CY !30_24 !30_26 30_25 30_27
+CLBLL_R.SLICEL_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
+CLBLL_R.SLICEL_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
+CLBLL_R.SLICEL_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27
+CLBLL_R.SLICEL_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
+CLBLL_R.SLICEL_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24
+CLBLL_R.SLICEL_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
+CLBLL_R.SLICEL_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25
+CLBLL_R.SLICEL_X0.BFF.ZINI 31_28
+CLBLL_R.SLICEL_X0.BFF.ZRST 30_30
+CLBLL_R.SLICEL_X0.BLUT.INIT[00] 32_31
+CLBLL_R.SLICEL_X0.BLUT.INIT[01] 33_31
+CLBLL_R.SLICEL_X0.BLUT.INIT[02] 32_30
+CLBLL_R.SLICEL_X0.BLUT.INIT[03] 33_30
+CLBLL_R.SLICEL_X0.BLUT.INIT[04] 32_29
+CLBLL_R.SLICEL_X0.BLUT.INIT[05] 33_29
+CLBLL_R.SLICEL_X0.BLUT.INIT[06] 32_28
+CLBLL_R.SLICEL_X0.BLUT.INIT[07] 33_28
+CLBLL_R.SLICEL_X0.BLUT.INIT[08] 35_31
+CLBLL_R.SLICEL_X0.BLUT.INIT[09] 34_31
+CLBLL_R.SLICEL_X0.BLUT.INIT[10] 35_30
+CLBLL_R.SLICEL_X0.BLUT.INIT[11] 34_30
+CLBLL_R.SLICEL_X0.BLUT.INIT[12] 35_29
+CLBLL_R.SLICEL_X0.BLUT.INIT[13] 34_29
+CLBLL_R.SLICEL_X0.BLUT.INIT[14] 35_28
+CLBLL_R.SLICEL_X0.BLUT.INIT[15] 34_28
+CLBLL_R.SLICEL_X0.BLUT.INIT[16] 32_27
+CLBLL_R.SLICEL_X0.BLUT.INIT[17] 33_27
+CLBLL_R.SLICEL_X0.BLUT.INIT[18] 32_26
+CLBLL_R.SLICEL_X0.BLUT.INIT[19] 33_26
+CLBLL_R.SLICEL_X0.BLUT.INIT[20] 32_25
+CLBLL_R.SLICEL_X0.BLUT.INIT[21] 33_25
+CLBLL_R.SLICEL_X0.BLUT.INIT[22] 32_24
+CLBLL_R.SLICEL_X0.BLUT.INIT[23] 33_24
+CLBLL_R.SLICEL_X0.BLUT.INIT[24] 35_27
+CLBLL_R.SLICEL_X0.BLUT.INIT[25] 34_27
+CLBLL_R.SLICEL_X0.BLUT.INIT[26] 35_26
+CLBLL_R.SLICEL_X0.BLUT.INIT[27] 34_26
+CLBLL_R.SLICEL_X0.BLUT.INIT[28] 35_25
+CLBLL_R.SLICEL_X0.BLUT.INIT[29] 34_25
+CLBLL_R.SLICEL_X0.BLUT.INIT[30] 35_24
+CLBLL_R.SLICEL_X0.BLUT.INIT[31] 34_24
+CLBLL_R.SLICEL_X0.BLUT.INIT[32] 32_23
+CLBLL_R.SLICEL_X0.BLUT.INIT[33] 33_23
+CLBLL_R.SLICEL_X0.BLUT.INIT[34] 32_22
+CLBLL_R.SLICEL_X0.BLUT.INIT[35] 33_22
+CLBLL_R.SLICEL_X0.BLUT.INIT[36] 32_21
+CLBLL_R.SLICEL_X0.BLUT.INIT[37] 33_21
+CLBLL_R.SLICEL_X0.BLUT.INIT[38] 32_20
+CLBLL_R.SLICEL_X0.BLUT.INIT[39] 33_20
+CLBLL_R.SLICEL_X0.BLUT.INIT[40] 35_23
+CLBLL_R.SLICEL_X0.BLUT.INIT[41] 34_23
+CLBLL_R.SLICEL_X0.BLUT.INIT[42] 35_22
+CLBLL_R.SLICEL_X0.BLUT.INIT[43] 34_22
+CLBLL_R.SLICEL_X0.BLUT.INIT[44] 35_21
+CLBLL_R.SLICEL_X0.BLUT.INIT[45] 34_21
+CLBLL_R.SLICEL_X0.BLUT.INIT[46] 35_20
+CLBLL_R.SLICEL_X0.BLUT.INIT[47] 34_20
+CLBLL_R.SLICEL_X0.BLUT.INIT[48] 32_19
+CLBLL_R.SLICEL_X0.BLUT.INIT[49] 33_19
+CLBLL_R.SLICEL_X0.BLUT.INIT[50] 32_18
+CLBLL_R.SLICEL_X0.BLUT.INIT[51] 33_18
+CLBLL_R.SLICEL_X0.BLUT.INIT[52] 32_17
+CLBLL_R.SLICEL_X0.BLUT.INIT[53] 33_17
+CLBLL_R.SLICEL_X0.BLUT.INIT[54] 32_16
+CLBLL_R.SLICEL_X0.BLUT.INIT[55] 33_16
+CLBLL_R.SLICEL_X0.BLUT.INIT[56] 35_19
+CLBLL_R.SLICEL_X0.BLUT.INIT[57] 34_19
+CLBLL_R.SLICEL_X0.BLUT.INIT[58] 35_18
+CLBLL_R.SLICEL_X0.BLUT.INIT[59] 34_18
+CLBLL_R.SLICEL_X0.BLUT.INIT[60] 35_17
+CLBLL_R.SLICEL_X0.BLUT.INIT[61] 34_17
+CLBLL_R.SLICEL_X0.BLUT.INIT[62] 35_16
+CLBLL_R.SLICEL_X0.BLUT.INIT[63] 34_16
+CLBLL_R.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
+CLBLL_R.SLICEL_X0.BOUTMUX.CY !30_20 30_21 30_22 !30_23
+CLBLL_R.SLICEL_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
+CLBLL_R.SLICEL_X0.BOUTMUX.O5 30_20 !30_21 30_22 !30_23
+CLBLL_R.SLICEL_X0.BOUTMUX.O6 30_20 !30_21 !30_22 !30_23
+CLBLL_R.SLICEL_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
+CLBLL_R.SLICEL_X0.C5FFMUX.IN_A 31_45
+CLBLL_R.SLICEL_X0.C5FFMUX.IN_B 30_39
+CLBLL_R.SLICEL_X0.C5FF.ZINI 31_41
+CLBLL_R.SLICEL_X0.C5FF.ZRST 01_47
+CLBLL_R.SLICEL_X0.CARRY4.ACY0 30_15
+CLBLL_R.SLICEL_X0.CARRY4.BCY0 01_15
+CLBLL_R.SLICEL_X0.CARRY4.CCY0 30_48
+CLBLL_R.SLICEL_X0.CARRY4.DCY0 30_49
+CLBLL_R.SLICEL_X0.CEUSEDMUX 01_39
+CLBLL_R.SLICEL_X0.CFFMUX.CX !30_35 30_36 !30_37 !30_38
+CLBLL_R.SLICEL_X0.CFFMUX.CY 30_35 !30_36 30_37 !30_38
+CLBLL_R.SLICEL_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37
+CLBLL_R.SLICEL_X0.CFFMUX.F7 30_35 30_36 !30_37 !30_38
+CLBLL_R.SLICEL_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
+CLBLL_R.SLICEL_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38
+CLBLL_R.SLICEL_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
+CLBLL_R.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
+CLBLL_R.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37
+CLBLL_R.SLICEL_X0.CFF.ZINI 31_33
+CLBLL_R.SLICEL_X0.CFF.ZRST 30_33
+CLBLL_R.SLICEL_X0.CLKINV 01_51
+CLBLL_R.SLICEL_X0.CLUT.INIT[00] 32_47
+CLBLL_R.SLICEL_X0.CLUT.INIT[01] 33_47
+CLBLL_R.SLICEL_X0.CLUT.INIT[02] 32_46
+CLBLL_R.SLICEL_X0.CLUT.INIT[03] 33_46
+CLBLL_R.SLICEL_X0.CLUT.INIT[04] 32_45
+CLBLL_R.SLICEL_X0.CLUT.INIT[05] 33_45
+CLBLL_R.SLICEL_X0.CLUT.INIT[06] 32_44
+CLBLL_R.SLICEL_X0.CLUT.INIT[07] 33_44
+CLBLL_R.SLICEL_X0.CLUT.INIT[08] 35_47
+CLBLL_R.SLICEL_X0.CLUT.INIT[09] 34_47
+CLBLL_R.SLICEL_X0.CLUT.INIT[10] 35_46
+CLBLL_R.SLICEL_X0.CLUT.INIT[11] 34_46
+CLBLL_R.SLICEL_X0.CLUT.INIT[12] 35_45
+CLBLL_R.SLICEL_X0.CLUT.INIT[13] 34_45
+CLBLL_R.SLICEL_X0.CLUT.INIT[14] 35_44
+CLBLL_R.SLICEL_X0.CLUT.INIT[15] 34_44
+CLBLL_R.SLICEL_X0.CLUT.INIT[16] 32_43
+CLBLL_R.SLICEL_X0.CLUT.INIT[17] 33_43
+CLBLL_R.SLICEL_X0.CLUT.INIT[18] 32_42
+CLBLL_R.SLICEL_X0.CLUT.INIT[19] 33_42
+CLBLL_R.SLICEL_X0.CLUT.INIT[20] 32_41
+CLBLL_R.SLICEL_X0.CLUT.INIT[21] 33_41
+CLBLL_R.SLICEL_X0.CLUT.INIT[22] 32_40
+CLBLL_R.SLICEL_X0.CLUT.INIT[23] 33_40
+CLBLL_R.SLICEL_X0.CLUT.INIT[24] 35_43
+CLBLL_R.SLICEL_X0.CLUT.INIT[25] 34_43
+CLBLL_R.SLICEL_X0.CLUT.INIT[26] 35_42
+CLBLL_R.SLICEL_X0.CLUT.INIT[27] 34_42
+CLBLL_R.SLICEL_X0.CLUT.INIT[28] 35_41
+CLBLL_R.SLICEL_X0.CLUT.INIT[29] 34_41
+CLBLL_R.SLICEL_X0.CLUT.INIT[30] 35_40
+CLBLL_R.SLICEL_X0.CLUT.INIT[31] 34_40
+CLBLL_R.SLICEL_X0.CLUT.INIT[32] 32_39
+CLBLL_R.SLICEL_X0.CLUT.INIT[33] 33_39
+CLBLL_R.SLICEL_X0.CLUT.INIT[34] 32_38
+CLBLL_R.SLICEL_X0.CLUT.INIT[35] 33_38
+CLBLL_R.SLICEL_X0.CLUT.INIT[36] 32_37
+CLBLL_R.SLICEL_X0.CLUT.INIT[37] 33_37
+CLBLL_R.SLICEL_X0.CLUT.INIT[38] 32_36
+CLBLL_R.SLICEL_X0.CLUT.INIT[39] 33_36
+CLBLL_R.SLICEL_X0.CLUT.INIT[40] 35_39
+CLBLL_R.SLICEL_X0.CLUT.INIT[41] 34_39
+CLBLL_R.SLICEL_X0.CLUT.INIT[42] 35_38
+CLBLL_R.SLICEL_X0.CLUT.INIT[43] 34_38
+CLBLL_R.SLICEL_X0.CLUT.INIT[44] 35_37
+CLBLL_R.SLICEL_X0.CLUT.INIT[45] 34_37
+CLBLL_R.SLICEL_X0.CLUT.INIT[46] 35_36
+CLBLL_R.SLICEL_X0.CLUT.INIT[47] 34_36
+CLBLL_R.SLICEL_X0.CLUT.INIT[48] 32_35
+CLBLL_R.SLICEL_X0.CLUT.INIT[49] 33_35
+CLBLL_R.SLICEL_X0.CLUT.INIT[50] 32_34
+CLBLL_R.SLICEL_X0.CLUT.INIT[51] 33_34
+CLBLL_R.SLICEL_X0.CLUT.INIT[52] 32_33
+CLBLL_R.SLICEL_X0.CLUT.INIT[53] 33_33
+CLBLL_R.SLICEL_X0.CLUT.INIT[54] 32_32
+CLBLL_R.SLICEL_X0.CLUT.INIT[55] 33_32
+CLBLL_R.SLICEL_X0.CLUT.INIT[56] 35_35
+CLBLL_R.SLICEL_X0.CLUT.INIT[57] 34_35
+CLBLL_R.SLICEL_X0.CLUT.INIT[58] 35_34
+CLBLL_R.SLICEL_X0.CLUT.INIT[59] 34_34
+CLBLL_R.SLICEL_X0.CLUT.INIT[60] 35_33
+CLBLL_R.SLICEL_X0.CLUT.INIT[61] 34_33
+CLBLL_R.SLICEL_X0.CLUT.INIT[62] 35_32
+CLBLL_R.SLICEL_X0.CLUT.INIT[63] 34_32
+CLBLL_R.SLICEL_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
+CLBLL_R.SLICEL_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
+CLBLL_R.SLICEL_X0.COUTMUX.F7 30_40 30_43 !30_44 !30_45
+CLBLL_R.SLICEL_X0.COUTMUX.O5 30_40 !30_43 !30_44 30_45
+CLBLL_R.SLICEL_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
+CLBLL_R.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
+CLBLL_R.SLICEL_X0.D5FFMUX.IN_A 30_55
+CLBLL_R.SLICEL_X0.D5FFMUX.IN_B 30_54
+CLBLL_R.SLICEL_X0.D5FF.ZINI 31_51
+CLBLL_R.SLICEL_X0.D5FF.ZRST 01_55
+CLBLL_R.SLICEL_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
+CLBLL_R.SLICEL_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
+CLBLL_R.SLICEL_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
+CLBLL_R.SLICEL_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61
+CLBLL_R.SLICEL_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
+CLBLL_R.SLICEL_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62
+CLBLL_R.SLICEL_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
+CLBLL_R.SLICEL_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59
+CLBLL_R.SLICEL_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
+CLBLL_R.SLICEL_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60
+CLBLL_R.SLICEL_X0.DFF.ZINI 31_58
+CLBLL_R.SLICEL_X0.DFF.ZRST 30_50
+CLBLL_R.SLICEL_X0.DLUT.INIT[00] 32_63
+CLBLL_R.SLICEL_X0.DLUT.INIT[01] 33_63
+CLBLL_R.SLICEL_X0.DLUT.INIT[02] 32_62
+CLBLL_R.SLICEL_X0.DLUT.INIT[03] 33_62
+CLBLL_R.SLICEL_X0.DLUT.INIT[04] 32_61
+CLBLL_R.SLICEL_X0.DLUT.INIT[05] 33_61
+CLBLL_R.SLICEL_X0.DLUT.INIT[06] 32_60
+CLBLL_R.SLICEL_X0.DLUT.INIT[07] 33_60
+CLBLL_R.SLICEL_X0.DLUT.INIT[08] 35_63
+CLBLL_R.SLICEL_X0.DLUT.INIT[09] 34_63
+CLBLL_R.SLICEL_X0.DLUT.INIT[10] 35_62
+CLBLL_R.SLICEL_X0.DLUT.INIT[11] 34_62
+CLBLL_R.SLICEL_X0.DLUT.INIT[12] 35_61
+CLBLL_R.SLICEL_X0.DLUT.INIT[13] 34_61
+CLBLL_R.SLICEL_X0.DLUT.INIT[14] 35_60
+CLBLL_R.SLICEL_X0.DLUT.INIT[15] 34_60
+CLBLL_R.SLICEL_X0.DLUT.INIT[16] 32_59
+CLBLL_R.SLICEL_X0.DLUT.INIT[17] 33_59
+CLBLL_R.SLICEL_X0.DLUT.INIT[18] 32_58
+CLBLL_R.SLICEL_X0.DLUT.INIT[19] 33_58
+CLBLL_R.SLICEL_X0.DLUT.INIT[20] 32_57
+CLBLL_R.SLICEL_X0.DLUT.INIT[21] 33_57
+CLBLL_R.SLICEL_X0.DLUT.INIT[22] 32_56
+CLBLL_R.SLICEL_X0.DLUT.INIT[23] 33_56
+CLBLL_R.SLICEL_X0.DLUT.INIT[24] 35_59
+CLBLL_R.SLICEL_X0.DLUT.INIT[25] 34_59
+CLBLL_R.SLICEL_X0.DLUT.INIT[26] 35_58
+CLBLL_R.SLICEL_X0.DLUT.INIT[27] 34_58
+CLBLL_R.SLICEL_X0.DLUT.INIT[28] 35_57
+CLBLL_R.SLICEL_X0.DLUT.INIT[29] 34_57
+CLBLL_R.SLICEL_X0.DLUT.INIT[30] 35_56
+CLBLL_R.SLICEL_X0.DLUT.INIT[31] 34_56
+CLBLL_R.SLICEL_X0.DLUT.INIT[32] 32_55
+CLBLL_R.SLICEL_X0.DLUT.INIT[33] 33_55
+CLBLL_R.SLICEL_X0.DLUT.INIT[34] 32_54
+CLBLL_R.SLICEL_X0.DLUT.INIT[35] 33_54
+CLBLL_R.SLICEL_X0.DLUT.INIT[36] 32_53
+CLBLL_R.SLICEL_X0.DLUT.INIT[37] 33_53
+CLBLL_R.SLICEL_X0.DLUT.INIT[38] 32_52
+CLBLL_R.SLICEL_X0.DLUT.INIT[39] 33_52
+CLBLL_R.SLICEL_X0.DLUT.INIT[40] 35_55
+CLBLL_R.SLICEL_X0.DLUT.INIT[41] 34_55
+CLBLL_R.SLICEL_X0.DLUT.INIT[42] 35_54
+CLBLL_R.SLICEL_X0.DLUT.INIT[43] 34_54
+CLBLL_R.SLICEL_X0.DLUT.INIT[44] 35_53
+CLBLL_R.SLICEL_X0.DLUT.INIT[45] 34_53
+CLBLL_R.SLICEL_X0.DLUT.INIT[46] 35_52
+CLBLL_R.SLICEL_X0.DLUT.INIT[47] 34_52
+CLBLL_R.SLICEL_X0.DLUT.INIT[48] 32_51
+CLBLL_R.SLICEL_X0.DLUT.INIT[49] 33_51
+CLBLL_R.SLICEL_X0.DLUT.INIT[50] 32_50
+CLBLL_R.SLICEL_X0.DLUT.INIT[51] 33_50
+CLBLL_R.SLICEL_X0.DLUT.INIT[52] 32_49
+CLBLL_R.SLICEL_X0.DLUT.INIT[53] 33_49
+CLBLL_R.SLICEL_X0.DLUT.INIT[54] 32_48
+CLBLL_R.SLICEL_X0.DLUT.INIT[55] 33_48
+CLBLL_R.SLICEL_X0.DLUT.INIT[56] 35_51
+CLBLL_R.SLICEL_X0.DLUT.INIT[57] 34_51
+CLBLL_R.SLICEL_X0.DLUT.INIT[58] 35_50
+CLBLL_R.SLICEL_X0.DLUT.INIT[59] 34_50
+CLBLL_R.SLICEL_X0.DLUT.INIT[60] 35_49
+CLBLL_R.SLICEL_X0.DLUT.INIT[61] 34_49
+CLBLL_R.SLICEL_X0.DLUT.INIT[62] 35_48
+CLBLL_R.SLICEL_X0.DLUT.INIT[63] 34_48
+CLBLL_R.SLICEL_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
+CLBLL_R.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
+CLBLL_R.SLICEL_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
+CLBLL_R.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
+CLBLL_R.SLICEL_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
+CLBLL_R.SLICEL_X0.FFSYNC 00_48
+CLBLL_R.SLICEL_X0.LATCH 30_32
+CLBLL_R.SLICEL_X0.NOCLKINV !01_51
+CLBLL_R.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
+CLBLL_R.SLICEL_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
+CLBLL_R.SLICEL_X0.PRECYINIT.C1 00_12 !30_13 !30_14
+CLBLL_R.SLICEL_X0.PRECYINIT.C1 !30_13 !30_14 00_12
+CLBLL_R.SLICEL_X0.PRECYINIT.CIN !00_12 30_13 !30_14
+CLBLL_R.SLICEL_X0.PRECYINIT.CIN !00_12 !30_14 30_13
+CLBLL_R.SLICEL_X0.SRUSEDMUX 01_35
+CLBLL_R.SLICEL_X1.A5FFMUX.IN_A 31_08
+CLBLL_R.SLICEL_X1.A5FFMUX.IN_B 31_11
+CLBLL_R.SLICEL_X1.A5FF.ZINI 31_05
+CLBLL_R.SLICEL_X1.A5FF.ZRST 01_03
+CLBLL_R.SLICEL_X1.AFFMUX.AX !30_04 !31_00 31_01 !31_02
+CLBLL_R.SLICEL_X1.AFFMUX.CY !30_04 31_00 !31_01 31_02
+CLBLL_R.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02
+CLBLL_R.SLICEL_X1.AFFMUX.F7 !30_04 31_00 31_01 !31_02
+CLBLL_R.SLICEL_X1.AFFMUX.O5 30_04 31_00 !31_01 !31_02
+CLBLL_R.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00
+CLBLL_R.SLICEL_X1.AFFMUX.O6 30_04 !31_00 !31_01 !31_02
+CLBLL_R.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04
+CLBLL_R.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
+CLBLL_R.SLICEL_X1.AFF.ZINI 31_04
+CLBLL_R.SLICEL_X1.AFF.ZRST 31_15
+CLBLL_R.SLICEL_X1.ALUT.INIT[00] 26_15
+CLBLL_R.SLICEL_X1.ALUT.INIT[01] 27_15
+CLBLL_R.SLICEL_X1.ALUT.INIT[02] 26_14
+CLBLL_R.SLICEL_X1.ALUT.INIT[03] 27_14
+CLBLL_R.SLICEL_X1.ALUT.INIT[04] 26_13
+CLBLL_R.SLICEL_X1.ALUT.INIT[05] 27_13
+CLBLL_R.SLICEL_X1.ALUT.INIT[06] 26_12
+CLBLL_R.SLICEL_X1.ALUT.INIT[07] 27_12
+CLBLL_R.SLICEL_X1.ALUT.INIT[08] 29_15
+CLBLL_R.SLICEL_X1.ALUT.INIT[09] 28_15
+CLBLL_R.SLICEL_X1.ALUT.INIT[10] 29_14
+CLBLL_R.SLICEL_X1.ALUT.INIT[11] 28_14
+CLBLL_R.SLICEL_X1.ALUT.INIT[12] 29_13
+CLBLL_R.SLICEL_X1.ALUT.INIT[13] 28_13
+CLBLL_R.SLICEL_X1.ALUT.INIT[14] 29_12
+CLBLL_R.SLICEL_X1.ALUT.INIT[15] 28_12
+CLBLL_R.SLICEL_X1.ALUT.INIT[16] 26_11
+CLBLL_R.SLICEL_X1.ALUT.INIT[17] 27_11
+CLBLL_R.SLICEL_X1.ALUT.INIT[18] 26_10
+CLBLL_R.SLICEL_X1.ALUT.INIT[19] 27_10
+CLBLL_R.SLICEL_X1.ALUT.INIT[20] 26_09
+CLBLL_R.SLICEL_X1.ALUT.INIT[21] 27_09
+CLBLL_R.SLICEL_X1.ALUT.INIT[22] 26_08
+CLBLL_R.SLICEL_X1.ALUT.INIT[23] 27_08
+CLBLL_R.SLICEL_X1.ALUT.INIT[24] 29_11
+CLBLL_R.SLICEL_X1.ALUT.INIT[25] 28_11
+CLBLL_R.SLICEL_X1.ALUT.INIT[26] 29_10
+CLBLL_R.SLICEL_X1.ALUT.INIT[27] 28_10
+CLBLL_R.SLICEL_X1.ALUT.INIT[28] 29_09
+CLBLL_R.SLICEL_X1.ALUT.INIT[29] 28_09
+CLBLL_R.SLICEL_X1.ALUT.INIT[30] 29_08
+CLBLL_R.SLICEL_X1.ALUT.INIT[31] 28_08
+CLBLL_R.SLICEL_X1.ALUT.INIT[32] 26_07
+CLBLL_R.SLICEL_X1.ALUT.INIT[33] 27_07
+CLBLL_R.SLICEL_X1.ALUT.INIT[34] 26_06
+CLBLL_R.SLICEL_X1.ALUT.INIT[35] 27_06
+CLBLL_R.SLICEL_X1.ALUT.INIT[36] 26_05
+CLBLL_R.SLICEL_X1.ALUT.INIT[37] 27_05
+CLBLL_R.SLICEL_X1.ALUT.INIT[38] 26_04
+CLBLL_R.SLICEL_X1.ALUT.INIT[39] 27_04
+CLBLL_R.SLICEL_X1.ALUT.INIT[40] 29_07
+CLBLL_R.SLICEL_X1.ALUT.INIT[41] 28_07
+CLBLL_R.SLICEL_X1.ALUT.INIT[42] 29_06
+CLBLL_R.SLICEL_X1.ALUT.INIT[43] 28_06
+CLBLL_R.SLICEL_X1.ALUT.INIT[44] 29_05
+CLBLL_R.SLICEL_X1.ALUT.INIT[45] 28_05
+CLBLL_R.SLICEL_X1.ALUT.INIT[46] 29_04
+CLBLL_R.SLICEL_X1.ALUT.INIT[47] 28_04
+CLBLL_R.SLICEL_X1.ALUT.INIT[48] 26_03
+CLBLL_R.SLICEL_X1.ALUT.INIT[49] 27_03
+CLBLL_R.SLICEL_X1.ALUT.INIT[50] 26_02
+CLBLL_R.SLICEL_X1.ALUT.INIT[51] 27_02
+CLBLL_R.SLICEL_X1.ALUT.INIT[52] 26_01
+CLBLL_R.SLICEL_X1.ALUT.INIT[53] 27_01
+CLBLL_R.SLICEL_X1.ALUT.INIT[54] 26_00
+CLBLL_R.SLICEL_X1.ALUT.INIT[55] 27_00
+CLBLL_R.SLICEL_X1.ALUT.INIT[56] 29_03
+CLBLL_R.SLICEL_X1.ALUT.INIT[57] 28_03
+CLBLL_R.SLICEL_X1.ALUT.INIT[58] 29_02
+CLBLL_R.SLICEL_X1.ALUT.INIT[59] 28_02
+CLBLL_R.SLICEL_X1.ALUT.INIT[60] 29_01
+CLBLL_R.SLICEL_X1.ALUT.INIT[61] 28_01
+CLBLL_R.SLICEL_X1.ALUT.INIT[62] 29_00
+CLBLL_R.SLICEL_X1.ALUT.INIT[63] 28_00
+CLBLL_R.SLICEL_X1.AOUTMUX.A5Q 30_05 !31_07 !31_09 !31_10
+CLBLL_R.SLICEL_X1.AOUTMUX.CY !30_05 31_07 !31_09 31_10
+CLBLL_R.SLICEL_X1.AOUTMUX.F7 30_05 !31_07 !31_09 31_10
+CLBLL_R.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
+CLBLL_R.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 31_09 !31_10
+CLBLL_R.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
+CLBLL_R.SLICEL_X1.B5FFMUX.IN_A 31_19
+CLBLL_R.SLICEL_X1.B5FFMUX.IN_B 31_18
+CLBLL_R.SLICEL_X1.B5FF.ZINI 31_23
+CLBLL_R.SLICEL_X1.B5FF.ZRST 00_16
+CLBLL_R.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
+CLBLL_R.SLICEL_X1.BFFMUX.CY !31_24 31_25 31_26 !31_27
+CLBLL_R.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26
+CLBLL_R.SLICEL_X1.BFFMUX.F8 !31_24 31_25 !31_26 31_27
+CLBLL_R.SLICEL_X1.BFFMUX.O5 31_24 31_25 !31_26 !31_27
+CLBLL_R.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25
+CLBLL_R.SLICEL_X1.BFFMUX.O6 31_24 !31_25 !31_26 !31_27
+CLBLL_R.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24
+CLBLL_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
+CLBLL_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26
+CLBLL_R.SLICEL_X1.BFF.ZINI 31_29
+CLBLL_R.SLICEL_X1.BFF.ZRST 31_30
+CLBLL_R.SLICEL_X1.BLUT.INIT[00] 26_31
+CLBLL_R.SLICEL_X1.BLUT.INIT[01] 27_31
+CLBLL_R.SLICEL_X1.BLUT.INIT[02] 26_30
+CLBLL_R.SLICEL_X1.BLUT.INIT[03] 27_30
+CLBLL_R.SLICEL_X1.BLUT.INIT[04] 26_29
+CLBLL_R.SLICEL_X1.BLUT.INIT[05] 27_29
+CLBLL_R.SLICEL_X1.BLUT.INIT[06] 26_28
+CLBLL_R.SLICEL_X1.BLUT.INIT[07] 27_28
+CLBLL_R.SLICEL_X1.BLUT.INIT[08] 29_31
+CLBLL_R.SLICEL_X1.BLUT.INIT[09] 28_31
+CLBLL_R.SLICEL_X1.BLUT.INIT[10] 29_30
+CLBLL_R.SLICEL_X1.BLUT.INIT[11] 28_30
+CLBLL_R.SLICEL_X1.BLUT.INIT[12] 29_29
+CLBLL_R.SLICEL_X1.BLUT.INIT[13] 28_29
+CLBLL_R.SLICEL_X1.BLUT.INIT[14] 29_28
+CLBLL_R.SLICEL_X1.BLUT.INIT[15] 28_28
+CLBLL_R.SLICEL_X1.BLUT.INIT[16] 26_27
+CLBLL_R.SLICEL_X1.BLUT.INIT[17] 27_27
+CLBLL_R.SLICEL_X1.BLUT.INIT[18] 26_26
+CLBLL_R.SLICEL_X1.BLUT.INIT[19] 27_26
+CLBLL_R.SLICEL_X1.BLUT.INIT[20] 26_25
+CLBLL_R.SLICEL_X1.BLUT.INIT[21] 27_25
+CLBLL_R.SLICEL_X1.BLUT.INIT[22] 26_24
+CLBLL_R.SLICEL_X1.BLUT.INIT[23] 27_24
+CLBLL_R.SLICEL_X1.BLUT.INIT[24] 29_27
+CLBLL_R.SLICEL_X1.BLUT.INIT[25] 28_27
+CLBLL_R.SLICEL_X1.BLUT.INIT[26] 29_26
+CLBLL_R.SLICEL_X1.BLUT.INIT[27] 28_26
+CLBLL_R.SLICEL_X1.BLUT.INIT[28] 29_25
+CLBLL_R.SLICEL_X1.BLUT.INIT[29] 28_25
+CLBLL_R.SLICEL_X1.BLUT.INIT[30] 29_24
+CLBLL_R.SLICEL_X1.BLUT.INIT[31] 28_24
+CLBLL_R.SLICEL_X1.BLUT.INIT[32] 26_23
+CLBLL_R.SLICEL_X1.BLUT.INIT[33] 27_23
+CLBLL_R.SLICEL_X1.BLUT.INIT[34] 26_22
+CLBLL_R.SLICEL_X1.BLUT.INIT[35] 27_22
+CLBLL_R.SLICEL_X1.BLUT.INIT[36] 26_21
+CLBLL_R.SLICEL_X1.BLUT.INIT[37] 27_21
+CLBLL_R.SLICEL_X1.BLUT.INIT[38] 26_20
+CLBLL_R.SLICEL_X1.BLUT.INIT[39] 27_20
+CLBLL_R.SLICEL_X1.BLUT.INIT[40] 29_23
+CLBLL_R.SLICEL_X1.BLUT.INIT[41] 28_23
+CLBLL_R.SLICEL_X1.BLUT.INIT[42] 29_22
+CLBLL_R.SLICEL_X1.BLUT.INIT[43] 28_22
+CLBLL_R.SLICEL_X1.BLUT.INIT[44] 29_21
+CLBLL_R.SLICEL_X1.BLUT.INIT[45] 28_21
+CLBLL_R.SLICEL_X1.BLUT.INIT[46] 29_20
+CLBLL_R.SLICEL_X1.BLUT.INIT[47] 28_20
+CLBLL_R.SLICEL_X1.BLUT.INIT[48] 26_19
+CLBLL_R.SLICEL_X1.BLUT.INIT[49] 27_19
+CLBLL_R.SLICEL_X1.BLUT.INIT[50] 26_18
+CLBLL_R.SLICEL_X1.BLUT.INIT[51] 27_18
+CLBLL_R.SLICEL_X1.BLUT.INIT[52] 26_17
+CLBLL_R.SLICEL_X1.BLUT.INIT[53] 27_17
+CLBLL_R.SLICEL_X1.BLUT.INIT[54] 26_16
+CLBLL_R.SLICEL_X1.BLUT.INIT[55] 27_16
+CLBLL_R.SLICEL_X1.BLUT.INIT[56] 29_19
+CLBLL_R.SLICEL_X1.BLUT.INIT[57] 28_19
+CLBLL_R.SLICEL_X1.BLUT.INIT[58] 29_18
+CLBLL_R.SLICEL_X1.BLUT.INIT[59] 28_18
+CLBLL_R.SLICEL_X1.BLUT.INIT[60] 29_17
+CLBLL_R.SLICEL_X1.BLUT.INIT[61] 28_17
+CLBLL_R.SLICEL_X1.BLUT.INIT[62] 29_16
+CLBLL_R.SLICEL_X1.BLUT.INIT[63] 28_16
+CLBLL_R.SLICEL_X1.BOUTMUX.B5Q !30_28 30_29 !31_20 !31_21
+CLBLL_R.SLICEL_X1.BOUTMUX.CY 30_28 !30_29 !31_20 31_21
+CLBLL_R.SLICEL_X1.BOUTMUX.F8 !30_28 30_29 !31_20 31_21
+CLBLL_R.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
+CLBLL_R.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 31_20 !31_21
+CLBLL_R.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
+CLBLL_R.SLICEL_X1.C5FFMUX.IN_A 31_44
+CLBLL_R.SLICEL_X1.C5FFMUX.IN_B 31_39
+CLBLL_R.SLICEL_X1.C5FF.ZINI 31_42
+CLBLL_R.SLICEL_X1.C5FF.ZRST 00_44
+CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_14
+CLBLL_R.SLICEL_X1.CARRY4.BCY0 00_08
+CLBLL_R.SLICEL_X1.CARRY4.CCY0 31_48
+CLBLL_R.SLICEL_X1.CARRY4.DCY0 31_49
+CLBLL_R.SLICEL_X1.CEUSEDMUX 00_36
+CLBLL_R.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
+CLBLL_R.SLICEL_X1.CFFMUX.CY 31_35 !31_36 31_37 !31_38
+CLBLL_R.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37
+CLBLL_R.SLICEL_X1.CFFMUX.F7 31_35 !31_36 !31_37 31_38
+CLBLL_R.SLICEL_X1.CFFMUX.O5 31_35 31_36 !31_37 !31_38
+CLBLL_R.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36
+CLBLL_R.SLICEL_X1.CFFMUX.O6 !31_35 31_36 !31_37 !31_38
+CLBLL_R.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36
+CLBLL_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
+CLBLL_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37
+CLBLL_R.SLICEL_X1.CFF.ZINI 31_34
+CLBLL_R.SLICEL_X1.CFF.ZRST 30_34
+CLBLL_R.SLICEL_X1.CLKINV 00_52
+CLBLL_R.SLICEL_X1.CLUT.INIT[00] 26_47
+CLBLL_R.SLICEL_X1.CLUT.INIT[01] 27_47
+CLBLL_R.SLICEL_X1.CLUT.INIT[02] 26_46
+CLBLL_R.SLICEL_X1.CLUT.INIT[03] 27_46
+CLBLL_R.SLICEL_X1.CLUT.INIT[04] 26_45
+CLBLL_R.SLICEL_X1.CLUT.INIT[05] 27_45
+CLBLL_R.SLICEL_X1.CLUT.INIT[06] 26_44
+CLBLL_R.SLICEL_X1.CLUT.INIT[07] 27_44
+CLBLL_R.SLICEL_X1.CLUT.INIT[08] 29_47
+CLBLL_R.SLICEL_X1.CLUT.INIT[09] 28_47
+CLBLL_R.SLICEL_X1.CLUT.INIT[10] 29_46
+CLBLL_R.SLICEL_X1.CLUT.INIT[11] 28_46
+CLBLL_R.SLICEL_X1.CLUT.INIT[12] 29_45
+CLBLL_R.SLICEL_X1.CLUT.INIT[13] 28_45
+CLBLL_R.SLICEL_X1.CLUT.INIT[14] 29_44
+CLBLL_R.SLICEL_X1.CLUT.INIT[15] 28_44
+CLBLL_R.SLICEL_X1.CLUT.INIT[16] 26_43
+CLBLL_R.SLICEL_X1.CLUT.INIT[17] 27_43
+CLBLL_R.SLICEL_X1.CLUT.INIT[18] 26_42
+CLBLL_R.SLICEL_X1.CLUT.INIT[19] 27_42
+CLBLL_R.SLICEL_X1.CLUT.INIT[20] 26_41
+CLBLL_R.SLICEL_X1.CLUT.INIT[21] 27_41
+CLBLL_R.SLICEL_X1.CLUT.INIT[22] 26_40
+CLBLL_R.SLICEL_X1.CLUT.INIT[23] 27_40
+CLBLL_R.SLICEL_X1.CLUT.INIT[24] 29_43
+CLBLL_R.SLICEL_X1.CLUT.INIT[25] 28_43
+CLBLL_R.SLICEL_X1.CLUT.INIT[26] 29_42
+CLBLL_R.SLICEL_X1.CLUT.INIT[27] 28_42
+CLBLL_R.SLICEL_X1.CLUT.INIT[28] 29_41
+CLBLL_R.SLICEL_X1.CLUT.INIT[29] 28_41
+CLBLL_R.SLICEL_X1.CLUT.INIT[30] 29_40
+CLBLL_R.SLICEL_X1.CLUT.INIT[31] 28_40
+CLBLL_R.SLICEL_X1.CLUT.INIT[32] 26_39
+CLBLL_R.SLICEL_X1.CLUT.INIT[33] 27_39
+CLBLL_R.SLICEL_X1.CLUT.INIT[34] 26_38
+CLBLL_R.SLICEL_X1.CLUT.INIT[35] 27_38
+CLBLL_R.SLICEL_X1.CLUT.INIT[36] 26_37
+CLBLL_R.SLICEL_X1.CLUT.INIT[37] 27_37
+CLBLL_R.SLICEL_X1.CLUT.INIT[38] 26_36
+CLBLL_R.SLICEL_X1.CLUT.INIT[39] 27_36
+CLBLL_R.SLICEL_X1.CLUT.INIT[40] 29_39
+CLBLL_R.SLICEL_X1.CLUT.INIT[41] 28_39
+CLBLL_R.SLICEL_X1.CLUT.INIT[42] 29_38
+CLBLL_R.SLICEL_X1.CLUT.INIT[43] 28_38
+CLBLL_R.SLICEL_X1.CLUT.INIT[44] 29_37
+CLBLL_R.SLICEL_X1.CLUT.INIT[45] 28_37
+CLBLL_R.SLICEL_X1.CLUT.INIT[46] 29_36
+CLBLL_R.SLICEL_X1.CLUT.INIT[47] 28_36
+CLBLL_R.SLICEL_X1.CLUT.INIT[48] 26_35
+CLBLL_R.SLICEL_X1.CLUT.INIT[49] 27_35
+CLBLL_R.SLICEL_X1.CLUT.INIT[50] 26_34
+CLBLL_R.SLICEL_X1.CLUT.INIT[51] 27_34
+CLBLL_R.SLICEL_X1.CLUT.INIT[52] 26_33
+CLBLL_R.SLICEL_X1.CLUT.INIT[53] 27_33
+CLBLL_R.SLICEL_X1.CLUT.INIT[54] 26_32
+CLBLL_R.SLICEL_X1.CLUT.INIT[55] 27_32
+CLBLL_R.SLICEL_X1.CLUT.INIT[56] 29_35
+CLBLL_R.SLICEL_X1.CLUT.INIT[57] 28_35
+CLBLL_R.SLICEL_X1.CLUT.INIT[58] 29_34
+CLBLL_R.SLICEL_X1.CLUT.INIT[59] 28_34
+CLBLL_R.SLICEL_X1.CLUT.INIT[60] 29_33
+CLBLL_R.SLICEL_X1.CLUT.INIT[61] 28_33
+CLBLL_R.SLICEL_X1.CLUT.INIT[62] 29_32
+CLBLL_R.SLICEL_X1.CLUT.INIT[63] 28_32
+CLBLL_R.SLICEL_X1.COUTMUX.C5Q 30_41 !30_42 !31_40 !31_43
+CLBLL_R.SLICEL_X1.COUTMUX.CY !30_41 30_42 31_40 !31_43
+CLBLL_R.SLICEL_X1.COUTMUX.F7 30_41 !30_42 31_40 !31_43
+CLBLL_R.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
+CLBLL_R.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
+CLBLL_R.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
+CLBLL_R.SLICEL_X1.D5FFMUX.IN_A 31_55
+CLBLL_R.SLICEL_X1.D5FFMUX.IN_B 31_54
+CLBLL_R.SLICEL_X1.D5FF.ZINI 31_52
+CLBLL_R.SLICEL_X1.D5FF.ZRST 00_56
+CLBLL_R.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
+CLBLL_R.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
+CLBLL_R.SLICEL_X1.DFFMUX.DX !30_58 !31_60 31_61 !31_62
+CLBLL_R.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61
+CLBLL_R.SLICEL_X1.DFFMUX.O5 30_58 31_60 !31_61 !31_62
+CLBLL_R.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60
+CLBLL_R.SLICEL_X1.DFFMUX.O6 !30_58 31_60 !31_61 !31_62
+CLBLL_R.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60
+CLBLL_R.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
+CLBLL_R.SLICEL_X1.DFF.ZINI 31_59
+CLBLL_R.SLICEL_X1.DFF.ZRST 31_50
+CLBLL_R.SLICEL_X1.DLUT.INIT[00] 26_63
+CLBLL_R.SLICEL_X1.DLUT.INIT[01] 27_63
+CLBLL_R.SLICEL_X1.DLUT.INIT[02] 26_62
+CLBLL_R.SLICEL_X1.DLUT.INIT[03] 27_62
+CLBLL_R.SLICEL_X1.DLUT.INIT[04] 26_61
+CLBLL_R.SLICEL_X1.DLUT.INIT[05] 27_61
+CLBLL_R.SLICEL_X1.DLUT.INIT[06] 26_60
+CLBLL_R.SLICEL_X1.DLUT.INIT[07] 27_60
+CLBLL_R.SLICEL_X1.DLUT.INIT[08] 29_63
+CLBLL_R.SLICEL_X1.DLUT.INIT[09] 28_63
+CLBLL_R.SLICEL_X1.DLUT.INIT[10] 29_62
+CLBLL_R.SLICEL_X1.DLUT.INIT[11] 28_62
+CLBLL_R.SLICEL_X1.DLUT.INIT[12] 29_61
+CLBLL_R.SLICEL_X1.DLUT.INIT[13] 28_61
+CLBLL_R.SLICEL_X1.DLUT.INIT[14] 29_60
+CLBLL_R.SLICEL_X1.DLUT.INIT[15] 28_60
+CLBLL_R.SLICEL_X1.DLUT.INIT[16] 26_59
+CLBLL_R.SLICEL_X1.DLUT.INIT[17] 27_59
+CLBLL_R.SLICEL_X1.DLUT.INIT[18] 26_58
+CLBLL_R.SLICEL_X1.DLUT.INIT[19] 27_58
+CLBLL_R.SLICEL_X1.DLUT.INIT[20] 26_57
+CLBLL_R.SLICEL_X1.DLUT.INIT[21] 27_57
+CLBLL_R.SLICEL_X1.DLUT.INIT[22] 26_56
+CLBLL_R.SLICEL_X1.DLUT.INIT[23] 27_56
+CLBLL_R.SLICEL_X1.DLUT.INIT[24] 29_59
+CLBLL_R.SLICEL_X1.DLUT.INIT[25] 28_59
+CLBLL_R.SLICEL_X1.DLUT.INIT[26] 29_58
+CLBLL_R.SLICEL_X1.DLUT.INIT[27] 28_58
+CLBLL_R.SLICEL_X1.DLUT.INIT[28] 29_57
+CLBLL_R.SLICEL_X1.DLUT.INIT[29] 28_57
+CLBLL_R.SLICEL_X1.DLUT.INIT[30] 29_56
+CLBLL_R.SLICEL_X1.DLUT.INIT[31] 28_56
+CLBLL_R.SLICEL_X1.DLUT.INIT[32] 26_55
+CLBLL_R.SLICEL_X1.DLUT.INIT[33] 27_55
+CLBLL_R.SLICEL_X1.DLUT.INIT[34] 26_54
+CLBLL_R.SLICEL_X1.DLUT.INIT[35] 27_54
+CLBLL_R.SLICEL_X1.DLUT.INIT[36] 26_53
+CLBLL_R.SLICEL_X1.DLUT.INIT[37] 27_53
+CLBLL_R.SLICEL_X1.DLUT.INIT[38] 26_52
+CLBLL_R.SLICEL_X1.DLUT.INIT[39] 27_52
+CLBLL_R.SLICEL_X1.DLUT.INIT[40] 29_55
+CLBLL_R.SLICEL_X1.DLUT.INIT[41] 28_55
+CLBLL_R.SLICEL_X1.DLUT.INIT[42] 29_54
+CLBLL_R.SLICEL_X1.DLUT.INIT[43] 28_54
+CLBLL_R.SLICEL_X1.DLUT.INIT[44] 29_53
+CLBLL_R.SLICEL_X1.DLUT.INIT[45] 28_53
+CLBLL_R.SLICEL_X1.DLUT.INIT[46] 29_52
+CLBLL_R.SLICEL_X1.DLUT.INIT[47] 28_52
+CLBLL_R.SLICEL_X1.DLUT.INIT[48] 26_51
+CLBLL_R.SLICEL_X1.DLUT.INIT[49] 27_51
+CLBLL_R.SLICEL_X1.DLUT.INIT[50] 26_50
+CLBLL_R.SLICEL_X1.DLUT.INIT[51] 27_50
+CLBLL_R.SLICEL_X1.DLUT.INIT[52] 26_49
+CLBLL_R.SLICEL_X1.DLUT.INIT[53] 27_49
+CLBLL_R.SLICEL_X1.DLUT.INIT[54] 26_48
+CLBLL_R.SLICEL_X1.DLUT.INIT[55] 27_48
+CLBLL_R.SLICEL_X1.DLUT.INIT[56] 29_51
+CLBLL_R.SLICEL_X1.DLUT.INIT[57] 28_51
+CLBLL_R.SLICEL_X1.DLUT.INIT[58] 29_50
+CLBLL_R.SLICEL_X1.DLUT.INIT[59] 28_50
+CLBLL_R.SLICEL_X1.DLUT.INIT[60] 29_49
+CLBLL_R.SLICEL_X1.DLUT.INIT[61] 28_49
+CLBLL_R.SLICEL_X1.DLUT.INIT[62] 29_48
+CLBLL_R.SLICEL_X1.DLUT.INIT[63] 28_48
+CLBLL_R.SLICEL_X1.DOUTMUX.CY 30_53 !31_53 !31_56 31_57
+CLBLL_R.SLICEL_X1.DOUTMUX.D5Q !30_53 31_53 !31_56 !31_57
+CLBLL_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
+CLBLL_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
+CLBLL_R.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
+CLBLL_R.SLICEL_X1.FFSYNC 01_31
+CLBLL_R.SLICEL_X1.LATCH 31_32
+CLBLL_R.SLICEL_X1.NOCLKINV !00_52
+CLBLL_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
+CLBLL_R.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
+CLBLL_R.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
+CLBLL_R.SLICEL_X1.PRECYINIT.C1 !31_12 !31_13 01_11
+CLBLL_R.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
+CLBLL_R.SLICEL_X1.PRECYINIT.CIN !01_11 !31_13 31_12
+CLBLL_R.SLICEL_X1.SRUSEDMUX 00_32

database/virtex7/segbits_clblm_l.db

@@ -0,0 +1,737 @@
+CLBLM_L.SLICEL_X1.A5FFMUX.IN_A 31_08
+CLBLM_L.SLICEL_X1.A5FFMUX.IN_B 31_11
+CLBLM_L.SLICEL_X1.A5FF.ZINI 31_05
+CLBLM_L.SLICEL_X1.A5FF.ZRST 01_03
+CLBLM_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 31_01 !31_02
+CLBLM_L.SLICEL_X1.AFFMUX.CY !30_04 31_00 !31_01 31_02
+CLBLM_L.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02
+CLBLM_L.SLICEL_X1.AFFMUX.F7 !30_04 31_00 31_01 !31_02
+CLBLM_L.SLICEL_X1.AFFMUX.O5 30_04 31_00 !31_01 !31_02
+CLBLM_L.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00
+CLBLM_L.SLICEL_X1.AFFMUX.O6 30_04 !31_00 !31_01 !31_02
+CLBLM_L.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04
+CLBLM_L.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
+CLBLM_L.SLICEL_X1.AFF.ZINI 31_04
+CLBLM_L.SLICEL_X1.AFF.ZRST 31_15
+CLBLM_L.SLICEL_X1.ALUT.INIT[00] 26_15
+CLBLM_L.SLICEL_X1.ALUT.INIT[01] 27_15
+CLBLM_L.SLICEL_X1.ALUT.INIT[02] 26_14
+CLBLM_L.SLICEL_X1.ALUT.INIT[03] 27_14
+CLBLM_L.SLICEL_X1.ALUT.INIT[04] 26_13
+CLBLM_L.SLICEL_X1.ALUT.INIT[05] 27_13
+CLBLM_L.SLICEL_X1.ALUT.INIT[06] 26_12
+CLBLM_L.SLICEL_X1.ALUT.INIT[07] 27_12
+CLBLM_L.SLICEL_X1.ALUT.INIT[08] 29_15
+CLBLM_L.SLICEL_X1.ALUT.INIT[09] 28_15
+CLBLM_L.SLICEL_X1.ALUT.INIT[10] 29_14
+CLBLM_L.SLICEL_X1.ALUT.INIT[11] 28_14
+CLBLM_L.SLICEL_X1.ALUT.INIT[12] 29_13
+CLBLM_L.SLICEL_X1.ALUT.INIT[13] 28_13
+CLBLM_L.SLICEL_X1.ALUT.INIT[14] 29_12
+CLBLM_L.SLICEL_X1.ALUT.INIT[15] 28_12
+CLBLM_L.SLICEL_X1.ALUT.INIT[16] 26_11
+CLBLM_L.SLICEL_X1.ALUT.INIT[17] 27_11
+CLBLM_L.SLICEL_X1.ALUT.INIT[18] 26_10
+CLBLM_L.SLICEL_X1.ALUT.INIT[19] 27_10
+CLBLM_L.SLICEL_X1.ALUT.INIT[20] 26_09
+CLBLM_L.SLICEL_X1.ALUT.INIT[21] 27_09
+CLBLM_L.SLICEL_X1.ALUT.INIT[22] 26_08
+CLBLM_L.SLICEL_X1.ALUT.INIT[23] 27_08
+CLBLM_L.SLICEL_X1.ALUT.INIT[24] 29_11
+CLBLM_L.SLICEL_X1.ALUT.INIT[25] 28_11
+CLBLM_L.SLICEL_X1.ALUT.INIT[26] 29_10
+CLBLM_L.SLICEL_X1.ALUT.INIT[27] 28_10
+CLBLM_L.SLICEL_X1.ALUT.INIT[28] 29_09
+CLBLM_L.SLICEL_X1.ALUT.INIT[29] 28_09
+CLBLM_L.SLICEL_X1.ALUT.INIT[30] 29_08
+CLBLM_L.SLICEL_X1.ALUT.INIT[31] 28_08
+CLBLM_L.SLICEL_X1.ALUT.INIT[32] 26_07
+CLBLM_L.SLICEL_X1.ALUT.INIT[33] 27_07
+CLBLM_L.SLICEL_X1.ALUT.INIT[34] 26_06
+CLBLM_L.SLICEL_X1.ALUT.INIT[35] 27_06
+CLBLM_L.SLICEL_X1.ALUT.INIT[36] 26_05
+CLBLM_L.SLICEL_X1.ALUT.INIT[37] 27_05
+CLBLM_L.SLICEL_X1.ALUT.INIT[38] 26_04
+CLBLM_L.SLICEL_X1.ALUT.INIT[39] 27_04
+CLBLM_L.SLICEL_X1.ALUT.INIT[40] 29_07
+CLBLM_L.SLICEL_X1.ALUT.INIT[41] 28_07
+CLBLM_L.SLICEL_X1.ALUT.INIT[42] 29_06
+CLBLM_L.SLICEL_X1.ALUT.INIT[43] 28_06
+CLBLM_L.SLICEL_X1.ALUT.INIT[44] 29_05
+CLBLM_L.SLICEL_X1.ALUT.INIT[45] 28_05
+CLBLM_L.SLICEL_X1.ALUT.INIT[46] 29_04
+CLBLM_L.SLICEL_X1.ALUT.INIT[47] 28_04
+CLBLM_L.SLICEL_X1.ALUT.INIT[48] 26_03
+CLBLM_L.SLICEL_X1.ALUT.INIT[49] 27_03
+CLBLM_L.SLICEL_X1.ALUT.INIT[50] 26_02
+CLBLM_L.SLICEL_X1.ALUT.INIT[51] 27_02
+CLBLM_L.SLICEL_X1.ALUT.INIT[52] 26_01
+CLBLM_L.SLICEL_X1.ALUT.INIT[53] 27_01
+CLBLM_L.SLICEL_X1.ALUT.INIT[54] 26_00
+CLBLM_L.SLICEL_X1.ALUT.INIT[55] 27_00
+CLBLM_L.SLICEL_X1.ALUT.INIT[56] 29_03
+CLBLM_L.SLICEL_X1.ALUT.INIT[57] 28_03
+CLBLM_L.SLICEL_X1.ALUT.INIT[58] 29_02
+CLBLM_L.SLICEL_X1.ALUT.INIT[59] 28_02
+CLBLM_L.SLICEL_X1.ALUT.INIT[60] 29_01
+CLBLM_L.SLICEL_X1.ALUT.INIT[61] 28_01
+CLBLM_L.SLICEL_X1.ALUT.INIT[62] 29_00
+CLBLM_L.SLICEL_X1.ALUT.INIT[63] 28_00
+CLBLM_L.SLICEL_X1.AOUTMUX.A5Q 30_05 !31_07 !31_09 !31_10
+CLBLM_L.SLICEL_X1.AOUTMUX.CY !30_05 31_07 !31_09 31_10
+CLBLM_L.SLICEL_X1.AOUTMUX.F7 30_05 !31_07 !31_09 31_10
+CLBLM_L.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
+CLBLM_L.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 31_09 !31_10
+CLBLM_L.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
+CLBLM_L.SLICEL_X1.B5FFMUX.IN_A 31_19
+CLBLM_L.SLICEL_X1.B5FFMUX.IN_B 31_18
+CLBLM_L.SLICEL_X1.B5FF.ZINI 31_23
+CLBLM_L.SLICEL_X1.B5FF.ZRST 00_16
+CLBLM_L.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
+CLBLM_L.SLICEL_X1.BFFMUX.CY !31_24 31_25 31_26 !31_27
+CLBLM_L.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26
+CLBLM_L.SLICEL_X1.BFFMUX.F8 !31_24 31_25 !31_26 31_27
+CLBLM_L.SLICEL_X1.BFFMUX.O5 31_24 31_25 !31_26 !31_27
+CLBLM_L.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25
+CLBLM_L.SLICEL_X1.BFFMUX.O6 31_24 !31_25 !31_26 !31_27
+CLBLM_L.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24
+CLBLM_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
+CLBLM_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26
+CLBLM_L.SLICEL_X1.BFF.ZINI 31_29
+CLBLM_L.SLICEL_X1.BFF.ZRST 31_30
+CLBLM_L.SLICEL_X1.BLUT.INIT[00] 26_31
+CLBLM_L.SLICEL_X1.BLUT.INIT[01] 27_31
+CLBLM_L.SLICEL_X1.BLUT.INIT[02] 26_30
+CLBLM_L.SLICEL_X1.BLUT.INIT[03] 27_30
+CLBLM_L.SLICEL_X1.BLUT.INIT[04] 26_29
+CLBLM_L.SLICEL_X1.BLUT.INIT[05] 27_29
+CLBLM_L.SLICEL_X1.BLUT.INIT[06] 26_28
+CLBLM_L.SLICEL_X1.BLUT.INIT[07] 27_28
+CLBLM_L.SLICEL_X1.BLUT.INIT[08] 29_31
+CLBLM_L.SLICEL_X1.BLUT.INIT[09] 28_31
+CLBLM_L.SLICEL_X1.BLUT.INIT[10] 29_30
+CLBLM_L.SLICEL_X1.BLUT.INIT[11] 28_30
+CLBLM_L.SLICEL_X1.BLUT.INIT[12] 29_29
+CLBLM_L.SLICEL_X1.BLUT.INIT[13] 28_29
+CLBLM_L.SLICEL_X1.BLUT.INIT[14] 29_28
+CLBLM_L.SLICEL_X1.BLUT.INIT[15] 28_28
+CLBLM_L.SLICEL_X1.BLUT.INIT[16] 26_27
+CLBLM_L.SLICEL_X1.BLUT.INIT[17] 27_27
+CLBLM_L.SLICEL_X1.BLUT.INIT[18] 26_26
+CLBLM_L.SLICEL_X1.BLUT.INIT[19] 27_26
+CLBLM_L.SLICEL_X1.BLUT.INIT[20] 26_25
+CLBLM_L.SLICEL_X1.BLUT.INIT[21] 27_25
+CLBLM_L.SLICEL_X1.BLUT.INIT[22] 26_24
+CLBLM_L.SLICEL_X1.BLUT.INIT[23] 27_24
+CLBLM_L.SLICEL_X1.BLUT.INIT[24] 29_27
+CLBLM_L.SLICEL_X1.BLUT.INIT[25] 28_27
+CLBLM_L.SLICEL_X1.BLUT.INIT[26] 29_26
+CLBLM_L.SLICEL_X1.BLUT.INIT[27] 28_26
+CLBLM_L.SLICEL_X1.BLUT.INIT[28] 29_25
+CLBLM_L.SLICEL_X1.BLUT.INIT[29] 28_25
+CLBLM_L.SLICEL_X1.BLUT.INIT[30] 29_24
+CLBLM_L.SLICEL_X1.BLUT.INIT[31] 28_24
+CLBLM_L.SLICEL_X1.BLUT.INIT[32] 26_23
+CLBLM_L.SLICEL_X1.BLUT.INIT[33] 27_23
+CLBLM_L.SLICEL_X1.BLUT.INIT[34] 26_22
+CLBLM_L.SLICEL_X1.BLUT.INIT[35] 27_22
+CLBLM_L.SLICEL_X1.BLUT.INIT[36] 26_21
+CLBLM_L.SLICEL_X1.BLUT.INIT[37] 27_21
+CLBLM_L.SLICEL_X1.BLUT.INIT[38] 26_20
+CLBLM_L.SLICEL_X1.BLUT.INIT[39] 27_20
+CLBLM_L.SLICEL_X1.BLUT.INIT[40] 29_23
+CLBLM_L.SLICEL_X1.BLUT.INIT[41] 28_23
+CLBLM_L.SLICEL_X1.BLUT.INIT[42] 29_22
+CLBLM_L.SLICEL_X1.BLUT.INIT[43] 28_22
+CLBLM_L.SLICEL_X1.BLUT.INIT[44] 29_21
+CLBLM_L.SLICEL_X1.BLUT.INIT[45] 28_21
+CLBLM_L.SLICEL_X1.BLUT.INIT[46] 29_20
+CLBLM_L.SLICEL_X1.BLUT.INIT[47] 28_20
+CLBLM_L.SLICEL_X1.BLUT.INIT[48] 26_19
+CLBLM_L.SLICEL_X1.BLUT.INIT[49] 27_19
+CLBLM_L.SLICEL_X1.BLUT.INIT[50] 26_18
+CLBLM_L.SLICEL_X1.BLUT.INIT[51] 27_18
+CLBLM_L.SLICEL_X1.BLUT.INIT[52] 26_17
+CLBLM_L.SLICEL_X1.BLUT.INIT[53] 27_17
+CLBLM_L.SLICEL_X1.BLUT.INIT[54] 26_16
+CLBLM_L.SLICEL_X1.BLUT.INIT[55] 27_16
+CLBLM_L.SLICEL_X1.BLUT.INIT[56] 29_19
+CLBLM_L.SLICEL_X1.BLUT.INIT[57] 28_19
+CLBLM_L.SLICEL_X1.BLUT.INIT[58] 29_18
+CLBLM_L.SLICEL_X1.BLUT.INIT[59] 28_18
+CLBLM_L.SLICEL_X1.BLUT.INIT[60] 29_17
+CLBLM_L.SLICEL_X1.BLUT.INIT[61] 28_17
+CLBLM_L.SLICEL_X1.BLUT.INIT[62] 29_16
+CLBLM_L.SLICEL_X1.BLUT.INIT[63] 28_16
+CLBLM_L.SLICEL_X1.BOUTMUX.B5Q !30_28 30_29 !31_20 !31_21
+CLBLM_L.SLICEL_X1.BOUTMUX.CY 30_28 !30_29 !31_20 31_21
+CLBLM_L.SLICEL_X1.BOUTMUX.F8 !30_28 30_29 !31_20 31_21
+CLBLM_L.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
+CLBLM_L.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 31_20 !31_21
+CLBLM_L.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
+CLBLM_L.SLICEL_X1.C5FFMUX.IN_A 31_44
+CLBLM_L.SLICEL_X1.C5FFMUX.IN_B 31_39
+CLBLM_L.SLICEL_X1.C5FF.ZINI 31_42
+CLBLM_L.SLICEL_X1.C5FF.ZRST 00_44
+CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_14
+CLBLM_L.SLICEL_X1.CARRY4.BCY0 00_08
+CLBLM_L.SLICEL_X1.CARRY4.CCY0 31_48
+CLBLM_L.SLICEL_X1.CARRY4.DCY0 31_49
+CLBLM_L.SLICEL_X1.CEUSEDMUX 00_36
+CLBLM_L.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
+CLBLM_L.SLICEL_X1.CFFMUX.CY 31_35 !31_36 31_37 !31_38
+CLBLM_L.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37
+CLBLM_L.SLICEL_X1.CFFMUX.F7 31_35 !31_36 !31_37 31_38
+CLBLM_L.SLICEL_X1.CFFMUX.O5 31_35 31_36 !31_37 !31_38
+CLBLM_L.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36
+CLBLM_L.SLICEL_X1.CFFMUX.O6 !31_35 31_36 !31_37 !31_38
+CLBLM_L.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36
+CLBLM_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
+CLBLM_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37
+CLBLM_L.SLICEL_X1.CFF.ZINI 31_34
+CLBLM_L.SLICEL_X1.CFF.ZRST 30_34
+CLBLM_L.SLICEL_X1.CLKINV 00_52
+CLBLM_L.SLICEL_X1.CLUT.INIT[00] 26_47
+CLBLM_L.SLICEL_X1.CLUT.INIT[01] 27_47
+CLBLM_L.SLICEL_X1.CLUT.INIT[02] 26_46
+CLBLM_L.SLICEL_X1.CLUT.INIT[03] 27_46
+CLBLM_L.SLICEL_X1.CLUT.INIT[04] 26_45
+CLBLM_L.SLICEL_X1.CLUT.INIT[05] 27_45
+CLBLM_L.SLICEL_X1.CLUT.INIT[06] 26_44
+CLBLM_L.SLICEL_X1.CLUT.INIT[07] 27_44
+CLBLM_L.SLICEL_X1.CLUT.INIT[08] 29_47
+CLBLM_L.SLICEL_X1.CLUT.INIT[09] 28_47
+CLBLM_L.SLICEL_X1.CLUT.INIT[10] 29_46
+CLBLM_L.SLICEL_X1.CLUT.INIT[11] 28_46
+CLBLM_L.SLICEL_X1.CLUT.INIT[12] 29_45
+CLBLM_L.SLICEL_X1.CLUT.INIT[13] 28_45
+CLBLM_L.SLICEL_X1.CLUT.INIT[14] 29_44
+CLBLM_L.SLICEL_X1.CLUT.INIT[15] 28_44
+CLBLM_L.SLICEL_X1.CLUT.INIT[16] 26_43
+CLBLM_L.SLICEL_X1.CLUT.INIT[17] 27_43
+CLBLM_L.SLICEL_X1.CLUT.INIT[18] 26_42
+CLBLM_L.SLICEL_X1.CLUT.INIT[19] 27_42
+CLBLM_L.SLICEL_X1.CLUT.INIT[20] 26_41
+CLBLM_L.SLICEL_X1.CLUT.INIT[21] 27_41
+CLBLM_L.SLICEL_X1.CLUT.INIT[22] 26_40
+CLBLM_L.SLICEL_X1.CLUT.INIT[23] 27_40
+CLBLM_L.SLICEL_X1.CLUT.INIT[24] 29_43
+CLBLM_L.SLICEL_X1.CLUT.INIT[25] 28_43
+CLBLM_L.SLICEL_X1.CLUT.INIT[26] 29_42
+CLBLM_L.SLICEL_X1.CLUT.INIT[27] 28_42
+CLBLM_L.SLICEL_X1.CLUT.INIT[28] 29_41
+CLBLM_L.SLICEL_X1.CLUT.INIT[29] 28_41
+CLBLM_L.SLICEL_X1.CLUT.INIT[30] 29_40
+CLBLM_L.SLICEL_X1.CLUT.INIT[31] 28_40
+CLBLM_L.SLICEL_X1.CLUT.INIT[32] 26_39
+CLBLM_L.SLICEL_X1.CLUT.INIT[33] 27_39
+CLBLM_L.SLICEL_X1.CLUT.INIT[34] 26_38
+CLBLM_L.SLICEL_X1.CLUT.INIT[35] 27_38
+CLBLM_L.SLICEL_X1.CLUT.INIT[36] 26_37
+CLBLM_L.SLICEL_X1.CLUT.INIT[37] 27_37
+CLBLM_L.SLICEL_X1.CLUT.INIT[38] 26_36
+CLBLM_L.SLICEL_X1.CLUT.INIT[39] 27_36
+CLBLM_L.SLICEL_X1.CLUT.INIT[40] 29_39
+CLBLM_L.SLICEL_X1.CLUT.INIT[41] 28_39
+CLBLM_L.SLICEL_X1.CLUT.INIT[42] 29_38
+CLBLM_L.SLICEL_X1.CLUT.INIT[43] 28_38
+CLBLM_L.SLICEL_X1.CLUT.INIT[44] 29_37
+CLBLM_L.SLICEL_X1.CLUT.INIT[45] 28_37
+CLBLM_L.SLICEL_X1.CLUT.INIT[46] 29_36
+CLBLM_L.SLICEL_X1.CLUT.INIT[47] 28_36
+CLBLM_L.SLICEL_X1.CLUT.INIT[48] 26_35
+CLBLM_L.SLICEL_X1.CLUT.INIT[49] 27_35
+CLBLM_L.SLICEL_X1.CLUT.INIT[50] 26_34
+CLBLM_L.SLICEL_X1.CLUT.INIT[51] 27_34
+CLBLM_L.SLICEL_X1.CLUT.INIT[52] 26_33
+CLBLM_L.SLICEL_X1.CLUT.INIT[53] 27_33
+CLBLM_L.SLICEL_X1.CLUT.INIT[54] 26_32
+CLBLM_L.SLICEL_X1.CLUT.INIT[55] 27_32
+CLBLM_L.SLICEL_X1.CLUT.INIT[56] 29_35
+CLBLM_L.SLICEL_X1.CLUT.INIT[57] 28_35
+CLBLM_L.SLICEL_X1.CLUT.INIT[58] 29_34
+CLBLM_L.SLICEL_X1.CLUT.INIT[59] 28_34
+CLBLM_L.SLICEL_X1.CLUT.INIT[60] 29_33
+CLBLM_L.SLICEL_X1.CLUT.INIT[61] 28_33
+CLBLM_L.SLICEL_X1.CLUT.INIT[62] 29_32
+CLBLM_L.SLICEL_X1.CLUT.INIT[63] 28_32
+CLBLM_L.SLICEL_X1.COUTMUX.C5Q 30_41 !30_42 !31_40 !31_43
+CLBLM_L.SLICEL_X1.COUTMUX.CY !30_41 30_42 31_40 !31_43
+CLBLM_L.SLICEL_X1.COUTMUX.F7 30_41 !30_42 31_40 !31_43
+CLBLM_L.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
+CLBLM_L.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
+CLBLM_L.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
+CLBLM_L.SLICEL_X1.D5FFMUX.IN_A 31_55
+CLBLM_L.SLICEL_X1.D5FFMUX.IN_B 31_54
+CLBLM_L.SLICEL_X1.D5FF.ZINI 31_52
+CLBLM_L.SLICEL_X1.D5FF.ZRST 00_56
+CLBLM_L.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
+CLBLM_L.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
+CLBLM_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 31_61 !31_62
+CLBLM_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61
+CLBLM_L.SLICEL_X1.DFFMUX.O5 30_58 31_60 !31_61 !31_62
+CLBLM_L.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60
+CLBLM_L.SLICEL_X1.DFFMUX.O6 !30_58 31_60 !31_61 !31_62
+CLBLM_L.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60
+CLBLM_L.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
+CLBLM_L.SLICEL_X1.DFF.ZINI 31_59
+CLBLM_L.SLICEL_X1.DFF.ZRST 31_50
+CLBLM_L.SLICEL_X1.DLUT.INIT[00] 26_63
+CLBLM_L.SLICEL_X1.DLUT.INIT[01] 27_63
+CLBLM_L.SLICEL_X1.DLUT.INIT[02] 26_62
+CLBLM_L.SLICEL_X1.DLUT.INIT[03] 27_62
+CLBLM_L.SLICEL_X1.DLUT.INIT[04] 26_61
+CLBLM_L.SLICEL_X1.DLUT.INIT[05] 27_61
+CLBLM_L.SLICEL_X1.DLUT.INIT[06] 26_60
+CLBLM_L.SLICEL_X1.DLUT.INIT[07] 27_60
+CLBLM_L.SLICEL_X1.DLUT.INIT[08] 29_63
+CLBLM_L.SLICEL_X1.DLUT.INIT[09] 28_63
+CLBLM_L.SLICEL_X1.DLUT.INIT[10] 29_62
+CLBLM_L.SLICEL_X1.DLUT.INIT[11] 28_62
+CLBLM_L.SLICEL_X1.DLUT.INIT[12] 29_61
+CLBLM_L.SLICEL_X1.DLUT.INIT[13] 28_61
+CLBLM_L.SLICEL_X1.DLUT.INIT[14] 29_60
+CLBLM_L.SLICEL_X1.DLUT.INIT[15] 28_60
+CLBLM_L.SLICEL_X1.DLUT.INIT[16] 26_59
+CLBLM_L.SLICEL_X1.DLUT.INIT[17] 27_59
+CLBLM_L.SLICEL_X1.DLUT.INIT[18] 26_58
+CLBLM_L.SLICEL_X1.DLUT.INIT[19] 27_58
+CLBLM_L.SLICEL_X1.DLUT.INIT[20] 26_57
+CLBLM_L.SLICEL_X1.DLUT.INIT[21] 27_57
+CLBLM_L.SLICEL_X1.DLUT.INIT[22] 26_56
+CLBLM_L.SLICEL_X1.DLUT.INIT[23] 27_56
+CLBLM_L.SLICEL_X1.DLUT.INIT[24] 29_59
+CLBLM_L.SLICEL_X1.DLUT.INIT[25] 28_59
+CLBLM_L.SLICEL_X1.DLUT.INIT[26] 29_58
+CLBLM_L.SLICEL_X1.DLUT.INIT[27] 28_58
+CLBLM_L.SLICEL_X1.DLUT.INIT[28] 29_57
+CLBLM_L.SLICEL_X1.DLUT.INIT[29] 28_57
+CLBLM_L.SLICEL_X1.DLUT.INIT[30] 29_56
+CLBLM_L.SLICEL_X1.DLUT.INIT[31] 28_56
+CLBLM_L.SLICEL_X1.DLUT.INIT[32] 26_55
+CLBLM_L.SLICEL_X1.DLUT.INIT[33] 27_55
+CLBLM_L.SLICEL_X1.DLUT.INIT[34] 26_54
+CLBLM_L.SLICEL_X1.DLUT.INIT[35] 27_54
+CLBLM_L.SLICEL_X1.DLUT.INIT[36] 26_53
+CLBLM_L.SLICEL_X1.DLUT.INIT[37] 27_53
+CLBLM_L.SLICEL_X1.DLUT.INIT[38] 26_52
+CLBLM_L.SLICEL_X1.DLUT.INIT[39] 27_52
+CLBLM_L.SLICEL_X1.DLUT.INIT[40] 29_55
+CLBLM_L.SLICEL_X1.DLUT.INIT[41] 28_55
+CLBLM_L.SLICEL_X1.DLUT.INIT[42] 29_54
+CLBLM_L.SLICEL_X1.DLUT.INIT[43] 28_54
+CLBLM_L.SLICEL_X1.DLUT.INIT[44] 29_53
+CLBLM_L.SLICEL_X1.DLUT.INIT[45] 28_53
+CLBLM_L.SLICEL_X1.DLUT.INIT[46] 29_52
+CLBLM_L.SLICEL_X1.DLUT.INIT[47] 28_52
+CLBLM_L.SLICEL_X1.DLUT.INIT[48] 26_51
+CLBLM_L.SLICEL_X1.DLUT.INIT[49] 27_51
+CLBLM_L.SLICEL_X1.DLUT.INIT[50] 26_50
+CLBLM_L.SLICEL_X1.DLUT.INIT[51] 27_50
+CLBLM_L.SLICEL_X1.DLUT.INIT[52] 26_49
+CLBLM_L.SLICEL_X1.DLUT.INIT[53] 27_49
+CLBLM_L.SLICEL_X1.DLUT.INIT[54] 26_48
+CLBLM_L.SLICEL_X1.DLUT.INIT[55] 27_48
+CLBLM_L.SLICEL_X1.DLUT.INIT[56] 29_51
+CLBLM_L.SLICEL_X1.DLUT.INIT[57] 28_51
+CLBLM_L.SLICEL_X1.DLUT.INIT[58] 29_50
+CLBLM_L.SLICEL_X1.DLUT.INIT[59] 28_50
+CLBLM_L.SLICEL_X1.DLUT.INIT[60] 29_49
+CLBLM_L.SLICEL_X1.DLUT.INIT[61] 28_49
+CLBLM_L.SLICEL_X1.DLUT.INIT[62] 29_48
+CLBLM_L.SLICEL_X1.DLUT.INIT[63] 28_48
+CLBLM_L.SLICEL_X1.DOUTMUX.CY 30_53 !31_53 !31_56 31_57
+CLBLM_L.SLICEL_X1.DOUTMUX.D5Q !30_53 31_53 !31_56 !31_57
+CLBLM_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
+CLBLM_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
+CLBLM_L.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
+CLBLM_L.SLICEL_X1.FFSYNC 01_31
+CLBLM_L.SLICEL_X1.LATCH 31_32
+CLBLM_L.SLICEL_X1.NOCLKINV !00_52
+CLBLM_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
+CLBLM_L.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
+CLBLM_L.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
+CLBLM_L.SLICEL_X1.PRECYINIT.C1 !31_12 !31_13 01_11
+CLBLM_L.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
+CLBLM_L.SLICEL_X1.PRECYINIT.CIN !01_11 !31_13 31_12
+CLBLM_L.SLICEL_X1.SRUSEDMUX 00_32
+CLBLM_L.SLICEM_X0.A5FFMUX.IN_A 30_09
+CLBLM_L.SLICEM_X0.A5FFMUX.IN_B 30_10
+CLBLM_L.SLICEM_X0.A5FF.ZINI 31_06
+CLBLM_L.SLICEM_X0.A5FF.ZRST 01_07
+CLBLM_L.SLICEM_X0.AFFMUX.AX !30_00 30_01 !30_02 !30_03
+CLBLM_L.SLICEM_X0.AFFMUX.CY 30_00 !30_01 30_02 !30_03
+CLBLM_L.SLICEM_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02
+CLBLM_L.SLICEM_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
+CLBLM_L.SLICEM_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
+CLBLM_L.SLICEM_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03
+CLBLM_L.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
+CLBLM_L.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
+CLBLM_L.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02
+CLBLM_L.SLICEM_X0.AFF.ZINI 31_03
+CLBLM_L.SLICEM_X0.AFF.ZRST 30_12
+CLBLM_L.SLICEM_X0.ALUT.DI1MUX.AI 00_00
+CLBLM_L.SLICEM_X0.ALUT.DI1MUX.BDI1_BMC31 !00_00
+CLBLM_L.SLICEM_X0.ALUT.INIT[00] 34_15
+CLBLM_L.SLICEM_X0.ALUT.INIT[01] 35_15
+CLBLM_L.SLICEM_X0.ALUT.INIT[02] 34_14
+CLBLM_L.SLICEM_X0.ALUT.INIT[03] 35_14
+CLBLM_L.SLICEM_X0.ALUT.INIT[04] 34_13
+CLBLM_L.SLICEM_X0.ALUT.INIT[05] 35_13
+CLBLM_L.SLICEM_X0.ALUT.INIT[06] 34_12
+CLBLM_L.SLICEM_X0.ALUT.INIT[07] 35_12
+CLBLM_L.SLICEM_X0.ALUT.INIT[08] 32_15
+CLBLM_L.SLICEM_X0.ALUT.INIT[09] 33_15
+CLBLM_L.SLICEM_X0.ALUT.INIT[10] 32_14
+CLBLM_L.SLICEM_X0.ALUT.INIT[11] 33_14
+CLBLM_L.SLICEM_X0.ALUT.INIT[12] 32_13
+CLBLM_L.SLICEM_X0.ALUT.INIT[13] 33_13
+CLBLM_L.SLICEM_X0.ALUT.INIT[14] 32_12
+CLBLM_L.SLICEM_X0.ALUT.INIT[15] 33_12
+CLBLM_L.SLICEM_X0.ALUT.INIT[16] 34_11
+CLBLM_L.SLICEM_X0.ALUT.INIT[17] 35_11
+CLBLM_L.SLICEM_X0.ALUT.INIT[18] 34_10
+CLBLM_L.SLICEM_X0.ALUT.INIT[19] 35_10
+CLBLM_L.SLICEM_X0.ALUT.INIT[20] 34_09
+CLBLM_L.SLICEM_X0.ALUT.INIT[21] 35_09
+CLBLM_L.SLICEM_X0.ALUT.INIT[22] 34_08
+CLBLM_L.SLICEM_X0.ALUT.INIT[23] 35_08
+CLBLM_L.SLICEM_X0.ALUT.INIT[24] 32_11
+CLBLM_L.SLICEM_X0.ALUT.INIT[25] 33_11
+CLBLM_L.SLICEM_X0.ALUT.INIT[26] 32_10
+CLBLM_L.SLICEM_X0.ALUT.INIT[27] 33_10
+CLBLM_L.SLICEM_X0.ALUT.INIT[28] 32_09
+CLBLM_L.SLICEM_X0.ALUT.INIT[29] 33_09
+CLBLM_L.SLICEM_X0.ALUT.INIT[30] 32_08
+CLBLM_L.SLICEM_X0.ALUT.INIT[31] 33_08
+CLBLM_L.SLICEM_X0.ALUT.INIT[32] 34_07
+CLBLM_L.SLICEM_X0.ALUT.INIT[33] 35_07
+CLBLM_L.SLICEM_X0.ALUT.INIT[34] 34_06
+CLBLM_L.SLICEM_X0.ALUT.INIT[35] 35_06
+CLBLM_L.SLICEM_X0.ALUT.INIT[36] 34_05
+CLBLM_L.SLICEM_X0.ALUT.INIT[37] 35_05
+CLBLM_L.SLICEM_X0.ALUT.INIT[38] 34_04
+CLBLM_L.SLICEM_X0.ALUT.INIT[39] 35_04
+CLBLM_L.SLICEM_X0.ALUT.INIT[40] 32_07
+CLBLM_L.SLICEM_X0.ALUT.INIT[41] 33_07
+CLBLM_L.SLICEM_X0.ALUT.INIT[42] 32_06
+CLBLM_L.SLICEM_X0.ALUT.INIT[43] 33_06
+CLBLM_L.SLICEM_X0.ALUT.INIT[44] 32_05
+CLBLM_L.SLICEM_X0.ALUT.INIT[45] 33_05
+CLBLM_L.SLICEM_X0.ALUT.INIT[46] 32_04
+CLBLM_L.SLICEM_X0.ALUT.INIT[47] 33_04
+CLBLM_L.SLICEM_X0.ALUT.INIT[48] 34_03
+CLBLM_L.SLICEM_X0.ALUT.INIT[49] 35_03
+CLBLM_L.SLICEM_X0.ALUT.INIT[50] 34_02
+CLBLM_L.SLICEM_X0.ALUT.INIT[51] 35_02
+CLBLM_L.SLICEM_X0.ALUT.INIT[52] 34_01
+CLBLM_L.SLICEM_X0.ALUT.INIT[53] 35_01
+CLBLM_L.SLICEM_X0.ALUT.INIT[54] 34_00
+CLBLM_L.SLICEM_X0.ALUT.INIT[55] 35_00
+CLBLM_L.SLICEM_X0.ALUT.INIT[56] 32_03
+CLBLM_L.SLICEM_X0.ALUT.INIT[57] 33_03
+CLBLM_L.SLICEM_X0.ALUT.INIT[58] 32_02
+CLBLM_L.SLICEM_X0.ALUT.INIT[59] 33_02
+CLBLM_L.SLICEM_X0.ALUT.INIT[60] 32_01
+CLBLM_L.SLICEM_X0.ALUT.INIT[61] 33_01
+CLBLM_L.SLICEM_X0.ALUT.INIT[62] 32_00
+CLBLM_L.SLICEM_X0.ALUT.INIT[63] 33_00
+CLBLM_L.SLICEM_X0.ALUT.RAM 31_16
+CLBLM_L.SLICEM_X0.ALUT.SMALL 00_04
+CLBLM_L.SLICEM_X0.ALUT.SRL 30_16
+CLBLM_L.SLICEM_X0.AOUTMUX.A5Q !30_06 30_07 !30_08 !30_11
+CLBLM_L.SLICEM_X0.AOUTMUX.CY 30_06 !30_07 30_08 !30_11
+CLBLM_L.SLICEM_X0.AOUTMUX.F7 30_06 30_07 !30_08 !30_11
+CLBLM_L.SLICEM_X0.AOUTMUX.O5 30_06 !30_07 !30_08 30_11
+CLBLM_L.SLICEM_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
+CLBLM_L.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
+CLBLM_L.SLICEM_X0.B5FFMUX.IN_A 30_19
+CLBLM_L.SLICEM_X0.B5FFMUX.IN_B 30_18
+CLBLM_L.SLICEM_X0.B5FF.ZINI 31_22
+CLBLM_L.SLICEM_X0.B5FF.ZRST 01_19
+CLBLM_L.SLICEM_X0.BFFMUX.BX !30_24 !30_25 30_26 !30_27
+CLBLM_L.SLICEM_X0.BFFMUX.CY !30_24 30_25 !30_26 30_27
+CLBLM_L.SLICEM_X0.BFFMUX.CY !30_24 !30_26 30_25 30_27
+CLBLM_L.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
+CLBLM_L.SLICEM_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
+CLBLM_L.SLICEM_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27
+CLBLM_L.SLICEM_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
+CLBLM_L.SLICEM_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24
+CLBLM_L.SLICEM_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
+CLBLM_L.SLICEM_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25
+CLBLM_L.SLICEM_X0.BFF.ZINI 31_28
+CLBLM_L.SLICEM_X0.BFF.ZRST 30_30
+CLBLM_L.SLICEM_X0.BLUT.DI1MUX.BI 00_20
+CLBLM_L.SLICEM_X0.BLUT.DI1MUX.DI_CMC31 !00_20
+CLBLM_L.SLICEM_X0.BLUT.INIT[00] 34_31
+CLBLM_L.SLICEM_X0.BLUT.INIT[01] 35_31
+CLBLM_L.SLICEM_X0.BLUT.INIT[02] 34_30
+CLBLM_L.SLICEM_X0.BLUT.INIT[03] 35_30
+CLBLM_L.SLICEM_X0.BLUT.INIT[04] 34_29
+CLBLM_L.SLICEM_X0.BLUT.INIT[05] 35_29
+CLBLM_L.SLICEM_X0.BLUT.INIT[06] 34_28
+CLBLM_L.SLICEM_X0.BLUT.INIT[07] 35_28
+CLBLM_L.SLICEM_X0.BLUT.INIT[08] 32_31
+CLBLM_L.SLICEM_X0.BLUT.INIT[09] 33_31
+CLBLM_L.SLICEM_X0.BLUT.INIT[10] 32_30
+CLBLM_L.SLICEM_X0.BLUT.INIT[11] 33_30
+CLBLM_L.SLICEM_X0.BLUT.INIT[12] 32_29
+CLBLM_L.SLICEM_X0.BLUT.INIT[13] 33_29
+CLBLM_L.SLICEM_X0.BLUT.INIT[14] 32_28
+CLBLM_L.SLICEM_X0.BLUT.INIT[15] 33_28
+CLBLM_L.SLICEM_X0.BLUT.INIT[16] 34_27
+CLBLM_L.SLICEM_X0.BLUT.INIT[17] 35_27
+CLBLM_L.SLICEM_X0.BLUT.INIT[18] 34_26
+CLBLM_L.SLICEM_X0.BLUT.INIT[19] 35_26
+CLBLM_L.SLICEM_X0.BLUT.INIT[20] 34_25
+CLBLM_L.SLICEM_X0.BLUT.INIT[21] 35_25
+CLBLM_L.SLICEM_X0.BLUT.INIT[22] 34_24
+CLBLM_L.SLICEM_X0.BLUT.INIT[23] 35_24
+CLBLM_L.SLICEM_X0.BLUT.INIT[24] 32_27
+CLBLM_L.SLICEM_X0.BLUT.INIT[25] 33_27
+CLBLM_L.SLICEM_X0.BLUT.INIT[26] 32_26
+CLBLM_L.SLICEM_X0.BLUT.INIT[27] 33_26
+CLBLM_L.SLICEM_X0.BLUT.INIT[28] 32_25
+CLBLM_L.SLICEM_X0.BLUT.INIT[29] 33_25
+CLBLM_L.SLICEM_X0.BLUT.INIT[30] 32_24
+CLBLM_L.SLICEM_X0.BLUT.INIT[31] 33_24
+CLBLM_L.SLICEM_X0.BLUT.INIT[32] 34_23
+CLBLM_L.SLICEM_X0.BLUT.INIT[33] 35_23
+CLBLM_L.SLICEM_X0.BLUT.INIT[34] 34_22
+CLBLM_L.SLICEM_X0.BLUT.INIT[35] 35_22
+CLBLM_L.SLICEM_X0.BLUT.INIT[36] 34_21
+CLBLM_L.SLICEM_X0.BLUT.INIT[37] 35_21
+CLBLM_L.SLICEM_X0.BLUT.INIT[38] 34_20
+CLBLM_L.SLICEM_X0.BLUT.INIT[39] 35_20
+CLBLM_L.SLICEM_X0.BLUT.INIT[40] 32_23
+CLBLM_L.SLICEM_X0.BLUT.INIT[41] 33_23
+CLBLM_L.SLICEM_X0.BLUT.INIT[42] 32_22
+CLBLM_L.SLICEM_X0.BLUT.INIT[43] 33_22
+CLBLM_L.SLICEM_X0.BLUT.INIT[44] 32_21
+CLBLM_L.SLICEM_X0.BLUT.INIT[45] 33_21
+CLBLM_L.SLICEM_X0.BLUT.INIT[46] 32_20
+CLBLM_L.SLICEM_X0.BLUT.INIT[47] 33_20
+CLBLM_L.SLICEM_X0.BLUT.INIT[48] 34_19
+CLBLM_L.SLICEM_X0.BLUT.INIT[49] 35_19
+CLBLM_L.SLICEM_X0.BLUT.INIT[50] 34_18
+CLBLM_L.SLICEM_X0.BLUT.INIT[51] 35_18
+CLBLM_L.SLICEM_X0.BLUT.INIT[52] 34_17
+CLBLM_L.SLICEM_X0.BLUT.INIT[53] 35_17
+CLBLM_L.SLICEM_X0.BLUT.INIT[54] 34_16
+CLBLM_L.SLICEM_X0.BLUT.INIT[55] 35_16
+CLBLM_L.SLICEM_X0.BLUT.INIT[56] 32_19
+CLBLM_L.SLICEM_X0.BLUT.INIT[57] 33_19
+CLBLM_L.SLICEM_X0.BLUT.INIT[58] 32_18
+CLBLM_L.SLICEM_X0.BLUT.INIT[59] 33_18
+CLBLM_L.SLICEM_X0.BLUT.INIT[60] 32_17
+CLBLM_L.SLICEM_X0.BLUT.INIT[61] 33_17
+CLBLM_L.SLICEM_X0.BLUT.INIT[62] 32_16
+CLBLM_L.SLICEM_X0.BLUT.INIT[63] 33_16
+CLBLM_L.SLICEM_X0.BLUT.RAM 31_17
+CLBLM_L.SLICEM_X0.BLUT.SMALL 00_24
+CLBLM_L.SLICEM_X0.BLUT.SRL 30_17
+CLBLM_L.SLICEM_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
+CLBLM_L.SLICEM_X0.BOUTMUX.CY !30_20 30_21 30_22 !30_23
+CLBLM_L.SLICEM_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
+CLBLM_L.SLICEM_X0.BOUTMUX.O5 30_20 !30_21 30_22 !30_23
+CLBLM_L.SLICEM_X0.BOUTMUX.O6 30_20 !30_21 !30_22 !30_23
+CLBLM_L.SLICEM_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
+CLBLM_L.SLICEM_X0.C5FFMUX.IN_A 31_45
+CLBLM_L.SLICEM_X0.C5FFMUX.IN_B 30_39
+CLBLM_L.SLICEM_X0.C5FF.ZINI 31_41
+CLBLM_L.SLICEM_X0.C5FF.ZRST 01_47
+CLBLM_L.SLICEM_X0.CARRY4.ACY0 30_15
+CLBLM_L.SLICEM_X0.CARRY4.BCY0 01_15
+CLBLM_L.SLICEM_X0.CARRY4.CCY0 30_48
+CLBLM_L.SLICEM_X0.CARRY4.DCY0 30_49
+CLBLM_L.SLICEM_X0.CEUSEDMUX 01_39
+CLBLM_L.SLICEM_X0.CFFMUX.CX !30_35 30_36 !30_37 !30_38
+CLBLM_L.SLICEM_X0.CFFMUX.CY 30_35 !30_36 30_37 !30_38
+CLBLM_L.SLICEM_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37
+CLBLM_L.SLICEM_X0.CFFMUX.F7 30_35 30_36 !30_37 !30_38
+CLBLM_L.SLICEM_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
+CLBLM_L.SLICEM_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38
+CLBLM_L.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
+CLBLM_L.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
+CLBLM_L.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37
+CLBLM_L.SLICEM_X0.CFF.ZINI 31_33
+CLBLM_L.SLICEM_X0.CFF.ZRST 30_33
+CLBLM_L.SLICEM_X0.CLKINV 01_51
+CLBLM_L.SLICEM_X0.CLUT.DI1MUX.CI 01_43
+CLBLM_L.SLICEM_X0.CLUT.DI1MUX.DI_DMC31 !01_43
+CLBLM_L.SLICEM_X0.CLUT.INIT[00] 34_47
+CLBLM_L.SLICEM_X0.CLUT.INIT[01] 35_47
+CLBLM_L.SLICEM_X0.CLUT.INIT[02] 34_46
+CLBLM_L.SLICEM_X0.CLUT.INIT[03] 35_46
+CLBLM_L.SLICEM_X0.CLUT.INIT[04] 34_45
+CLBLM_L.SLICEM_X0.CLUT.INIT[05] 35_45
+CLBLM_L.SLICEM_X0.CLUT.INIT[06] 34_44
+CLBLM_L.SLICEM_X0.CLUT.INIT[07] 35_44
+CLBLM_L.SLICEM_X0.CLUT.INIT[08] 32_47
+CLBLM_L.SLICEM_X0.CLUT.INIT[09] 33_47
+CLBLM_L.SLICEM_X0.CLUT.INIT[10] 32_46
+CLBLM_L.SLICEM_X0.CLUT.INIT[11] 33_46
+CLBLM_L.SLICEM_X0.CLUT.INIT[12] 32_45
+CLBLM_L.SLICEM_X0.CLUT.INIT[13] 33_45
+CLBLM_L.SLICEM_X0.CLUT.INIT[14] 32_44
+CLBLM_L.SLICEM_X0.CLUT.INIT[15] 33_44
+CLBLM_L.SLICEM_X0.CLUT.INIT[16] 34_43
+CLBLM_L.SLICEM_X0.CLUT.INIT[17] 35_43
+CLBLM_L.SLICEM_X0.CLUT.INIT[18] 34_42
+CLBLM_L.SLICEM_X0.CLUT.INIT[19] 35_42
+CLBLM_L.SLICEM_X0.CLUT.INIT[20] 34_41
+CLBLM_L.SLICEM_X0.CLUT.INIT[21] 35_41
+CLBLM_L.SLICEM_X0.CLUT.INIT[22] 34_40
+CLBLM_L.SLICEM_X0.CLUT.INIT[23] 35_40
+CLBLM_L.SLICEM_X0.CLUT.INIT[24] 32_43
+CLBLM_L.SLICEM_X0.CLUT.INIT[25] 33_43
+CLBLM_L.SLICEM_X0.CLUT.INIT[26] 32_42
+CLBLM_L.SLICEM_X0.CLUT.INIT[27] 33_42
+CLBLM_L.SLICEM_X0.CLUT.INIT[28] 32_41
+CLBLM_L.SLICEM_X0.CLUT.INIT[29] 33_41
+CLBLM_L.SLICEM_X0.CLUT.INIT[30] 32_40
+CLBLM_L.SLICEM_X0.CLUT.INIT[31] 33_40
+CLBLM_L.SLICEM_X0.CLUT.INIT[32] 34_39
+CLBLM_L.SLICEM_X0.CLUT.INIT[33] 35_39
+CLBLM_L.SLICEM_X0.CLUT.INIT[34] 34_38
+CLBLM_L.SLICEM_X0.CLUT.INIT[35] 35_38
+CLBLM_L.SLICEM_X0.CLUT.INIT[36] 34_37
+CLBLM_L.SLICEM_X0.CLUT.INIT[37] 35_37
+CLBLM_L.SLICEM_X0.CLUT.INIT[38] 34_36
+CLBLM_L.SLICEM_X0.CLUT.INIT[39] 35_36
+CLBLM_L.SLICEM_X0.CLUT.INIT[40] 32_39
+CLBLM_L.SLICEM_X0.CLUT.INIT[41] 33_39
+CLBLM_L.SLICEM_X0.CLUT.INIT[42] 32_38
+CLBLM_L.SLICEM_X0.CLUT.INIT[43] 33_38
+CLBLM_L.SLICEM_X0.CLUT.INIT[44] 32_37
+CLBLM_L.SLICEM_X0.CLUT.INIT[45] 33_37
+CLBLM_L.SLICEM_X0.CLUT.INIT[46] 32_36
+CLBLM_L.SLICEM_X0.CLUT.INIT[47] 33_36
+CLBLM_L.SLICEM_X0.CLUT.INIT[48] 34_35
+CLBLM_L.SLICEM_X0.CLUT.INIT[49] 35_35
+CLBLM_L.SLICEM_X0.CLUT.INIT[50] 34_34
+CLBLM_L.SLICEM_X0.CLUT.INIT[51] 35_34
+CLBLM_L.SLICEM_X0.CLUT.INIT[52] 34_33
+CLBLM_L.SLICEM_X0.CLUT.INIT[53] 35_33
+CLBLM_L.SLICEM_X0.CLUT.INIT[54] 34_32
+CLBLM_L.SLICEM_X0.CLUT.INIT[55] 35_32
+CLBLM_L.SLICEM_X0.CLUT.INIT[56] 32_35
+CLBLM_L.SLICEM_X0.CLUT.INIT[57] 33_35
+CLBLM_L.SLICEM_X0.CLUT.INIT[58] 32_34
+CLBLM_L.SLICEM_X0.CLUT.INIT[59] 33_34
+CLBLM_L.SLICEM_X0.CLUT.INIT[60] 32_33
+CLBLM_L.SLICEM_X0.CLUT.INIT[61] 33_33
+CLBLM_L.SLICEM_X0.CLUT.INIT[62] 32_32
+CLBLM_L.SLICEM_X0.CLUT.INIT[63] 33_32
+CLBLM_L.SLICEM_X0.CLUT.RAM 31_46
+CLBLM_L.SLICEM_X0.CLUT.SMALL 00_28
+CLBLM_L.SLICEM_X0.CLUT.SRL 30_46
+CLBLM_L.SLICEM_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
+CLBLM_L.SLICEM_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
+CLBLM_L.SLICEM_X0.COUTMUX.F7 30_40 30_43 !30_44 !30_45
+CLBLM_L.SLICEM_X0.COUTMUX.O5 30_40 !30_43 !30_44 30_45
+CLBLM_L.SLICEM_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
+CLBLM_L.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
+CLBLM_L.SLICEM_X0.D5FFMUX.IN_A 30_55
+CLBLM_L.SLICEM_X0.D5FFMUX.IN_B 30_54
+CLBLM_L.SLICEM_X0.D5FF.ZINI 31_51
+CLBLM_L.SLICEM_X0.D5FF.ZRST 01_55
+CLBLM_L.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
+CLBLM_L.SLICEM_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
+CLBLM_L.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
+CLBLM_L.SLICEM_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61
+CLBLM_L.SLICEM_X0.DFFMUX.MC31 !30_59 !30_60 30_61 30_62
+CLBLM_L.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
+CLBLM_L.SLICEM_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62
+CLBLM_L.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
+CLBLM_L.SLICEM_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59
+CLBLM_L.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
+CLBLM_L.SLICEM_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60
+CLBLM_L.SLICEM_X0.DFF.ZINI 31_58
+CLBLM_L.SLICEM_X0.DFF.ZRST 30_50
+CLBLM_L.SLICEM_X0.DLUT.INIT[00] 34_63
+CLBLM_L.SLICEM_X0.DLUT.INIT[01] 35_63
+CLBLM_L.SLICEM_X0.DLUT.INIT[02] 34_62
+CLBLM_L.SLICEM_X0.DLUT.INIT[03] 35_62
+CLBLM_L.SLICEM_X0.DLUT.INIT[04] 34_61
+CLBLM_L.SLICEM_X0.DLUT.INIT[05] 35_61
+CLBLM_L.SLICEM_X0.DLUT.INIT[06] 34_60
+CLBLM_L.SLICEM_X0.DLUT.INIT[07] 35_60
+CLBLM_L.SLICEM_X0.DLUT.INIT[08] 32_63
+CLBLM_L.SLICEM_X0.DLUT.INIT[09] 33_63
+CLBLM_L.SLICEM_X0.DLUT.INIT[10] 32_62
+CLBLM_L.SLICEM_X0.DLUT.INIT[11] 33_62
+CLBLM_L.SLICEM_X0.DLUT.INIT[12] 32_61
+CLBLM_L.SLICEM_X0.DLUT.INIT[13] 33_61
+CLBLM_L.SLICEM_X0.DLUT.INIT[14] 32_60
+CLBLM_L.SLICEM_X0.DLUT.INIT[15] 33_60
+CLBLM_L.SLICEM_X0.DLUT.INIT[16] 34_59
+CLBLM_L.SLICEM_X0.DLUT.INIT[17] 35_59
+CLBLM_L.SLICEM_X0.DLUT.INIT[18] 34_58
+CLBLM_L.SLICEM_X0.DLUT.INIT[19] 35_58
+CLBLM_L.SLICEM_X0.DLUT.INIT[20] 34_57
+CLBLM_L.SLICEM_X0.DLUT.INIT[21] 35_57
+CLBLM_L.SLICEM_X0.DLUT.INIT[22] 34_56
+CLBLM_L.SLICEM_X0.DLUT.INIT[23] 35_56
+CLBLM_L.SLICEM_X0.DLUT.INIT[24] 32_59
+CLBLM_L.SLICEM_X0.DLUT.INIT[25] 33_59
+CLBLM_L.SLICEM_X0.DLUT.INIT[26] 32_58
+CLBLM_L.SLICEM_X0.DLUT.INIT[27] 33_58
+CLBLM_L.SLICEM_X0.DLUT.INIT[28] 32_57
+CLBLM_L.SLICEM_X0.DLUT.INIT[29] 33_57
+CLBLM_L.SLICEM_X0.DLUT.INIT[30] 32_56
+CLBLM_L.SLICEM_X0.DLUT.INIT[31] 33_56
+CLBLM_L.SLICEM_X0.DLUT.INIT[32] 34_55
+CLBLM_L.SLICEM_X0.DLUT.INIT[33] 35_55
+CLBLM_L.SLICEM_X0.DLUT.INIT[34] 34_54
+CLBLM_L.SLICEM_X0.DLUT.INIT[35] 35_54
+CLBLM_L.SLICEM_X0.DLUT.INIT[36] 34_53
+CLBLM_L.SLICEM_X0.DLUT.INIT[37] 35_53
+CLBLM_L.SLICEM_X0.DLUT.INIT[38] 34_52
+CLBLM_L.SLICEM_X0.DLUT.INIT[39] 35_52
+CLBLM_L.SLICEM_X0.DLUT.INIT[40] 32_55
+CLBLM_L.SLICEM_X0.DLUT.INIT[41] 33_55
+CLBLM_L.SLICEM_X0.DLUT.INIT[42] 32_54
+CLBLM_L.SLICEM_X0.DLUT.INIT[43] 33_54
+CLBLM_L.SLICEM_X0.DLUT.INIT[44] 32_53
+CLBLM_L.SLICEM_X0.DLUT.INIT[45] 33_53
+CLBLM_L.SLICEM_X0.DLUT.INIT[46] 32_52
+CLBLM_L.SLICEM_X0.DLUT.INIT[47] 33_52
+CLBLM_L.SLICEM_X0.DLUT.INIT[48] 34_51
+CLBLM_L.SLICEM_X0.DLUT.INIT[49] 35_51
+CLBLM_L.SLICEM_X0.DLUT.INIT[50] 34_50
+CLBLM_L.SLICEM_X0.DLUT.INIT[51] 35_50
+CLBLM_L.SLICEM_X0.DLUT.INIT[52] 34_49
+CLBLM_L.SLICEM_X0.DLUT.INIT[53] 35_49
+CLBLM_L.SLICEM_X0.DLUT.INIT[54] 34_48
+CLBLM_L.SLICEM_X0.DLUT.INIT[55] 35_48
+CLBLM_L.SLICEM_X0.DLUT.INIT[56] 32_51
+CLBLM_L.SLICEM_X0.DLUT.INIT[57] 33_51
+CLBLM_L.SLICEM_X0.DLUT.INIT[58] 32_50
+CLBLM_L.SLICEM_X0.DLUT.INIT[59] 33_50
+CLBLM_L.SLICEM_X0.DLUT.INIT[60] 32_49
+CLBLM_L.SLICEM_X0.DLUT.INIT[61] 33_49
+CLBLM_L.SLICEM_X0.DLUT.INIT[62] 32_48
+CLBLM_L.SLICEM_X0.DLUT.INIT[63] 33_48
+CLBLM_L.SLICEM_X0.DLUT.RAM 31_47
+CLBLM_L.SLICEM_X0.DLUT.SMALL 01_59
+CLBLM_L.SLICEM_X0.DLUT.SRL 30_47
+CLBLM_L.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
+CLBLM_L.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
+CLBLM_L.SLICEM_X0.DOUTMUX.MC31 !30_51 30_52 !30_56 30_57
+CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
+CLBLM_L.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
+CLBLM_L.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
+CLBLM_L.SLICEM_X0.FFSYNC 00_48
+CLBLM_L.SLICEM_X0.LATCH 30_32
+CLBLM_L.SLICEM_X0.NOCLKINV !01_51
+CLBLM_L.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
+CLBLM_L.SLICEM_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
+CLBLM_L.SLICEM_X0.PRECYINIT.C1 00_12 !30_13 !30_14
+CLBLM_L.SLICEM_X0.PRECYINIT.C1 !30_13 !30_14 00_12
+CLBLM_L.SLICEM_X0.PRECYINIT.CIN !00_12 30_13 !30_14
+CLBLM_L.SLICEM_X0.PRECYINIT.CIN !00_12 !30_14 30_13
+CLBLM_L.SLICEM_X0.SRUSEDMUX 01_35
+CLBLM_L.SLICEM_X0.WA7USED 00_40
+CLBLM_L.SLICEM_X0.WA8USED 01_27
+CLBLM_L.SLICEM_X0.WEMUX.CE 01_23

database/virtex7/segbits_clblm_r.db

@@ -0,0 +1,737 @@
+CLBLM_R.SLICEL_X1.A5FFMUX.IN_A 31_08
+CLBLM_R.SLICEL_X1.A5FFMUX.IN_B 31_11
+CLBLM_R.SLICEL_X1.A5FF.ZINI 31_05
+CLBLM_R.SLICEL_X1.A5FF.ZRST 01_03
+CLBLM_R.SLICEL_X1.AFFMUX.AX !30_04 !31_00 31_01 !31_02
+CLBLM_R.SLICEL_X1.AFFMUX.CY !30_04 31_00 !31_01 31_02
+CLBLM_R.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02
+CLBLM_R.SLICEL_X1.AFFMUX.F7 !30_04 31_00 31_01 !31_02
+CLBLM_R.SLICEL_X1.AFFMUX.O5 30_04 31_00 !31_01 !31_02
+CLBLM_R.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00
+CLBLM_R.SLICEL_X1.AFFMUX.O6 30_04 !31_00 !31_01 !31_02
+CLBLM_R.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04
+CLBLM_R.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
+CLBLM_R.SLICEL_X1.AFF.ZINI 31_04
+CLBLM_R.SLICEL_X1.AFF.ZRST 31_15
+CLBLM_R.SLICEL_X1.ALUT.INIT[00] 26_15
+CLBLM_R.SLICEL_X1.ALUT.INIT[01] 27_15
+CLBLM_R.SLICEL_X1.ALUT.INIT[02] 26_14
+CLBLM_R.SLICEL_X1.ALUT.INIT[03] 27_14
+CLBLM_R.SLICEL_X1.ALUT.INIT[04] 26_13
+CLBLM_R.SLICEL_X1.ALUT.INIT[05] 27_13
+CLBLM_R.SLICEL_X1.ALUT.INIT[06] 26_12
+CLBLM_R.SLICEL_X1.ALUT.INIT[07] 27_12
+CLBLM_R.SLICEL_X1.ALUT.INIT[08] 29_15
+CLBLM_R.SLICEL_X1.ALUT.INIT[09] 28_15
+CLBLM_R.SLICEL_X1.ALUT.INIT[10] 29_14
+CLBLM_R.SLICEL_X1.ALUT.INIT[11] 28_14
+CLBLM_R.SLICEL_X1.ALUT.INIT[12] 29_13
+CLBLM_R.SLICEL_X1.ALUT.INIT[13] 28_13
+CLBLM_R.SLICEL_X1.ALUT.INIT[14] 29_12
+CLBLM_R.SLICEL_X1.ALUT.INIT[15] 28_12
+CLBLM_R.SLICEL_X1.ALUT.INIT[16] 26_11
+CLBLM_R.SLICEL_X1.ALUT.INIT[17] 27_11
+CLBLM_R.SLICEL_X1.ALUT.INIT[18] 26_10
+CLBLM_R.SLICEL_X1.ALUT.INIT[19] 27_10
+CLBLM_R.SLICEL_X1.ALUT.INIT[20] 26_09
+CLBLM_R.SLICEL_X1.ALUT.INIT[21] 27_09
+CLBLM_R.SLICEL_X1.ALUT.INIT[22] 26_08
+CLBLM_R.SLICEL_X1.ALUT.INIT[23] 27_08
+CLBLM_R.SLICEL_X1.ALUT.INIT[24] 29_11
+CLBLM_R.SLICEL_X1.ALUT.INIT[25] 28_11
+CLBLM_R.SLICEL_X1.ALUT.INIT[26] 29_10
+CLBLM_R.SLICEL_X1.ALUT.INIT[27] 28_10
+CLBLM_R.SLICEL_X1.ALUT.INIT[28] 29_09
+CLBLM_R.SLICEL_X1.ALUT.INIT[29] 28_09
+CLBLM_R.SLICEL_X1.ALUT.INIT[30] 29_08
+CLBLM_R.SLICEL_X1.ALUT.INIT[31] 28_08
+CLBLM_R.SLICEL_X1.ALUT.INIT[32] 26_07
+CLBLM_R.SLICEL_X1.ALUT.INIT[33] 27_07
+CLBLM_R.SLICEL_X1.ALUT.INIT[34] 26_06
+CLBLM_R.SLICEL_X1.ALUT.INIT[35] 27_06
+CLBLM_R.SLICEL_X1.ALUT.INIT[36] 26_05
+CLBLM_R.SLICEL_X1.ALUT.INIT[37] 27_05
+CLBLM_R.SLICEL_X1.ALUT.INIT[38] 26_04
+CLBLM_R.SLICEL_X1.ALUT.INIT[39] 27_04
+CLBLM_R.SLICEL_X1.ALUT.INIT[40] 29_07
+CLBLM_R.SLICEL_X1.ALUT.INIT[41] 28_07
+CLBLM_R.SLICEL_X1.ALUT.INIT[42] 29_06
+CLBLM_R.SLICEL_X1.ALUT.INIT[43] 28_06
+CLBLM_R.SLICEL_X1.ALUT.INIT[44] 29_05
+CLBLM_R.SLICEL_X1.ALUT.INIT[45] 28_05
+CLBLM_R.SLICEL_X1.ALUT.INIT[46] 29_04
+CLBLM_R.SLICEL_X1.ALUT.INIT[47] 28_04
+CLBLM_R.SLICEL_X1.ALUT.INIT[48] 26_03
+CLBLM_R.SLICEL_X1.ALUT.INIT[49] 27_03
+CLBLM_R.SLICEL_X1.ALUT.INIT[50] 26_02
+CLBLM_R.SLICEL_X1.ALUT.INIT[51] 27_02
+CLBLM_R.SLICEL_X1.ALUT.INIT[52] 26_01
+CLBLM_R.SLICEL_X1.ALUT.INIT[53] 27_01
+CLBLM_R.SLICEL_X1.ALUT.INIT[54] 26_00
+CLBLM_R.SLICEL_X1.ALUT.INIT[55] 27_00
+CLBLM_R.SLICEL_X1.ALUT.INIT[56] 29_03
+CLBLM_R.SLICEL_X1.ALUT.INIT[57] 28_03
+CLBLM_R.SLICEL_X1.ALUT.INIT[58] 29_02
+CLBLM_R.SLICEL_X1.ALUT.INIT[59] 28_02
+CLBLM_R.SLICEL_X1.ALUT.INIT[60] 29_01
+CLBLM_R.SLICEL_X1.ALUT.INIT[61] 28_01
+CLBLM_R.SLICEL_X1.ALUT.INIT[62] 29_00
+CLBLM_R.SLICEL_X1.ALUT.INIT[63] 28_00
+CLBLM_R.SLICEL_X1.AOUTMUX.A5Q 30_05 !31_07 !31_09 !31_10
+CLBLM_R.SLICEL_X1.AOUTMUX.CY !30_05 31_07 !31_09 31_10
+CLBLM_R.SLICEL_X1.AOUTMUX.F7 30_05 !31_07 !31_09 31_10
+CLBLM_R.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
+CLBLM_R.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 31_09 !31_10
+CLBLM_R.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
+CLBLM_R.SLICEL_X1.B5FFMUX.IN_A 31_19
+CLBLM_R.SLICEL_X1.B5FFMUX.IN_B 31_18
+CLBLM_R.SLICEL_X1.B5FF.ZINI 31_23
+CLBLM_R.SLICEL_X1.B5FF.ZRST 00_16
+CLBLM_R.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
+CLBLM_R.SLICEL_X1.BFFMUX.CY !31_24 31_25 31_26 !31_27
+CLBLM_R.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26
+CLBLM_R.SLICEL_X1.BFFMUX.F8 !31_24 31_25 !31_26 31_27
+CLBLM_R.SLICEL_X1.BFFMUX.O5 31_24 31_25 !31_26 !31_27
+CLBLM_R.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25
+CLBLM_R.SLICEL_X1.BFFMUX.O6 31_24 !31_25 !31_26 !31_27
+CLBLM_R.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24
+CLBLM_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
+CLBLM_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26
+CLBLM_R.SLICEL_X1.BFF.ZINI 31_29
+CLBLM_R.SLICEL_X1.BFF.ZRST 31_30
+CLBLM_R.SLICEL_X1.BLUT.INIT[00] 26_31
+CLBLM_R.SLICEL_X1.BLUT.INIT[01] 27_31
+CLBLM_R.SLICEL_X1.BLUT.INIT[02] 26_30
+CLBLM_R.SLICEL_X1.BLUT.INIT[03] 27_30
+CLBLM_R.SLICEL_X1.BLUT.INIT[04] 26_29
+CLBLM_R.SLICEL_X1.BLUT.INIT[05] 27_29
+CLBLM_R.SLICEL_X1.BLUT.INIT[06] 26_28
+CLBLM_R.SLICEL_X1.BLUT.INIT[07] 27_28
+CLBLM_R.SLICEL_X1.BLUT.INIT[08] 29_31
+CLBLM_R.SLICEL_X1.BLUT.INIT[09] 28_31
+CLBLM_R.SLICEL_X1.BLUT.INIT[10] 29_30
+CLBLM_R.SLICEL_X1.BLUT.INIT[11] 28_30
+CLBLM_R.SLICEL_X1.BLUT.INIT[12] 29_29
+CLBLM_R.SLICEL_X1.BLUT.INIT[13] 28_29
+CLBLM_R.SLICEL_X1.BLUT.INIT[14] 29_28
+CLBLM_R.SLICEL_X1.BLUT.INIT[15] 28_28
+CLBLM_R.SLICEL_X1.BLUT.INIT[16] 26_27
+CLBLM_R.SLICEL_X1.BLUT.INIT[17] 27_27
+CLBLM_R.SLICEL_X1.BLUT.INIT[18] 26_26
+CLBLM_R.SLICEL_X1.BLUT.INIT[19] 27_26
+CLBLM_R.SLICEL_X1.BLUT.INIT[20] 26_25
+CLBLM_R.SLICEL_X1.BLUT.INIT[21] 27_25
+CLBLM_R.SLICEL_X1.BLUT.INIT[22] 26_24
+CLBLM_R.SLICEL_X1.BLUT.INIT[23] 27_24
+CLBLM_R.SLICEL_X1.BLUT.INIT[24] 29_27
+CLBLM_R.SLICEL_X1.BLUT.INIT[25] 28_27
+CLBLM_R.SLICEL_X1.BLUT.INIT[26] 29_26
+CLBLM_R.SLICEL_X1.BLUT.INIT[27] 28_26
+CLBLM_R.SLICEL_X1.BLUT.INIT[28] 29_25
+CLBLM_R.SLICEL_X1.BLUT.INIT[29] 28_25
+CLBLM_R.SLICEL_X1.BLUT.INIT[30] 29_24
+CLBLM_R.SLICEL_X1.BLUT.INIT[31] 28_24
+CLBLM_R.SLICEL_X1.BLUT.INIT[32] 26_23
+CLBLM_R.SLICEL_X1.BLUT.INIT[33] 27_23
+CLBLM_R.SLICEL_X1.BLUT.INIT[34] 26_22
+CLBLM_R.SLICEL_X1.BLUT.INIT[35] 27_22
+CLBLM_R.SLICEL_X1.BLUT.INIT[36] 26_21
+CLBLM_R.SLICEL_X1.BLUT.INIT[37] 27_21
+CLBLM_R.SLICEL_X1.BLUT.INIT[38] 26_20
+CLBLM_R.SLICEL_X1.BLUT.INIT[39] 27_20
+CLBLM_R.SLICEL_X1.BLUT.INIT[40] 29_23
+CLBLM_R.SLICEL_X1.BLUT.INIT[41] 28_23
+CLBLM_R.SLICEL_X1.BLUT.INIT[42] 29_22
+CLBLM_R.SLICEL_X1.BLUT.INIT[43] 28_22
+CLBLM_R.SLICEL_X1.BLUT.INIT[44] 29_21
+CLBLM_R.SLICEL_X1.BLUT.INIT[45] 28_21
+CLBLM_R.SLICEL_X1.BLUT.INIT[46] 29_20
+CLBLM_R.SLICEL_X1.BLUT.INIT[47] 28_20
+CLBLM_R.SLICEL_X1.BLUT.INIT[48] 26_19
+CLBLM_R.SLICEL_X1.BLUT.INIT[49] 27_19
+CLBLM_R.SLICEL_X1.BLUT.INIT[50] 26_18
+CLBLM_R.SLICEL_X1.BLUT.INIT[51] 27_18
+CLBLM_R.SLICEL_X1.BLUT.INIT[52] 26_17
+CLBLM_R.SLICEL_X1.BLUT.INIT[53] 27_17
+CLBLM_R.SLICEL_X1.BLUT.INIT[54] 26_16
+CLBLM_R.SLICEL_X1.BLUT.INIT[55] 27_16
+CLBLM_R.SLICEL_X1.BLUT.INIT[56] 29_19
+CLBLM_R.SLICEL_X1.BLUT.INIT[57] 28_19
+CLBLM_R.SLICEL_X1.BLUT.INIT[58] 29_18
+CLBLM_R.SLICEL_X1.BLUT.INIT[59] 28_18
+CLBLM_R.SLICEL_X1.BLUT.INIT[60] 29_17
+CLBLM_R.SLICEL_X1.BLUT.INIT[61] 28_17
+CLBLM_R.SLICEL_X1.BLUT.INIT[62] 29_16
+CLBLM_R.SLICEL_X1.BLUT.INIT[63] 28_16
+CLBLM_R.SLICEL_X1.BOUTMUX.B5Q !30_28 30_29 !31_20 !31_21
+CLBLM_R.SLICEL_X1.BOUTMUX.CY 30_28 !30_29 !31_20 31_21
+CLBLM_R.SLICEL_X1.BOUTMUX.F8 !30_28 30_29 !31_20 31_21
+CLBLM_R.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
+CLBLM_R.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 31_20 !31_21
+CLBLM_R.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
+CLBLM_R.SLICEL_X1.C5FFMUX.IN_A 31_44
+CLBLM_R.SLICEL_X1.C5FFMUX.IN_B 31_39
+CLBLM_R.SLICEL_X1.C5FF.ZINI 31_42
+CLBLM_R.SLICEL_X1.C5FF.ZRST 00_44
+CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_14
+CLBLM_R.SLICEL_X1.CARRY4.BCY0 00_08
+CLBLM_R.SLICEL_X1.CARRY4.CCY0 31_48
+CLBLM_R.SLICEL_X1.CARRY4.DCY0 31_49
+CLBLM_R.SLICEL_X1.CEUSEDMUX 00_36
+CLBLM_R.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
+CLBLM_R.SLICEL_X1.CFFMUX.CY 31_35 !31_36 31_37 !31_38
+CLBLM_R.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37
+CLBLM_R.SLICEL_X1.CFFMUX.F7 31_35 !31_36 !31_37 31_38
+CLBLM_R.SLICEL_X1.CFFMUX.O5 31_35 31_36 !31_37 !31_38
+CLBLM_R.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36
+CLBLM_R.SLICEL_X1.CFFMUX.O6 !31_35 31_36 !31_37 !31_38
+CLBLM_R.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36
+CLBLM_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
+CLBLM_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37
+CLBLM_R.SLICEL_X1.CFF.ZINI 31_34
+CLBLM_R.SLICEL_X1.CFF.ZRST 30_34
+CLBLM_R.SLICEL_X1.CLKINV 00_52
+CLBLM_R.SLICEL_X1.CLUT.INIT[00] 26_47
+CLBLM_R.SLICEL_X1.CLUT.INIT[01] 27_47
+CLBLM_R.SLICEL_X1.CLUT.INIT[02] 26_46
+CLBLM_R.SLICEL_X1.CLUT.INIT[03] 27_46
+CLBLM_R.SLICEL_X1.CLUT.INIT[04] 26_45
+CLBLM_R.SLICEL_X1.CLUT.INIT[05] 27_45
+CLBLM_R.SLICEL_X1.CLUT.INIT[06] 26_44
+CLBLM_R.SLICEL_X1.CLUT.INIT[07] 27_44
+CLBLM_R.SLICEL_X1.CLUT.INIT[08] 29_47
+CLBLM_R.SLICEL_X1.CLUT.INIT[09] 28_47
+CLBLM_R.SLICEL_X1.CLUT.INIT[10] 29_46
+CLBLM_R.SLICEL_X1.CLUT.INIT[11] 28_46
+CLBLM_R.SLICEL_X1.CLUT.INIT[12] 29_45
+CLBLM_R.SLICEL_X1.CLUT.INIT[13] 28_45
+CLBLM_R.SLICEL_X1.CLUT.INIT[14] 29_44
+CLBLM_R.SLICEL_X1.CLUT.INIT[15] 28_44
+CLBLM_R.SLICEL_X1.CLUT.INIT[16] 26_43
+CLBLM_R.SLICEL_X1.CLUT.INIT[17] 27_43
+CLBLM_R.SLICEL_X1.CLUT.INIT[18] 26_42
+CLBLM_R.SLICEL_X1.CLUT.INIT[19] 27_42
+CLBLM_R.SLICEL_X1.CLUT.INIT[20] 26_41
+CLBLM_R.SLICEL_X1.CLUT.INIT[21] 27_41
+CLBLM_R.SLICEL_X1.CLUT.INIT[22] 26_40
+CLBLM_R.SLICEL_X1.CLUT.INIT[23] 27_40
+CLBLM_R.SLICEL_X1.CLUT.INIT[24] 29_43
+CLBLM_R.SLICEL_X1.CLUT.INIT[25] 28_43
+CLBLM_R.SLICEL_X1.CLUT.INIT[26] 29_42
+CLBLM_R.SLICEL_X1.CLUT.INIT[27] 28_42
+CLBLM_R.SLICEL_X1.CLUT.INIT[28] 29_41
+CLBLM_R.SLICEL_X1.CLUT.INIT[29] 28_41
+CLBLM_R.SLICEL_X1.CLUT.INIT[30] 29_40
+CLBLM_R.SLICEL_X1.CLUT.INIT[31] 28_40
+CLBLM_R.SLICEL_X1.CLUT.INIT[32] 26_39
+CLBLM_R.SLICEL_X1.CLUT.INIT[33] 27_39
+CLBLM_R.SLICEL_X1.CLUT.INIT[34] 26_38
+CLBLM_R.SLICEL_X1.CLUT.INIT[35] 27_38
+CLBLM_R.SLICEL_X1.CLUT.INIT[36] 26_37
+CLBLM_R.SLICEL_X1.CLUT.INIT[37] 27_37
+CLBLM_R.SLICEL_X1.CLUT.INIT[38] 26_36
+CLBLM_R.SLICEL_X1.CLUT.INIT[39] 27_36
+CLBLM_R.SLICEL_X1.CLUT.INIT[40] 29_39
+CLBLM_R.SLICEL_X1.CLUT.INIT[41] 28_39
+CLBLM_R.SLICEL_X1.CLUT.INIT[42] 29_38
+CLBLM_R.SLICEL_X1.CLUT.INIT[43] 28_38
+CLBLM_R.SLICEL_X1.CLUT.INIT[44] 29_37
+CLBLM_R.SLICEL_X1.CLUT.INIT[45] 28_37
+CLBLM_R.SLICEL_X1.CLUT.INIT[46] 29_36
+CLBLM_R.SLICEL_X1.CLUT.INIT[47] 28_36
+CLBLM_R.SLICEL_X1.CLUT.INIT[48] 26_35
+CLBLM_R.SLICEL_X1.CLUT.INIT[49] 27_35
+CLBLM_R.SLICEL_X1.CLUT.INIT[50] 26_34
+CLBLM_R.SLICEL_X1.CLUT.INIT[51] 27_34
+CLBLM_R.SLICEL_X1.CLUT.INIT[52] 26_33
+CLBLM_R.SLICEL_X1.CLUT.INIT[53] 27_33
+CLBLM_R.SLICEL_X1.CLUT.INIT[54] 26_32
+CLBLM_R.SLICEL_X1.CLUT.INIT[55] 27_32
+CLBLM_R.SLICEL_X1.CLUT.INIT[56] 29_35
+CLBLM_R.SLICEL_X1.CLUT.INIT[57] 28_35
+CLBLM_R.SLICEL_X1.CLUT.INIT[58] 29_34
+CLBLM_R.SLICEL_X1.CLUT.INIT[59] 28_34
+CLBLM_R.SLICEL_X1.CLUT.INIT[60] 29_33
+CLBLM_R.SLICEL_X1.CLUT.INIT[61] 28_33
+CLBLM_R.SLICEL_X1.CLUT.INIT[62] 29_32
+CLBLM_R.SLICEL_X1.CLUT.INIT[63] 28_32
+CLBLM_R.SLICEL_X1.COUTMUX.C5Q 30_41 !30_42 !31_40 !31_43
+CLBLM_R.SLICEL_X1.COUTMUX.CY !30_41 30_42 31_40 !31_43
+CLBLM_R.SLICEL_X1.COUTMUX.F7 30_41 !30_42 31_40 !31_43
+CLBLM_R.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
+CLBLM_R.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
+CLBLM_R.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
+CLBLM_R.SLICEL_X1.D5FFMUX.IN_A 31_55
+CLBLM_R.SLICEL_X1.D5FFMUX.IN_B 31_54
+CLBLM_R.SLICEL_X1.D5FF.ZINI 31_52
+CLBLM_R.SLICEL_X1.D5FF.ZRST 00_56
+CLBLM_R.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
+CLBLM_R.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
+CLBLM_R.SLICEL_X1.DFFMUX.DX !30_58 !31_60 31_61 !31_62
+CLBLM_R.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61
+CLBLM_R.SLICEL_X1.DFFMUX.O5 30_58 31_60 !31_61 !31_62
+CLBLM_R.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60
+CLBLM_R.SLICEL_X1.DFFMUX.O6 !30_58 31_60 !31_61 !31_62
+CLBLM_R.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60
+CLBLM_R.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
+CLBLM_R.SLICEL_X1.DFF.ZINI 31_59
+CLBLM_R.SLICEL_X1.DFF.ZRST 31_50
+CLBLM_R.SLICEL_X1.DLUT.INIT[00] 26_63
+CLBLM_R.SLICEL_X1.DLUT.INIT[01] 27_63
+CLBLM_R.SLICEL_X1.DLUT.INIT[02] 26_62
+CLBLM_R.SLICEL_X1.DLUT.INIT[03] 27_62
+CLBLM_R.SLICEL_X1.DLUT.INIT[04] 26_61
+CLBLM_R.SLICEL_X1.DLUT.INIT[05] 27_61
+CLBLM_R.SLICEL_X1.DLUT.INIT[06] 26_60
+CLBLM_R.SLICEL_X1.DLUT.INIT[07] 27_60
+CLBLM_R.SLICEL_X1.DLUT.INIT[08] 29_63
+CLBLM_R.SLICEL_X1.DLUT.INIT[09] 28_63
+CLBLM_R.SLICEL_X1.DLUT.INIT[10] 29_62
+CLBLM_R.SLICEL_X1.DLUT.INIT[11] 28_62
+CLBLM_R.SLICEL_X1.DLUT.INIT[12] 29_61
+CLBLM_R.SLICEL_X1.DLUT.INIT[13] 28_61
+CLBLM_R.SLICEL_X1.DLUT.INIT[14] 29_60
+CLBLM_R.SLICEL_X1.DLUT.INIT[15] 28_60
+CLBLM_R.SLICEL_X1.DLUT.INIT[16] 26_59
+CLBLM_R.SLICEL_X1.DLUT.INIT[17] 27_59
+CLBLM_R.SLICEL_X1.DLUT.INIT[18] 26_58
+CLBLM_R.SLICEL_X1.DLUT.INIT[19] 27_58
+CLBLM_R.SLICEL_X1.DLUT.INIT[20] 26_57
+CLBLM_R.SLICEL_X1.DLUT.INIT[21] 27_57
+CLBLM_R.SLICEL_X1.DLUT.INIT[22] 26_56
+CLBLM_R.SLICEL_X1.DLUT.INIT[23] 27_56
+CLBLM_R.SLICEL_X1.DLUT.INIT[24] 29_59
+CLBLM_R.SLICEL_X1.DLUT.INIT[25] 28_59
+CLBLM_R.SLICEL_X1.DLUT.INIT[26] 29_58
+CLBLM_R.SLICEL_X1.DLUT.INIT[27] 28_58
+CLBLM_R.SLICEL_X1.DLUT.INIT[28] 29_57
+CLBLM_R.SLICEL_X1.DLUT.INIT[29] 28_57
+CLBLM_R.SLICEL_X1.DLUT.INIT[30] 29_56
+CLBLM_R.SLICEL_X1.DLUT.INIT[31] 28_56
+CLBLM_R.SLICEL_X1.DLUT.INIT[32] 26_55
+CLBLM_R.SLICEL_X1.DLUT.INIT[33] 27_55
+CLBLM_R.SLICEL_X1.DLUT.INIT[34] 26_54
+CLBLM_R.SLICEL_X1.DLUT.INIT[35] 27_54
+CLBLM_R.SLICEL_X1.DLUT.INIT[36] 26_53
+CLBLM_R.SLICEL_X1.DLUT.INIT[37] 27_53
+CLBLM_R.SLICEL_X1.DLUT.INIT[38] 26_52
+CLBLM_R.SLICEL_X1.DLUT.INIT[39] 27_52
+CLBLM_R.SLICEL_X1.DLUT.INIT[40] 29_55
+CLBLM_R.SLICEL_X1.DLUT.INIT[41] 28_55
+CLBLM_R.SLICEL_X1.DLUT.INIT[42] 29_54
+CLBLM_R.SLICEL_X1.DLUT.INIT[43] 28_54
+CLBLM_R.SLICEL_X1.DLUT.INIT[44] 29_53
+CLBLM_R.SLICEL_X1.DLUT.INIT[45] 28_53
+CLBLM_R.SLICEL_X1.DLUT.INIT[46] 29_52
+CLBLM_R.SLICEL_X1.DLUT.INIT[47] 28_52
+CLBLM_R.SLICEL_X1.DLUT.INIT[48] 26_51
+CLBLM_R.SLICEL_X1.DLUT.INIT[49] 27_51
+CLBLM_R.SLICEL_X1.DLUT.INIT[50] 26_50
+CLBLM_R.SLICEL_X1.DLUT.INIT[51] 27_50
+CLBLM_R.SLICEL_X1.DLUT.INIT[52] 26_49
+CLBLM_R.SLICEL_X1.DLUT.INIT[53] 27_49
+CLBLM_R.SLICEL_X1.DLUT.INIT[54] 26_48
+CLBLM_R.SLICEL_X1.DLUT.INIT[55] 27_48
+CLBLM_R.SLICEL_X1.DLUT.INIT[56] 29_51
+CLBLM_R.SLICEL_X1.DLUT.INIT[57] 28_51
+CLBLM_R.SLICEL_X1.DLUT.INIT[58] 29_50
+CLBLM_R.SLICEL_X1.DLUT.INIT[59] 28_50
+CLBLM_R.SLICEL_X1.DLUT.INIT[60] 29_49
+CLBLM_R.SLICEL_X1.DLUT.INIT[61] 28_49
+CLBLM_R.SLICEL_X1.DLUT.INIT[62] 29_48
+CLBLM_R.SLICEL_X1.DLUT.INIT[63] 28_48
+CLBLM_R.SLICEL_X1.DOUTMUX.CY 30_53 !31_53 !31_56 31_57
+CLBLM_R.SLICEL_X1.DOUTMUX.D5Q !30_53 31_53 !31_56 !31_57
+CLBLM_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
+CLBLM_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
+CLBLM_R.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
+CLBLM_R.SLICEL_X1.FFSYNC 01_31
+CLBLM_R.SLICEL_X1.LATCH 31_32
+CLBLM_R.SLICEL_X1.NOCLKINV !00_52
+CLBLM_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
+CLBLM_R.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
+CLBLM_R.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
+CLBLM_R.SLICEL_X1.PRECYINIT.C1 !31_12 !31_13 01_11
+CLBLM_R.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
+CLBLM_R.SLICEL_X1.PRECYINIT.CIN !01_11 !31_13 31_12
+CLBLM_R.SLICEL_X1.SRUSEDMUX 00_32
+CLBLM_R.SLICEM_X0.A5FFMUX.IN_A 30_09
+CLBLM_R.SLICEM_X0.A5FFMUX.IN_B 30_10
+CLBLM_R.SLICEM_X0.A5FF.ZINI 31_06
+CLBLM_R.SLICEM_X0.A5FF.ZRST 01_07
+CLBLM_R.SLICEM_X0.AFFMUX.AX !30_00 30_01 !30_02 !30_03
+CLBLM_R.SLICEM_X0.AFFMUX.CY 30_00 !30_01 30_02 !30_03
+CLBLM_R.SLICEM_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02
+CLBLM_R.SLICEM_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
+CLBLM_R.SLICEM_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
+CLBLM_R.SLICEM_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03
+CLBLM_R.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
+CLBLM_R.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
+CLBLM_R.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02
+CLBLM_R.SLICEM_X0.AFF.ZINI 31_03
+CLBLM_R.SLICEM_X0.AFF.ZRST 30_12
+CLBLM_R.SLICEM_X0.ALUT.DI1MUX.AI 00_00
+CLBLM_R.SLICEM_X0.ALUT.DI1MUX.BDI1_BMC31 !00_00
+CLBLM_R.SLICEM_X0.ALUT.INIT[00] 34_15
+CLBLM_R.SLICEM_X0.ALUT.INIT[01] 35_15
+CLBLM_R.SLICEM_X0.ALUT.INIT[02] 34_14
+CLBLM_R.SLICEM_X0.ALUT.INIT[03] 35_14
+CLBLM_R.SLICEM_X0.ALUT.INIT[04] 34_13
+CLBLM_R.SLICEM_X0.ALUT.INIT[05] 35_13
+CLBLM_R.SLICEM_X0.ALUT.INIT[06] 34_12
+CLBLM_R.SLICEM_X0.ALUT.INIT[07] 35_12
+CLBLM_R.SLICEM_X0.ALUT.INIT[08] 32_15
+CLBLM_R.SLICEM_X0.ALUT.INIT[09] 33_15
+CLBLM_R.SLICEM_X0.ALUT.INIT[10] 32_14
+CLBLM_R.SLICEM_X0.ALUT.INIT[11] 33_14
+CLBLM_R.SLICEM_X0.ALUT.INIT[12] 32_13
+CLBLM_R.SLICEM_X0.ALUT.INIT[13] 33_13
+CLBLM_R.SLICEM_X0.ALUT.INIT[14] 32_12
+CLBLM_R.SLICEM_X0.ALUT.INIT[15] 33_12
+CLBLM_R.SLICEM_X0.ALUT.INIT[16] 34_11
+CLBLM_R.SLICEM_X0.ALUT.INIT[17] 35_11
+CLBLM_R.SLICEM_X0.ALUT.INIT[18] 34_10
+CLBLM_R.SLICEM_X0.ALUT.INIT[19] 35_10
+CLBLM_R.SLICEM_X0.ALUT.INIT[20] 34_09
+CLBLM_R.SLICEM_X0.ALUT.INIT[21] 35_09
+CLBLM_R.SLICEM_X0.ALUT.INIT[22] 34_08
+CLBLM_R.SLICEM_X0.ALUT.INIT[23] 35_08
+CLBLM_R.SLICEM_X0.ALUT.INIT[24] 32_11
+CLBLM_R.SLICEM_X0.ALUT.INIT[25] 33_11
+CLBLM_R.SLICEM_X0.ALUT.INIT[26] 32_10
+CLBLM_R.SLICEM_X0.ALUT.INIT[27] 33_10
+CLBLM_R.SLICEM_X0.ALUT.INIT[28] 32_09
+CLBLM_R.SLICEM_X0.ALUT.INIT[29] 33_09
+CLBLM_R.SLICEM_X0.ALUT.INIT[30] 32_08
+CLBLM_R.SLICEM_X0.ALUT.INIT[31] 33_08
+CLBLM_R.SLICEM_X0.ALUT.INIT[32] 34_07
+CLBLM_R.SLICEM_X0.ALUT.INIT[33] 35_07
+CLBLM_R.SLICEM_X0.ALUT.INIT[34] 34_06
+CLBLM_R.SLICEM_X0.ALUT.INIT[35] 35_06
+CLBLM_R.SLICEM_X0.ALUT.INIT[36] 34_05
+CLBLM_R.SLICEM_X0.ALUT.INIT[37] 35_05
+CLBLM_R.SLICEM_X0.ALUT.INIT[38] 34_04
+CLBLM_R.SLICEM_X0.ALUT.INIT[39] 35_04
+CLBLM_R.SLICEM_X0.ALUT.INIT[40] 32_07
+CLBLM_R.SLICEM_X0.ALUT.INIT[41] 33_07
+CLBLM_R.SLICEM_X0.ALUT.INIT[42] 32_06
+CLBLM_R.SLICEM_X0.ALUT.INIT[43] 33_06
+CLBLM_R.SLICEM_X0.ALUT.INIT[44] 32_05
+CLBLM_R.SLICEM_X0.ALUT.INIT[45] 33_05
+CLBLM_R.SLICEM_X0.ALUT.INIT[46] 32_04
+CLBLM_R.SLICEM_X0.ALUT.INIT[47] 33_04
+CLBLM_R.SLICEM_X0.ALUT.INIT[48] 34_03
+CLBLM_R.SLICEM_X0.ALUT.INIT[49] 35_03
+CLBLM_R.SLICEM_X0.ALUT.INIT[50] 34_02
+CLBLM_R.SLICEM_X0.ALUT.INIT[51] 35_02
+CLBLM_R.SLICEM_X0.ALUT.INIT[52] 34_01
+CLBLM_R.SLICEM_X0.ALUT.INIT[53] 35_01
+CLBLM_R.SLICEM_X0.ALUT.INIT[54] 34_00
+CLBLM_R.SLICEM_X0.ALUT.INIT[55] 35_00
+CLBLM_R.SLICEM_X0.ALUT.INIT[56] 32_03
+CLBLM_R.SLICEM_X0.ALUT.INIT[57] 33_03
+CLBLM_R.SLICEM_X0.ALUT.INIT[58] 32_02
+CLBLM_R.SLICEM_X0.ALUT.INIT[59] 33_02
+CLBLM_R.SLICEM_X0.ALUT.INIT[60] 32_01
+CLBLM_R.SLICEM_X0.ALUT.INIT[61] 33_01
+CLBLM_R.SLICEM_X0.ALUT.INIT[62] 32_00
+CLBLM_R.SLICEM_X0.ALUT.INIT[63] 33_00
+CLBLM_R.SLICEM_X0.ALUT.RAM 31_16
+CLBLM_R.SLICEM_X0.ALUT.SMALL 00_04
+CLBLM_R.SLICEM_X0.ALUT.SRL 30_16
+CLBLM_R.SLICEM_X0.AOUTMUX.A5Q !30_06 30_07 !30_08 !30_11
+CLBLM_R.SLICEM_X0.AOUTMUX.CY 30_06 !30_07 30_08 !30_11
+CLBLM_R.SLICEM_X0.AOUTMUX.F7 30_06 30_07 !30_08 !30_11
+CLBLM_R.SLICEM_X0.AOUTMUX.O5 30_06 !30_07 !30_08 30_11
+CLBLM_R.SLICEM_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
+CLBLM_R.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
+CLBLM_R.SLICEM_X0.B5FFMUX.IN_A 30_19
+CLBLM_R.SLICEM_X0.B5FFMUX.IN_B 30_18
+CLBLM_R.SLICEM_X0.B5FF.ZINI 31_22
+CLBLM_R.SLICEM_X0.B5FF.ZRST 01_19
+CLBLM_R.SLICEM_X0.BFFMUX.BX !30_24 !30_25 30_26 !30_27
+CLBLM_R.SLICEM_X0.BFFMUX.CY !30_24 30_25 !30_26 30_27
+CLBLM_R.SLICEM_X0.BFFMUX.CY !30_24 !30_26 30_25 30_27
+CLBLM_R.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
+CLBLM_R.SLICEM_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
+CLBLM_R.SLICEM_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27
+CLBLM_R.SLICEM_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
+CLBLM_R.SLICEM_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24
+CLBLM_R.SLICEM_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
+CLBLM_R.SLICEM_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25
+CLBLM_R.SLICEM_X0.BFF.ZINI 31_28
+CLBLM_R.SLICEM_X0.BFF.ZRST 30_30
+CLBLM_R.SLICEM_X0.BLUT.DI1MUX.BI 00_20
+CLBLM_R.SLICEM_X0.BLUT.DI1MUX.DI_CMC31 !00_20
+CLBLM_R.SLICEM_X0.BLUT.INIT[00] 34_31
+CLBLM_R.SLICEM_X0.BLUT.INIT[01] 35_31
+CLBLM_R.SLICEM_X0.BLUT.INIT[02] 34_30
+CLBLM_R.SLICEM_X0.BLUT.INIT[03] 35_30
+CLBLM_R.SLICEM_X0.BLUT.INIT[04] 34_29
+CLBLM_R.SLICEM_X0.BLUT.INIT[05] 35_29
+CLBLM_R.SLICEM_X0.BLUT.INIT[06] 34_28
+CLBLM_R.SLICEM_X0.BLUT.INIT[07] 35_28
+CLBLM_R.SLICEM_X0.BLUT.INIT[08] 32_31
+CLBLM_R.SLICEM_X0.BLUT.INIT[09] 33_31
+CLBLM_R.SLICEM_X0.BLUT.INIT[10] 32_30
+CLBLM_R.SLICEM_X0.BLUT.INIT[11] 33_30
+CLBLM_R.SLICEM_X0.BLUT.INIT[12] 32_29
+CLBLM_R.SLICEM_X0.BLUT.INIT[13] 33_29
+CLBLM_R.SLICEM_X0.BLUT.INIT[14] 32_28
+CLBLM_R.SLICEM_X0.BLUT.INIT[15] 33_28
+CLBLM_R.SLICEM_X0.BLUT.INIT[16] 34_27
+CLBLM_R.SLICEM_X0.BLUT.INIT[17] 35_27
+CLBLM_R.SLICEM_X0.BLUT.INIT[18] 34_26
+CLBLM_R.SLICEM_X0.BLUT.INIT[19] 35_26
+CLBLM_R.SLICEM_X0.BLUT.INIT[20] 34_25
+CLBLM_R.SLICEM_X0.BLUT.INIT[21] 35_25
+CLBLM_R.SLICEM_X0.BLUT.INIT[22] 34_24
+CLBLM_R.SLICEM_X0.BLUT.INIT[23] 35_24
+CLBLM_R.SLICEM_X0.BLUT.INIT[24] 32_27
+CLBLM_R.SLICEM_X0.BLUT.INIT[25] 33_27
+CLBLM_R.SLICEM_X0.BLUT.INIT[26] 32_26
+CLBLM_R.SLICEM_X0.BLUT.INIT[27] 33_26
+CLBLM_R.SLICEM_X0.BLUT.INIT[28] 32_25
+CLBLM_R.SLICEM_X0.BLUT.INIT[29] 33_25
+CLBLM_R.SLICEM_X0.BLUT.INIT[30] 32_24
+CLBLM_R.SLICEM_X0.BLUT.INIT[31] 33_24
+CLBLM_R.SLICEM_X0.BLUT.INIT[32] 34_23
+CLBLM_R.SLICEM_X0.BLUT.INIT[33] 35_23
+CLBLM_R.SLICEM_X0.BLUT.INIT[34] 34_22
+CLBLM_R.SLICEM_X0.BLUT.INIT[35] 35_22
+CLBLM_R.SLICEM_X0.BLUT.INIT[36] 34_21
+CLBLM_R.SLICEM_X0.BLUT.INIT[37] 35_21
+CLBLM_R.SLICEM_X0.BLUT.INIT[38] 34_20
+CLBLM_R.SLICEM_X0.BLUT.INIT[39] 35_20
+CLBLM_R.SLICEM_X0.BLUT.INIT[40] 32_23
+CLBLM_R.SLICEM_X0.BLUT.INIT[41] 33_23
+CLBLM_R.SLICEM_X0.BLUT.INIT[42] 32_22
+CLBLM_R.SLICEM_X0.BLUT.INIT[43] 33_22
+CLBLM_R.SLICEM_X0.BLUT.INIT[44] 32_21
+CLBLM_R.SLICEM_X0.BLUT.INIT[45] 33_21
+CLBLM_R.SLICEM_X0.BLUT.INIT[46] 32_20
+CLBLM_R.SLICEM_X0.BLUT.INIT[47] 33_20
+CLBLM_R.SLICEM_X0.BLUT.INIT[48] 34_19
+CLBLM_R.SLICEM_X0.BLUT.INIT[49] 35_19
+CLBLM_R.SLICEM_X0.BLUT.INIT[50] 34_18
+CLBLM_R.SLICEM_X0.BLUT.INIT[51] 35_18
+CLBLM_R.SLICEM_X0.BLUT.INIT[52] 34_17
+CLBLM_R.SLICEM_X0.BLUT.INIT[53] 35_17
+CLBLM_R.SLICEM_X0.BLUT.INIT[54] 34_16
+CLBLM_R.SLICEM_X0.BLUT.INIT[55] 35_16
+CLBLM_R.SLICEM_X0.BLUT.INIT[56] 32_19
+CLBLM_R.SLICEM_X0.BLUT.INIT[57] 33_19
+CLBLM_R.SLICEM_X0.BLUT.INIT[58] 32_18
+CLBLM_R.SLICEM_X0.BLUT.INIT[59] 33_18
+CLBLM_R.SLICEM_X0.BLUT.INIT[60] 32_17
+CLBLM_R.SLICEM_X0.BLUT.INIT[61] 33_17
+CLBLM_R.SLICEM_X0.BLUT.INIT[62] 32_16
+CLBLM_R.SLICEM_X0.BLUT.INIT[63] 33_16
+CLBLM_R.SLICEM_X0.BLUT.RAM 31_17
+CLBLM_R.SLICEM_X0.BLUT.SMALL 00_24
+CLBLM_R.SLICEM_X0.BLUT.SRL 30_17
+CLBLM_R.SLICEM_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
+CLBLM_R.SLICEM_X0.BOUTMUX.CY !30_20 30_21 30_22 !30_23
+CLBLM_R.SLICEM_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
+CLBLM_R.SLICEM_X0.BOUTMUX.O5 30_20 !30_21 30_22 !30_23
+CLBLM_R.SLICEM_X0.BOUTMUX.O6 30_20 !30_21 !30_22 !30_23
+CLBLM_R.SLICEM_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
+CLBLM_R.SLICEM_X0.C5FFMUX.IN_A 31_45
+CLBLM_R.SLICEM_X0.C5FFMUX.IN_B 30_39
+CLBLM_R.SLICEM_X0.C5FF.ZINI 31_41
+CLBLM_R.SLICEM_X0.C5FF.ZRST 01_47
+CLBLM_R.SLICEM_X0.CARRY4.ACY0 30_15
+CLBLM_R.SLICEM_X0.CARRY4.BCY0 01_15
+CLBLM_R.SLICEM_X0.CARRY4.CCY0 30_48
+CLBLM_R.SLICEM_X0.CARRY4.DCY0 30_49
+CLBLM_R.SLICEM_X0.CEUSEDMUX 01_39
+CLBLM_R.SLICEM_X0.CFFMUX.CX !30_35 30_36 !30_37 !30_38
+CLBLM_R.SLICEM_X0.CFFMUX.CY 30_35 !30_36 30_37 !30_38
+CLBLM_R.SLICEM_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37
+CLBLM_R.SLICEM_X0.CFFMUX.F7 30_35 30_36 !30_37 !30_38
+CLBLM_R.SLICEM_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
+CLBLM_R.SLICEM_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38
+CLBLM_R.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
+CLBLM_R.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
+CLBLM_R.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37
+CLBLM_R.SLICEM_X0.CFF.ZINI 31_33
+CLBLM_R.SLICEM_X0.CFF.ZRST 30_33
+CLBLM_R.SLICEM_X0.CLKINV 01_51
+CLBLM_R.SLICEM_X0.CLUT.DI1MUX.CI 01_43
+CLBLM_R.SLICEM_X0.CLUT.DI1MUX.DI_DMC31 !01_43
+CLBLM_R.SLICEM_X0.CLUT.INIT[00] 34_47
+CLBLM_R.SLICEM_X0.CLUT.INIT[01] 35_47
+CLBLM_R.SLICEM_X0.CLUT.INIT[02] 34_46
+CLBLM_R.SLICEM_X0.CLUT.INIT[03] 35_46
+CLBLM_R.SLICEM_X0.CLUT.INIT[04] 34_45
+CLBLM_R.SLICEM_X0.CLUT.INIT[05] 35_45
+CLBLM_R.SLICEM_X0.CLUT.INIT[06] 34_44
+CLBLM_R.SLICEM_X0.CLUT.INIT[07] 35_44
+CLBLM_R.SLICEM_X0.CLUT.INIT[08] 32_47
+CLBLM_R.SLICEM_X0.CLUT.INIT[09] 33_47
+CLBLM_R.SLICEM_X0.CLUT.INIT[10] 32_46
+CLBLM_R.SLICEM_X0.CLUT.INIT[11] 33_46
+CLBLM_R.SLICEM_X0.CLUT.INIT[12] 32_45
+CLBLM_R.SLICEM_X0.CLUT.INIT[13] 33_45
+CLBLM_R.SLICEM_X0.CLUT.INIT[14] 32_44
+CLBLM_R.SLICEM_X0.CLUT.INIT[15] 33_44
+CLBLM_R.SLICEM_X0.CLUT.INIT[16] 34_43
+CLBLM_R.SLICEM_X0.CLUT.INIT[17] 35_43
+CLBLM_R.SLICEM_X0.CLUT.INIT[18] 34_42
+CLBLM_R.SLICEM_X0.CLUT.INIT[19] 35_42
+CLBLM_R.SLICEM_X0.CLUT.INIT[20] 34_41
+CLBLM_R.SLICEM_X0.CLUT.INIT[21] 35_41
+CLBLM_R.SLICEM_X0.CLUT.INIT[22] 34_40
+CLBLM_R.SLICEM_X0.CLUT.INIT[23] 35_40
+CLBLM_R.SLICEM_X0.CLUT.INIT[24] 32_43
+CLBLM_R.SLICEM_X0.CLUT.INIT[25] 33_43
+CLBLM_R.SLICEM_X0.CLUT.INIT[26] 32_42
+CLBLM_R.SLICEM_X0.CLUT.INIT[27] 33_42
+CLBLM_R.SLICEM_X0.CLUT.INIT[28] 32_41
+CLBLM_R.SLICEM_X0.CLUT.INIT[29] 33_41
+CLBLM_R.SLICEM_X0.CLUT.INIT[30] 32_40
+CLBLM_R.SLICEM_X0.CLUT.INIT[31] 33_40
+CLBLM_R.SLICEM_X0.CLUT.INIT[32] 34_39
+CLBLM_R.SLICEM_X0.CLUT.INIT[33] 35_39
+CLBLM_R.SLICEM_X0.CLUT.INIT[34] 34_38
+CLBLM_R.SLICEM_X0.CLUT.INIT[35] 35_38
+CLBLM_R.SLICEM_X0.CLUT.INIT[36] 34_37
+CLBLM_R.SLICEM_X0.CLUT.INIT[37] 35_37
+CLBLM_R.SLICEM_X0.CLUT.INIT[38] 34_36
+CLBLM_R.SLICEM_X0.CLUT.INIT[39] 35_36
+CLBLM_R.SLICEM_X0.CLUT.INIT[40] 32_39
+CLBLM_R.SLICEM_X0.CLUT.INIT[41] 33_39
+CLBLM_R.SLICEM_X0.CLUT.INIT[42] 32_38
+CLBLM_R.SLICEM_X0.CLUT.INIT[43] 33_38
+CLBLM_R.SLICEM_X0.CLUT.INIT[44] 32_37
+CLBLM_R.SLICEM_X0.CLUT.INIT[45] 33_37
+CLBLM_R.SLICEM_X0.CLUT.INIT[46] 32_36
+CLBLM_R.SLICEM_X0.CLUT.INIT[47] 33_36
+CLBLM_R.SLICEM_X0.CLUT.INIT[48] 34_35
+CLBLM_R.SLICEM_X0.CLUT.INIT[49] 35_35
+CLBLM_R.SLICEM_X0.CLUT.INIT[50] 34_34
+CLBLM_R.SLICEM_X0.CLUT.INIT[51] 35_34
+CLBLM_R.SLICEM_X0.CLUT.INIT[52] 34_33
+CLBLM_R.SLICEM_X0.CLUT.INIT[53] 35_33
+CLBLM_R.SLICEM_X0.CLUT.INIT[54] 34_32
+CLBLM_R.SLICEM_X0.CLUT.INIT[55] 35_32
+CLBLM_R.SLICEM_X0.CLUT.INIT[56] 32_35
+CLBLM_R.SLICEM_X0.CLUT.INIT[57] 33_35
+CLBLM_R.SLICEM_X0.CLUT.INIT[58] 32_34
+CLBLM_R.SLICEM_X0.CLUT.INIT[59] 33_34
+CLBLM_R.SLICEM_X0.CLUT.INIT[60] 32_33
+CLBLM_R.SLICEM_X0.CLUT.INIT[61] 33_33
+CLBLM_R.SLICEM_X0.CLUT.INIT[62] 32_32
+CLBLM_R.SLICEM_X0.CLUT.INIT[63] 33_32
+CLBLM_R.SLICEM_X0.CLUT.RAM 31_46
+CLBLM_R.SLICEM_X0.CLUT.SMALL 00_28
+CLBLM_R.SLICEM_X0.CLUT.SRL 30_46
+CLBLM_R.SLICEM_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
+CLBLM_R.SLICEM_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
+CLBLM_R.SLICEM_X0.COUTMUX.F7 30_40 30_43 !30_44 !30_45
+CLBLM_R.SLICEM_X0.COUTMUX.O5 30_40 !30_43 !30_44 30_45
+CLBLM_R.SLICEM_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
+CLBLM_R.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
+CLBLM_R.SLICEM_X0.D5FFMUX.IN_A 30_55
+CLBLM_R.SLICEM_X0.D5FFMUX.IN_B 30_54
+CLBLM_R.SLICEM_X0.D5FF.ZINI 31_51
+CLBLM_R.SLICEM_X0.D5FF.ZRST 01_55
+CLBLM_R.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
+CLBLM_R.SLICEM_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
+CLBLM_R.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
+CLBLM_R.SLICEM_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61
+CLBLM_R.SLICEM_X0.DFFMUX.MC31 !30_59 !30_60 30_61 30_62
+CLBLM_R.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
+CLBLM_R.SLICEM_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62
+CLBLM_R.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
+CLBLM_R.SLICEM_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59
+CLBLM_R.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
+CLBLM_R.SLICEM_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60
+CLBLM_R.SLICEM_X0.DFF.ZINI 31_58
+CLBLM_R.SLICEM_X0.DFF.ZRST 30_50
+CLBLM_R.SLICEM_X0.DLUT.INIT[00] 34_63
+CLBLM_R.SLICEM_X0.DLUT.INIT[01] 35_63
+CLBLM_R.SLICEM_X0.DLUT.INIT[02] 34_62
+CLBLM_R.SLICEM_X0.DLUT.INIT[03] 35_62
+CLBLM_R.SLICEM_X0.DLUT.INIT[04] 34_61
+CLBLM_R.SLICEM_X0.DLUT.INIT[05] 35_61
+CLBLM_R.SLICEM_X0.DLUT.INIT[06] 34_60
+CLBLM_R.SLICEM_X0.DLUT.INIT[07] 35_60
+CLBLM_R.SLICEM_X0.DLUT.INIT[08] 32_63
+CLBLM_R.SLICEM_X0.DLUT.INIT[09] 33_63
+CLBLM_R.SLICEM_X0.DLUT.INIT[10] 32_62
+CLBLM_R.SLICEM_X0.DLUT.INIT[11] 33_62
+CLBLM_R.SLICEM_X0.DLUT.INIT[12] 32_61
+CLBLM_R.SLICEM_X0.DLUT.INIT[13] 33_61
+CLBLM_R.SLICEM_X0.DLUT.INIT[14] 32_60
+CLBLM_R.SLICEM_X0.DLUT.INIT[15] 33_60
+CLBLM_R.SLICEM_X0.DLUT.INIT[16] 34_59
+CLBLM_R.SLICEM_X0.DLUT.INIT[17] 35_59
+CLBLM_R.SLICEM_X0.DLUT.INIT[18] 34_58
+CLBLM_R.SLICEM_X0.DLUT.INIT[19] 35_58
+CLBLM_R.SLICEM_X0.DLUT.INIT[20] 34_57
+CLBLM_R.SLICEM_X0.DLUT.INIT[21] 35_57
+CLBLM_R.SLICEM_X0.DLUT.INIT[22] 34_56
+CLBLM_R.SLICEM_X0.DLUT.INIT[23] 35_56
+CLBLM_R.SLICEM_X0.DLUT.INIT[24] 32_59
+CLBLM_R.SLICEM_X0.DLUT.INIT[25] 33_59
+CLBLM_R.SLICEM_X0.DLUT.INIT[26] 32_58
+CLBLM_R.SLICEM_X0.DLUT.INIT[27] 33_58
+CLBLM_R.SLICEM_X0.DLUT.INIT[28] 32_57
+CLBLM_R.SLICEM_X0.DLUT.INIT[29] 33_57
+CLBLM_R.SLICEM_X0.DLUT.INIT[30] 32_56
+CLBLM_R.SLICEM_X0.DLUT.INIT[31] 33_56
+CLBLM_R.SLICEM_X0.DLUT.INIT[32] 34_55
+CLBLM_R.SLICEM_X0.DLUT.INIT[33] 35_55
+CLBLM_R.SLICEM_X0.DLUT.INIT[34] 34_54
+CLBLM_R.SLICEM_X0.DLUT.INIT[35] 35_54
+CLBLM_R.SLICEM_X0.DLUT.INIT[36] 34_53
+CLBLM_R.SLICEM_X0.DLUT.INIT[37] 35_53
+CLBLM_R.SLICEM_X0.DLUT.INIT[38] 34_52
+CLBLM_R.SLICEM_X0.DLUT.INIT[39] 35_52
+CLBLM_R.SLICEM_X0.DLUT.INIT[40] 32_55
+CLBLM_R.SLICEM_X0.DLUT.INIT[41] 33_55
+CLBLM_R.SLICEM_X0.DLUT.INIT[42] 32_54
+CLBLM_R.SLICEM_X0.DLUT.INIT[43] 33_54
+CLBLM_R.SLICEM_X0.DLUT.INIT[44] 32_53
+CLBLM_R.SLICEM_X0.DLUT.INIT[45] 33_53
+CLBLM_R.SLICEM_X0.DLUT.INIT[46] 32_52
+CLBLM_R.SLICEM_X0.DLUT.INIT[47] 33_52
+CLBLM_R.SLICEM_X0.DLUT.INIT[48] 34_51
+CLBLM_R.SLICEM_X0.DLUT.INIT[49] 35_51
+CLBLM_R.SLICEM_X0.DLUT.INIT[50] 34_50
+CLBLM_R.SLICEM_X0.DLUT.INIT[51] 35_50
+CLBLM_R.SLICEM_X0.DLUT.INIT[52] 34_49
+CLBLM_R.SLICEM_X0.DLUT.INIT[53] 35_49
+CLBLM_R.SLICEM_X0.DLUT.INIT[54] 34_48
+CLBLM_R.SLICEM_X0.DLUT.INIT[55] 35_48
+CLBLM_R.SLICEM_X0.DLUT.INIT[56] 32_51
+CLBLM_R.SLICEM_X0.DLUT.INIT[57] 33_51
+CLBLM_R.SLICEM_X0.DLUT.INIT[58] 32_50
+CLBLM_R.SLICEM_X0.DLUT.INIT[59] 33_50
+CLBLM_R.SLICEM_X0.DLUT.INIT[60] 32_49
+CLBLM_R.SLICEM_X0.DLUT.INIT[61] 33_49
+CLBLM_R.SLICEM_X0.DLUT.INIT[62] 32_48
+CLBLM_R.SLICEM_X0.DLUT.INIT[63] 33_48
+CLBLM_R.SLICEM_X0.DLUT.RAM 31_47
+CLBLM_R.SLICEM_X0.DLUT.SMALL 01_59
+CLBLM_R.SLICEM_X0.DLUT.SRL 30_47
+CLBLM_R.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
+CLBLM_R.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
+CLBLM_R.SLICEM_X0.DOUTMUX.MC31 !30_51 30_52 !30_56 30_57
+CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
+CLBLM_R.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
+CLBLM_R.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
+CLBLM_R.SLICEM_X0.FFSYNC 00_48
+CLBLM_R.SLICEM_X0.LATCH 30_32
+CLBLM_R.SLICEM_X0.NOCLKINV !01_51
+CLBLM_R.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
+CLBLM_R.SLICEM_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
+CLBLM_R.SLICEM_X0.PRECYINIT.C1 00_12 !30_13 !30_14
+CLBLM_R.SLICEM_X0.PRECYINIT.C1 !30_13 !30_14 00_12
+CLBLM_R.SLICEM_X0.PRECYINIT.CIN !00_12 30_13 !30_14
+CLBLM_R.SLICEM_X0.PRECYINIT.CIN !00_12 !30_14 30_13
+CLBLM_R.SLICEM_X0.SRUSEDMUX 01_35
+CLBLM_R.SLICEM_X0.WA7USED 00_40
+CLBLM_R.SLICEM_X0.WA8USED 01_27
+CLBLM_R.SLICEM_X0.WEMUX.CE 01_23

database/virtex7/segbits_liob18.db

@@ -0,0 +1,75 @@
+LIOB18.DIFF.ZIBUF_LOW_PWR 38_124 39_03
+LIOB18.IOB_Y0.DCITERMDISABLE.I 39_65
+LIOB18.IOB_Y0.IBUFDISABLE.I 38_88
+LIOB18.IOB_Y0.IBUF_HP_BANK_GLUE 29_109
+LIOB18.IOB_Y0.LVCMOS12.DRIVE.I2_I4_I6_I8 !38_104 !38_86 !39_73 !39_83 !39_97 38_72 39_93 39_95
+LIOB18.IOB_Y0.LVCMOS12.SLEW.FAST !38_82 !39_101 !39_81 !39_89 38_114 39_105 39_111 39_113 39_77
+LIOB18.IOB_Y0.LVCMOS12_LVCMOS15.IN !39_01 38_126 39_127
+LIOB18.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN !39_01 38_126 39_127
+LIOB18.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.SLEW.SLOW !38_114 !38_82 !39_101 !39_105 !39_111 !39_113 !39_77 !39_81 !39_89
+LIOB18.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_104 !38_72 !38_86 !39_73 !39_83 !39_93 !39_95 !39_97 38_78 38_80 38_94 39_103 39_79
+LIOB18.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_114 !38_82 !39_101 !39_105 !39_111 !39_113 !39_77 !39_81 !39_89
+LIOB18.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN !00_127
+LIOB18.IOB_Y0.LVCMOS12_LVCMOS15_SSTL12_SSTL135_SSTL15.IN_ONLY !38_104 !38_72 !38_86 !39_73 !39_83 !39_93 !39_95 !39_97 38_78 38_80 38_94 39_103 39_79
+LIOB18.IOB_Y0.LVCMOS15.SLEW.FAST !38_114 !38_82 !39_101 !39_105 !39_111 !39_113 !39_77 !39_89 39_81
+LIOB18.IOB_Y0.LVCMOS15_LVCMOS18.DRIVE.I12_I16_I2_I4_I6_I8 !38_104 !38_72 !38_86 !39_73 !39_83 !39_97 39_93 39_95
+LIOB18.IOB_Y0.LVCMOS18.DRIVE.I12_I8 !38_104 !38_72 !38_86 !39_73 !39_83 !39_97 39_93 39_95
+LIOB18.IOB_Y0.LVCMOS18.SLEW.FAST !38_114 !39_101 !39_111 !39_77 38_82 39_105 39_113 39_81 39_89
+LIOB18.IOB_Y0.LVDS.DRIVE.I_FIXED !38_104 !38_72 !39_83 !39_97 38_24 38_48 38_86 39_33 39_47 39_49 39_73 39_93 39_95
+LIOB18.IOB_Y0.LVDS.IN_DIFF !38_126 !39_127 39_01
+LIOB18.IOB_Y0.LVDS.IN_ONLY !38_104 !38_72 !38_78 !38_80 !38_86 !38_94 !39_103 !39_73 !39_79 !39_83 !39_93 !39_95 !39_97 38_24 38_48 39_33 39_47 39_49
+LIOB18.IOB_Y0.LVDS.IN_USE !38_78 !38_80 !38_94 !39_79 38_24 38_48 39_33 39_47 39_49
+LIOB18.IOB_Y0.LVDS.OUT !38_104 !38_72 !38_82 !39_77 !39_81 !39_83 !39_97 38_86 39_73 39_93 39_95
+LIOB18.IOB_Y0.OBUF_HP_BANK_GLUE 31_086 32_066 33_111
+LIOB18.IOB_Y0.PULLTYPE.KEEPER !39_117 39_115 39_123
+LIOB18.IOB_Y0.PULLTYPE.NONE !39_117 !39_123 39_115
+LIOB18.IOB_Y0.PULLTYPE.PULLDOWN !39_115 !39_117 !39_123
+LIOB18.IOB_Y0.PULLTYPE.PULLUP !39_123 39_115 39_117
+LIOB18.IOB_Y0.SSTL12.DRIVE.I_FIXED !38_72 !38_86 !39_73 38_104 38_94 39_79 39_83 39_93 39_95 39_97
+LIOB18.IOB_Y0.SSTL12.IN_USE !38_78 !38_80 38_94 39_79
+LIOB18.IOB_Y0.SSTL12.SLEW.FAST !39_101 !39_77 38_114 38_82 39_105 39_111 39_113 39_81 39_89
+LIOB18.IOB_Y0.SSTL12_SSTL135.SLEW.SLOW !38_114 !39_101 !39_105 !39_111 !39_113 !39_89 38_82 39_77 39_81
+LIOB18.IOB_Y0.SSTL12_SSTL135_SSTL15.IN !38_126 39_127
+LIOB18.IOB_Y0.SSTL12_SSTL135_SSTL15.IN_DIFF !39_127 38_126 39_01
+LIOB18.IOB_Y0.SSTL135.DRIVE.I_FIXED !38_72 !38_86 !39_73 !39_83 38_104 38_78 38_94 39_93 39_95 39_97
+LIOB18.IOB_Y0.SSTL135.IN_USE !38_80 !39_79 38_78 38_94
+LIOB18.IOB_Y0.SSTL135.SLEW.FAST !39_77 38_114 38_82 39_101 39_105 39_111 39_113 39_81 39_89
+LIOB18.IOB_Y0.SSTL15.DRIVE.I_FIXED !38_104 !38_86 !39_73 38_72 38_78 38_80 39_79 39_83 39_93 39_95 39_97
+LIOB18.IOB_Y0.SSTL15.IN_USE !38_94 38_78 38_80 39_79
+LIOB18.IOB_Y0.SSTL15.SLEW.FAST !39_81 !39_89 38_114 38_82 39_101 39_105 39_111 39_113 39_77
+LIOB18.IOB_Y0.SSTL15.SLEW.SLOW !38_114 !39_101 !39_105 !39_111 !39_113 38_82 39_77 39_81 39_89
+LIOB18.IOB_Y0.ZIBUF_LOW_PWR 39_125
+LIOB18.IOB_Y1.DCITERMDISABLE.I 38_62
+LIOB18.IOB_Y1.IBUFDISABLE.I 39_39
+LIOB18.IOB_Y1.LVCMOS12.DRIVE.I2_I4_I6_I8 !38_30 !38_44 !39_23 38_32 38_34 39_55
+LIOB18.IOB_Y1.LVCMOS12.SLEW.FAST !38_26 !38_38 !38_46 !39_45 38_14 38_16 38_22 38_50 39_13
+LIOB18.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN 38_00 39_01
+LIOB18.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.SLEW.SLOW !38_14 !38_16 !38_22 !38_26 !38_38 !38_46 !38_50 !39_13 !39_45
+LIOB18.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL12_SSTL135_SSTL15.IN_ONLY !38_30 !38_44 !39_23 !39_55 38_24 38_48 39_33 39_47 39_49
+LIOB18.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN !00_127
+LIOB18.IOB_Y1.LVCMOS15.SLEW.FAST !38_14 !38_16 !38_22 !38_26 !38_38 !38_50 !39_13 !39_45 38_46
+LIOB18.IOB_Y1.LVCMOS15_LVCMOS18.DRIVE.I12_I16_I2_I4_I6_I8 !38_30 !38_44 !39_23 !39_55 38_32 38_34
+LIOB18.IOB_Y1.LVCMOS18.SLEW.FAST !38_16 !38_26 !38_50 !39_13 38_14 38_22 38_38 38_46 39_45
+LIOB18.IOB_Y1.OBUF_HP_BANK_GLUE 30_041 32_016 33_061
+LIOB18.IOB_Y1.PULLTYPE.KEEPER !38_10 38_04 38_12
+LIOB18.IOB_Y1.PULLTYPE.NONE !38_04 !38_10 38_12
+LIOB18.IOB_Y1.PULLTYPE.PULLDOWN !38_04 !38_10 !38_12
+LIOB18.IOB_Y1.PULLTYPE.PULLUP !38_04 38_10 38_12
+LIOB18.IOB_Y1.SSTL12.DRIVE.I_FIXED !39_55 38_30 38_32 38_34 38_44 38_48 39_23 39_33
+LIOB18.IOB_Y1.SSTL12.IN_USE !39_47 !39_49 38_48 39_33
+LIOB18.IOB_Y1.SSTL12.SLEW.FAST !38_26 !38_50 38_14 38_16 38_22 38_38 38_46 39_13 39_45
+LIOB18.IOB_Y1.SSTL12_SSTL135.SLEW.SLOW !38_14 !38_16 !38_22 !38_26 !38_38 !39_13 38_46 38_50 39_45
+LIOB18.IOB_Y1.SSTL12_SSTL135_SSTL15.IN !38_126 !39_01 38_00
+LIOB18.IOB_Y1.SSTL12_SSTL135_SSTL15.IN_DIFF 38_00 38_126 39_01
+LIOB18.IOB_Y1.SSTL135.DRIVE.I_FIXED !38_44 !39_55 38_30 38_32 38_34 39_23 39_33 39_49
+LIOB18.IOB_Y1.SSTL135.IN_USE !38_48 !39_47 39_33 39_49
+LIOB18.IOB_Y1.SSTL135.SLEW.FAST !38_50 38_14 38_16 38_22 38_26 38_38 38_46 39_13 39_45
+LIOB18.IOB_Y1.SSTL15.DRIVE.I_FIXED !39_23 38_30 38_32 38_34 38_44 38_48 39_47 39_49 39_55
+LIOB18.IOB_Y1.SSTL15.IN_USE !39_33 38_48 39_47 39_49
+LIOB18.IOB_Y1.SSTL15.SLEW.FAST !38_38 !38_46 38_14 38_16 38_22 38_26 38_50 39_13 39_45
+LIOB18.IOB_Y1.SSTL15.SLEW.SLOW !38_14 !38_16 !38_22 !38_26 !39_13 38_38 38_46 38_50 39_45
+LIOB18.IOB_Y1.ZIBUF_LOW_PWR 38_02
+LIOB18.OUT_DIFF 39_17 39_43
+LIOB18.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_30 !38_44 !39_23 !39_55 38_24 38_48 39_33 39_47 39_49
+LIOB18.IOB_Y1.LVCMOS18.DRIVE.I12_I8 !38_30 !38_44 !39_23 !39_55 38_32 38_34
+LIOB18.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_14 !38_16 !38_22 !38_26 !38_38 !38_46 !38_50 !39_13 !39_45

database/virtex7/segbits_riob18.db

@@ -0,0 +1,68 @@
+RIOB18.DIFF.ZIBUF_LOW_PWR 38_124 39_03
+RIOB18.IOB_Y0.DCITERMDISABLE.I 39_65
+RIOB18.IOB_Y0.IBUFDISABLE.I 38_88
+RIOB18.IOB_Y0.IBUFDS_BANK_GLUE 38_008 38_028 38_040 39_015 39_021 39_037 39_041
+RIOB18.IOB_Y0.LVCMOS12.DRIVE.I2_I4_I6_I8 !38_104 !38_86 !39_73 !39_83 !39_97 38_72 39_93 39_95
+RIOB18.IOB_Y0.LVCMOS12.SLEW.FAST !38_82 !39_101 !39_81 !39_89 38_114 39_105 39_111 39_113 39_77
+RIOB18.IOB_Y0.LVCMOS12_LVCMOS15.IN !39_01 38_126 39_127
+RIOB18.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN 38_126 39_127
+RIOB18.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.SLEW.SLOW !38_114 !38_82 !39_101 !39_105 !39_111 !39_113 !39_77 !39_81 !39_89
+RIOB18.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL12_SSTL135_SSTL15.IN_ONLY !38_104 !38_72 !38_86 !39_73 !39_83 !39_93 !39_95 !39_97 38_78 38_80 38_94 39_103 39_79
+RIOB18.IOB_Y0.LVCMOS12_LVCMOS15_SSTL12_SSTL135_SSTL15.IN_ONLY !38_104 !38_72 !38_86 !39_73 !39_83 !39_93 !39_95 !39_97 38_78 38_80 38_94 39_103 39_79
+RIOB18.IOB_Y0.LVCMOS15.SLEW.FAST !38_114 !38_82 !39_101 !39_105 !39_111 !39_113 !39_77 !39_89 39_81
+RIOB18.IOB_Y0.LVCMOS15_LVCMOS18.DRIVE.I12_I16_I2_I4_I6_I8 !38_104 !38_72 !38_86 !39_73 !39_83 !39_97 39_93 39_95
+RIOB18.IOB_Y0.LVCMOS18.SLEW.FAST !38_114 !39_101 !39_111 !39_77 38_82 39_105 39_113 39_81 39_89
+RIOB18.IOB_Y0.LVDS.DRIVE.I_FIXED !38_104 !38_72 !39_83 !39_97 38_24 38_48 38_86 39_33 39_47 39_49 39_73 39_93 39_95
+RIOB18.IOB_Y0.LVDS.IN_DIFF !38_126 !39_127 39_01
+RIOB18.IOB_Y0.LVDS.IN_ONLY !38_104 !38_72 !38_78 !38_80 !38_86 !38_94 !39_103 !39_73 !39_79 !39_83 !39_93 !39_95 !39_97 38_24 38_48 39_33 39_47 39_49
+RIOB18.IOB_Y0.LVDS.IN_USE !38_78 !38_80 !38_94 !39_79 38_24 38_48 39_33 39_47 39_49
+RIOB18.IOB_Y0.LVDS.OUT !38_104 !38_72 !38_82 !39_77 !39_81 !39_83 !39_97 38_86 39_73 39_93 39_95
+RIOB18.IOB_Y0.LVDS_SSTL12_SSTL135_SSTL15.IN_DIFF !39_127 38_126 39_01
+RIOB18.IOB_Y0.PULLTYPE.KEEPER !39_117 39_115 39_123
+RIOB18.IOB_Y0.PULLTYPE.NONE !39_117 !39_123 39_115
+RIOB18.IOB_Y0.PULLTYPE.PULLDOWN !39_115 !39_117 !39_123
+RIOB18.IOB_Y0.PULLTYPE.PULLUP !39_123 39_115 39_117
+RIOB18.IOB_Y0.SSTL12.DRIVE.I_FIXED !38_72 !38_86 !39_73 38_104 38_94 39_79 39_83 39_93 39_95 39_97
+RIOB18.IOB_Y0.SSTL12.IN_USE !38_78 !38_80 38_94 39_79
+RIOB18.IOB_Y0.SSTL12.SLEW.FAST !39_101 !39_77 38_114 38_82 39_105 39_111 39_113 39_81 39_89
+RIOB18.IOB_Y0.SSTL12_SSTL135.SLEW.SLOW !38_114 !39_101 !39_105 !39_111 !39_113 !39_89 38_82 39_77 39_81
+RIOB18.IOB_Y0.SSTL12_SSTL135_SSTL15.IN !38_126 39_127
+RIOB18.IOB_Y0.SSTL12_SSTL135_SSTL15.IN_DIFF !39_127 38_126 39_01
+RIOB18.IOB_Y0.SSTL135.DRIVE.I_FIXED !38_72 !38_86 !39_73 !39_83 38_104 38_78 38_94 39_93 39_95 39_97
+RIOB18.IOB_Y0.SSTL135.IN_USE !38_80 !39_79 38_78 38_94
+RIOB18.IOB_Y0.SSTL135.SLEW.FAST !39_77 38_114 38_82 39_101 39_105 39_111 39_113 39_81 39_89
+RIOB18.IOB_Y0.SSTL15.DRIVE.I_FIXED !38_104 !38_86 !39_73 38_72 38_78 38_80 39_79 39_83 39_93 39_95 39_97
+RIOB18.IOB_Y0.SSTL15.IN_USE !38_94 38_78 38_80 39_79
+RIOB18.IOB_Y0.SSTL15.SLEW.FAST !39_81 !39_89 38_114 38_82 39_101 39_105 39_111 39_113 39_77
+RIOB18.IOB_Y0.SSTL15.SLEW.SLOW !38_114 !39_101 !39_105 !39_111 !39_113 38_82 39_77 39_81 39_89
+RIOB18.IOB_Y0.ZIBUF_LOW_PWR 39_125
+RIOB18.IOB_Y1.DCITERMDISABLE.I 38_62
+RIOB18.IOB_Y1.IBUFDISABLE.I 39_39
+RIOB18.IOB_Y1.LVCMOS12.DRIVE.I2_I4_I6_I8 !38_30 !38_44 !39_23 38_32 38_34 39_55
+RIOB18.IOB_Y1.LVCMOS12.SLEW.FAST !38_26 !38_38 !38_46 !39_45 38_14 38_16 38_22 38_50 39_13
+RIOB18.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN 38_00 39_01
+RIOB18.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.SLEW.SLOW !38_14 !38_16 !38_22 !38_26 !38_38 !38_46 !38_50 !39_13 !39_45
+RIOB18.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL12_SSTL135_SSTL15.IN_ONLY !38_30 !38_44 !39_23 !39_55 38_24 38_48 39_33 39_47 39_49
+RIOB18.IOB_Y1.LVCMOS15.SLEW.FAST !38_14 !38_16 !38_22 !38_26 !38_38 !38_50 !39_13 !39_45 38_46
+RIOB18.IOB_Y1.LVCMOS15_LVCMOS18.DRIVE.I12_I16_I2_I4_I6_I8 !38_30 !38_44 !39_23 !39_55 38_32 38_34
+RIOB18.IOB_Y1.LVCMOS18.SLEW.FAST !38_16 !38_26 !38_50 !39_13 38_14 38_22 38_38 38_46 39_45
+RIOB18.IOB_Y1.LVDS_SSTL12_SSTL135_SSTL15.IN_DIFF 38_00 38_126 39_01
+RIOB18.IOB_Y1.PULLTYPE.KEEPER !38_10 38_04 38_12
+RIOB18.IOB_Y1.PULLTYPE.NONE !38_04 !38_10 38_12
+RIOB18.IOB_Y1.PULLTYPE.PULLDOWN !38_04 !38_10 !38_12
+RIOB18.IOB_Y1.PULLTYPE.PULLUP !38_04 38_10 38_12
+RIOB18.IOB_Y1.SSTL12.DRIVE.I_FIXED !39_55 38_30 38_32 38_34 38_44 38_48 39_23 39_33
+RIOB18.IOB_Y1.SSTL12.IN_USE !39_47 !39_49 38_48 39_33
+RIOB18.IOB_Y1.SSTL12.SLEW.FAST !38_26 !38_50 38_14 38_16 38_22 38_38 38_46 39_13 39_45
+RIOB18.IOB_Y1.SSTL12_SSTL135.SLEW.SLOW !38_14 !38_16 !38_22 !38_26 !38_38 !39_13 38_46 38_50 39_45
+RIOB18.IOB_Y1.SSTL12_SSTL135_SSTL15.IN !38_126 !39_01 38_00
+RIOB18.IOB_Y1.SSTL12_SSTL135_SSTL15.IN_DIFF 38_00 38_126 39_01
+RIOB18.IOB_Y1.SSTL135.DRIVE.I_FIXED !38_44 !39_55 38_30 38_32 38_34 39_23 39_33 39_49
+RIOB18.IOB_Y1.SSTL135.IN_USE !38_48 !39_47 39_33 39_49
+RIOB18.IOB_Y1.SSTL135.SLEW.FAST !38_50 38_14 38_16 38_22 38_26 38_38 38_46 39_13 39_45
+RIOB18.IOB_Y1.SSTL15.DRIVE.I_FIXED !39_23 38_30 38_32 38_34 38_44 38_48 39_47 39_49 39_55
+RIOB18.IOB_Y1.SSTL15.IN_USE !39_33 38_48 39_47 39_49
+RIOB18.IOB_Y1.SSTL15.SLEW.FAST !38_38 !38_46 38_14 38_16 38_22 38_26 38_50 39_13 39_45
+RIOB18.IOB_Y1.SSTL15.SLEW.SLOW !38_14 !38_16 !38_22 !38_26 !39_13 38_38 38_46 38_50 39_45
+RIOB18.IOB_Y1.ZIBUF_LOW_PWR 38_02
+RIOB18.OUT_DIFF 39_17 39_43

fuzzers/001-part-yaml/generate.tcl

@@ -29,10 +29,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog ../../top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
 
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]

fuzzers/005-tilegrid/Makefile

@@ -6,13 +6,33 @@
 #
 # SPDX-License-Identifier: ISC
 
+# I/O bank types present on the target device. Most 7-series parts have
+# high-range (HR) banks; Virtex-7 "VX" parts are high-performance (HP) only.
+HAS_HIGH_RANGE_BANKS ?= 1
+HAS_HIGH_PERFORMANCE_BANKS ?= 0
+
+ifeq (${XRAY_DATABASE}, virtex7)
+HAS_HIGH_PERFORMANCE_BANKS = 1
+# TODO: some virtex devices also have high range banks
+HAS_HIGH_RANGE_BANKS = 0
+endif
+ifeq (${XRAY_DATABASE}, kintex7)
+# xc7k420t/xc7k480t have no high performance banks
+ifneq (${XRAY_FABRIC}, $(filter ${XRAY_FABRIC}, xc7k480t))
+HAS_HIGH_PERFORMANCE_BANKS = 1
+endif
+endif
+
 FUZDIR=$(shell pwd)
 BUILD_FOLDER=build_${XRAY_PART}
 BUILD_DIR=$(FUZDIR)/$(BUILD_FOLDER)
 TILEGRID_TDB_DEPENDENCIES=
+# High-range (HR) bank I/O tiles
+ifeq (${HAS_HIGH_RANGE_BANKS}, 1)
 TILEGRID_TDB_DEPENDENCIES += iob/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += iob_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += ioi/$(BUILD_FOLDER)/segbits_tilegrid.tdb
+endif
 TILEGRID_TDB_DEPENDENCIES += monitor/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += bram/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += bram_block/$(BUILD_FOLDER)/segbits_tilegrid.tdb
@@ -57,19 +77,30 @@ TILEGRID_TDB_DEPENDENCIES += ioi18/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 endif
 endif
 
-# Kintex7 only fuzzers
+# High-performance (HP) bank I/O fuzzers.
-ifeq (${XRAY_DATABASE}, kintex7)
+# Present on Kintex-7 (except xc7k480t) and Virtex-7 VX parts.
-# xc7k420t/xc7k480t have no high performance banks
+ifeq (${HAS_HIGH_PERFORMANCE_BANKS}, 1)
-ifneq (${XRAY_FABRIC}, $(filter ${XRAY_FABRIC}, xc7k480t))
 TILEGRID_TDB_DEPENDENCIES += iob18/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += iob18_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb
+# iob18_sing is intentionally NOT a tilegrid dependency: SING tiles inherit
+# their base address from the parent IOB18 column via propagate_IOB_SING in
+# generate_full.py, not via direct measurement. The iob18_sing rule below is
+# kept so the build can still be invoked manually as a Vivado-measurement
+# guard (its tdb half-aligns at offset+1 - exactly what propagate_IOB_SING's
+# top-tile alias models with offset=99).
 TILEGRID_TDB_DEPENDENCIES += ioi18/$(BUILD_FOLDER)/segbits_tilegrid.tdb
+# GTX transceiver fuzzers. Kintex-7 only: the xc7vx485t-ffg1761 package used for
+# virtex7 bonds only ~7 of its 14 GTX quads, so the unbonded GTX_COMMON tiles
+# cannot be placed/fuzzed. GTX is therefore skipped for virtex7.
+ifneq (${XRAY_DATABASE}, virtex7)
 TILEGRID_TDB_DEPENDENCIES += gtx_common/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += gtx_channel/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += gtx_int_interface/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 endif
+endif
 
 # These kintex parts give an empty design
+ifeq (${XRAY_DATABASE}, kintex7)
 ifneq (${XRAY_FABRIC}, $(filter ${XRAY_FABRIC}, xc7k160t xc7k325t xc7k480t))
 TILEGRID_TDB_DEPENDENCIES += orphan_int_column/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 endif
@@ -116,6 +147,9 @@ iob_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
 iob18_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
 	cd iob18_int && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG})
 
+iob18_sing/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
+	cd iob18_sing && $(MAKE)
+
 ioi/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
 	cd ioi && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG})
 
@@ -221,6 +255,7 @@ clean:
 	cd iob18 && $(MAKE) clean
 	cd iob_int && $(MAKE) clean
 	cd iob18_int && $(MAKE) clean
+	cd iob18_sing && $(MAKE) clean
 	cd ioi && $(MAKE) clean
 	cd ioi18 && $(MAKE) clean
 	cd mmcm && $(MAKE) clean
@@ -259,6 +294,7 @@ clean_part:
 	cd iob18 && $(MAKE) clean_part
 	cd iob_int && $(MAKE) clean_part
 	cd iob18_int && $(MAKE) clean_part
+	cd iob18_sing && $(MAKE) clean_part
 	cd ioi && $(MAKE) clean_part
 	cd ioi18 && $(MAKE) clean_part
 	cd mmcm && $(MAKE) clean_part

fuzzers/005-tilegrid/add_tdb.py

@@ -47,7 +47,17 @@ def load_db(fn):
         parts = l.split(' ')
         tagstr = parts[0]
         addrlist = parts[1:]
-        assert not any(s == '<const0>' for s in addrlist), (fn, l)
+        # segmatch emits a "<...>" marker (e.g. "<const0>", "<const1>",
+        # "<0 candidates>") instead of a frame address when it could not solve a
+        # tag's bit, i.e. the tile was not exercised/uniquely toggled by the
+        # design (e.g. unplaceable edge/special tiles such as BRAM_L_X114Y0 or
+        # CFG_CENTER_MID_X157Y84 on xc7vx485t-ffg1761). Such tiles can't have a
+        # base address solved here, so skip them with a warning rather than
+        # aborting the whole tilegrid aggregation.
+        if not addrlist or any(s.startswith('<') for s in addrlist):
+            print("WARNING: skipping unsolved tile (no address): "
+                  "%s in %s" % (l, fn))
+            continue
         check_frames(tagstr, addrlist)
         # Take the first address in the list
         frame, wordidx, bitidx = parse_addr(addrlist[0])
@@ -79,7 +89,8 @@ def load_db(fn):
         if not bitidx_up:
             bitidx = 0
         assert bitidx == 0, l
-        assert frame % 0x80 == 0, "Unaligned frame at 0x%08X" % frame
+        assert frame % 0x80 == 0, \
+            "Unaligned frame at 0x%08X in %s: %s" % (frame, fn, l)
         yield (tile, frame, wordidx)
 
 

fuzzers/005-tilegrid/bram/generate.tcl

@@ -12,10 +12,10 @@ proc run {} {
     read_verilog top.v
     synth_design -top top
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
     set_property CFGBVS VCCO [current_design]
     set_property CONFIG_VOLTAGE 3.3 [current_design]

fuzzers/005-tilegrid/cfg/generate.tcl

@@ -6,4 +6,9 @@
 #
 # SPDX-License-Identifier: ISC
 source "$::env(XRAY_DIR)/utils/utils.tcl"
+# The cfg fuzzer sweeps BSCANE2 JTAG_CHAIN values to locate config bits; some
+# values fail DRC PDRC-2 (BSCAN site vs JTAG_CHAIN mismatch) under newer Vivado,
+# which aborts write_bitstream. We only need the resulting config bits, not a
+# JTAG-valid design, so disable that DRC check for this fuzzer.
+set_property IS_ENABLED 0 [get_drc_checks {PDRC-2}]
 generate_top

fuzzers/005-tilegrid/clb/generate.tcl

@@ -12,10 +12,10 @@ proc run {} {
     read_verilog top.v
     synth_design -top top
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
     set_property CFGBVS VCCO [current_design]
     set_property CONFIG_VOLTAGE 3.3 [current_design]

fuzzers/005-tilegrid/clb_int/generate.tcl

@@ -12,8 +12,8 @@ proc run {} {
     read_verilog top.v
     synth_design -top top
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
     set_property CFGBVS VCCO [current_design]
     set_property CONFIG_VOLTAGE 3.3 [current_design]

fuzzers/005-tilegrid/fuzzaddr/common.mk

@@ -9,7 +9,13 @@ database: $(BUILD_DIR)/segbits_tilegrid.tdb
 $(BUILD_DIR)/segbits_tilegrid.tdb: $(SPECIMENS_OK)
 	${XRAY_SEGMATCH} -o $(BUILD_DIR)/segbits_tilegrid.tdb $$(find $(BUILD_DIR) -name "segdata_tilegrid.txt")
 
+# Retry a specimen up to 3 times: Vivado's FlexLM license manager can crash
+# (SIGSEGV in libXil_lmgr11/freeaddrinfo) under concurrent license checkouts.
+# Such crashes are transient and unrelated to the design, so retry before giving
+# up. The success path is unchanged (first attempt short-circuits the chain).
 $(SPECIMENS_OK):
+	GENERATE_ARGS=${GENERATE_ARGS} bash ../fuzzaddr/generate.sh $(subst /OK,,$@) || \
+	GENERATE_ARGS=${GENERATE_ARGS} bash ../fuzzaddr/generate.sh $(subst /OK,,$@) || \
 	GENERATE_ARGS=${GENERATE_ARGS} bash ../fuzzaddr/generate.sh $(subst /OK,,$@)
 	touch $@
 

fuzzers/005-tilegrid/generate_full.py

@@ -369,7 +369,8 @@ def propagate_IOB_SING(database, tiles_by_grid):
         if tile in seen_iobs:
             continue
 
-        if database[tile]["type"] not in ["LIOB33", "RIOB33", "RIOB18"]:
+        if database[tile]["type"] not in ["LIOB33", "RIOB33", "LIOB18",
+                                          "RIOB18"]:
             continue
 
         while True:
@@ -405,9 +406,16 @@ def propagate_IOB_SING(database, tiles_by_grid):
         database[top_tile]['bits']['CLB_IO_CLK'] = copy.deepcopy(bits)
         database[top_tile]['bits']['CLB_IO_CLK']['words'] = 2
         database[top_tile]['bits']['CLB_IO_CLK']['offset'] = 99
+        # start_offset 2 (not 0): the top SING tile only has frame words 99-100,
+        # and nextpnr-xilinx places the IOB features that live in the full
+        # tile's *upper* words (2-3) here.  With start_offset 0 those map to
+        # absolute words 101-102, which don't exist -> fasm2frames "invalid
+        # word address" and the features are silently dropped.  start_offset 2
+        # gives effective offset 97 so words 2-3 land at abs 99-100.  HW-verified
+        # (VC707 open-flow UART DSP calculator computes correctly).
         database[top_tile]['bits']['CLB_IO_CLK']['alias'] = {
             'type': database[prev_tile]['type'],
-            'start_offset': 0,
+            'start_offset': 2,
             'sites': {
                 'IOB33_Y0': 'IOB33_Y1',
             }
@@ -439,7 +447,7 @@ def propagate_IOI_SING(database, tiles_by_grid):
         if tile in seen_iois:
             continue
 
-        if database[tile]["type"] not in ["LIOI3", "RIOI3", "RIOI"]:
+        if database[tile]["type"] not in ["LIOI3", "RIOI3", "LIOI", "RIOI"]:
             continue
 
         while True:
@@ -480,9 +488,15 @@ def propagate_IOI_SING(database, tiles_by_grid):
         database[top_tile]['bits']['CLB_IO_CLK'] = copy.deepcopy(bits)
         database[top_tile]['bits']['CLB_IO_CLK']['words'] = 2
         database[top_tile]['bits']['CLB_IO_CLK']['offset'] = 99
+        # start_offset 2 (not 0): see propagate_IOB_SING.  The top SING IOI tile
+        # has only frame words 99-100; nextpnr-xilinx targets the full tile's
+        # upper OLOGIC/ILOGIC words (2-3) here, which under start_offset 0 map to
+        # absolute words 101-102 (don't exist) and get dropped by fasm2frames.
+        # start_offset 2 -> effective offset 97 -> words 2-3 at abs 99-100.
+        # HW-verified via the open-flow calculator (OLOGIC_Y0.OMUX.D1 @ abs 100).
         database[top_tile]['bits']['CLB_IO_CLK']['alias'] = {
             'type': database[prev_tile]['type'],
-            'start_offset': 0,
+            'start_offset': 2,
             'sites': {}
         }
 

fuzzers/005-tilegrid/gtx_channel/top.py

@@ -24,6 +24,18 @@ def gen_sites():
 
         for site_name, site_type in gridinfo.sites.items():
             if site_type in ['GTXE2_CHANNEL']:
+                # XRAY_GTX_SITES restricts the fuzz to a comma-separated list of
+                # site names.  Needed on virtex7: the xc7vx485t-ffg1761 package
+                # bonds only about half its GTX quads, and an UNBONDED quad
+                # cannot be placed, so fuzzing every site fails the whole run --
+                # which is why 005-tilegrid skips GTX for virtex7 entirely.
+                # Restricting to a bonded quad measures the tiles that a real
+                # design actually uses (this board's SGMII sits on
+                # GTXE2_CHANNEL_X1Y* / GTXE2_COMMON_X1Y0) and leaves the
+                # unbonded ones legitimately unmeasured.
+                want = os.getenv("XRAY_GTX_SITES")
+                if want and site_name not in want.split(','):
+                    continue
                 yield tile_name, site_name
 
 

fuzzers/005-tilegrid/gtx_common/top.py

@@ -24,6 +24,18 @@ def gen_sites():
 
         for site_name, site_type in gridinfo.sites.items():
             if site_type in ['GTXE2_COMMON']:
+                # XRAY_GTX_SITES restricts the fuzz to a comma-separated list of
+                # site names.  Needed on virtex7: the xc7vx485t-ffg1761 package
+                # bonds only about half its GTX quads, and an UNBONDED quad
+                # cannot be placed, so fuzzing every site fails the whole run --
+                # which is why 005-tilegrid skips GTX for virtex7 entirely.
+                # Restricting to a bonded quad measures the tiles that a real
+                # design actually uses (this board's SGMII sits on
+                # GTXE2_CHANNEL_X1Y* / GTXE2_COMMON_X1Y0) and leaves the
+                # unbonded ones legitimately unmeasured.
+                want = os.getenv("XRAY_GTX_SITES")
+                if want and site_name not in want.split(','):
+                    continue
                 yield tile_name, site_name
 
 

fuzzers/005-tilegrid/iob18_int/top.py

@@ -49,12 +49,15 @@ def gen_sites():
 
         sites, _ = zip(*sorted(zip(sites, sites_y), key=lambda x: x[1]))
 
+        # IOI/IDELAY-to-INT column spacing is 3 on Kintex-7 but 2 on Virtex-7
+        # (verified from the tilegrid for all LIOI/RIOI variants).
+        int_dx = 2 if os.environ.get('XRAY_DATABASE') == 'virtex7' else 3
         if gridinfo.tile_type[0] == 'L':
-            int_grid_x = loc.grid_x + 3
+            int_grid_x = loc.grid_x + int_dx
             pad_grid_x = loc.grid_x - 1
             int_tile_type = 'INT_L'
         else:
-            int_grid_x = loc.grid_x - 3
+            int_grid_x = loc.grid_x - int_dx
             pad_grid_x = loc.grid_x + 1
             int_tile_type = 'INT_R'
 

fuzzers/005-tilegrid/iob18_sing/Makefile

@@ -0,0 +1,10 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+N ?= 14
+GENERATE_ARGS?="--oneval 1 --design params.csv --dframe 26 --dword 0"
+include ../fuzzaddr/common.mk

fuzzers/005-tilegrid/iob18_sing/generate.tcl

@@ -0,0 +1,86 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+source "$::env(XRAY_DIR)/utils/utils.tcl"
+
+proc make_io_pin_sites {} {
+    # get all possible IOB pins
+    foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] {
+        set site [get_sites -of_objects $pad]
+        if {[llength $site] == 0} {
+            continue
+        }
+        if [string match IOB18* [get_property SITE_TYPE $site]] {
+            dict append io_pin_sites $site $pad
+        }
+    }
+    return $io_pin_sites
+}
+
+proc load_pin_lines {} {
+    # IOB_X0Y103 clk input
+    # IOB_X0Y129 do[0] output
+
+    set fp [open "params.csv" r]
+    gets $fp line
+
+    set pin_lines {}
+    for {gets $fp line} {$line != ""} {gets $fp line} {
+        lappend pin_lines [split $line ","]
+    }
+    close $fp
+    return $pin_lines
+}
+
+proc loc_pins {} {
+    set pin_lines [load_pin_lines]
+    set io_pin_sites [make_io_pin_sites]
+
+    puts "Looping"
+    for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} {
+        set line [lindex $pin_lines $idx]
+        puts "$line"
+
+        set site_str [lindex $line 2]
+        set pin_str [lindex $line 3]
+
+        # Have: site
+        # Want: pin for site
+
+        set site [get_sites $site_str]
+        set pad_bel [get_bels -of_objects $site -filter {TYPE =~ PAD && NAME =~ IOB_*}]
+        # set port [get_ports -of_objects $site]
+        set port [get_ports $pin_str]
+        set tile [get_tiles -of_objects $site]
+
+        set pin [dict get $io_pin_sites $site]
+        set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS18" $port
+    }
+}
+
+proc run {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    loc_pins
+
+    set_property CFGBVS GND [current_design]
+    set_property CONFIG_VOLTAGE 1.8 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-79}]
+    set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
+    set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+}
+
+run

fuzzers/005-tilegrid/iob18_sing/top.py

@@ -0,0 +1,91 @@
+#!/usr/bin/env python3
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+#
+# 005-tilegrid sub-fuzzer for SING-row IOB18 tiles.  The existing
+# iob18 sub-fuzzer filters to `IOB18S` (the main IOB of a diff pair)
+# and ioi18 explicitly skips `_SING` tile types, so the SING-row
+# IOB18 sites (one per LIOB18_SING / RIOB18_SING tile) never get
+# their tilegrid frame addresses resolved by the existing fuzzers.
+# This sub-fuzzer addresses that gap (task #17): place an IBUF on
+# every SING-row IOB18 site, then bit-diff produces a tdb that
+# add_tdb.py merges into tilegrid.json.
+import os
+import random
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray.db import Database
+
+
+def gen_sites():
+    '''SING-row IOB18 singleton sites: tile_type ends in _SING, site
+    type is plain IOB18 (no S/M suffix, no diff-pair partner).'''
+    db = Database(util.get_db_root(), util.get_part())
+    grid = db.grid()
+    for tile_name in sorted(grid.tiles()):
+        loc = grid.loc_of_tilename(tile_name)
+        gridinfo = grid.gridinfo_at_loc(loc)
+
+        if not gridinfo.tile_type.endswith("_SING"):
+            continue
+        # Skip non-IOB SING tiles (LIOI_SING etc.); only LIOB18_SING
+        # / RIOB18_SING expose an IOB18 site.
+        for site_name, site_type in gridinfo.sites.items():
+            if site_type == 'IOB18':
+                yield tile_name, site_name
+
+
+def write_params(params):
+    pinstr = 'tile,val,site,pin\n'
+    for tile, (site, val, pin) in sorted(params.items()):
+        pinstr += '%s,%s,%s,%s\n' % (tile, val, site, pin)
+    open('params.csv', 'w').write(pinstr)
+
+
+def run():
+    sites = list(gen_sites())
+    print(
+        '''
+`define N_DI {}
+
+module top(input wire [`N_DI-1:0] di);
+    wire [`N_DI-1:0] di_buf;
+    '''.format(len(sites)))
+
+    params = {}
+    print('''
+        (* KEEP, DONT_TOUCH *)
+        LUT6 dummy_lut();''')
+
+    for idx, ((tile_name, site_name), isone) in enumerate(zip(
+            sites, util.gen_fuzz_states(len(sites)))):
+        params[tile_name] = (site_name, isone, "di[%u]" % idx)
+        print(
+            '''
+    (* KEEP, DONT_TOUCH *)
+    IBUF #(
+    ) ibuf_{site_name} (
+        .I(di[{idx}]),
+        .O(di_buf[{idx}])
+        );'''.format(site_name=site_name, idx=idx))
+
+        if isone:
+            print(
+                '''
+    (* KEEP, DONT_TOUCH *)
+    PULLUP #(
+    ) pullup_{site_name} (
+        .O(di[{idx}])
+        );'''.format(site_name=site_name, idx=idx))
+
+    print("endmodule")
+    write_params(params)
+
+
+if __name__ == '__main__':
+    run()

fuzzers/005-tilegrid/ioi18/Makefile

@@ -6,5 +6,13 @@
 #
 # SPDX-License-Identifier: ISC
 N ?= 24
+# On Virtex-7 a few IOI18 tiles (e.g. LIOI_X82Y10, RIOI_X311Y10) place the
+# toggled bit one frame above the Kintex-7 offset, so a fixed DFRAME mis-aligns
+# their base address. Use AUTO_FRAME (round the base down to the 0x80 boundary)
+# for virtex7 instead; it is equivalent to DFRAME:20 for the aligned tiles.
+ifeq ($(XRAY_DATABASE),virtex7)
+GENERATE_ARGS?="--oneval 1 --design params.csv --auto-frame --dword 3"
+else
 GENERATE_ARGS?="--oneval 1 --design params.csv --dframe 20 --dword 3"
+endif
 include ../fuzzaddr/common.mk

fuzzers/005-tilegrid/mmcm/generate.tcl

@@ -12,10 +12,10 @@ proc run {} {
     read_verilog top.v
     synth_design -top top
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
     set_property CFGBVS VCCO [current_design]
     set_property CONFIG_VOLTAGE 3.3 [current_design]

fuzzers/005-tilegrid/monitor/generate.tcl

@@ -12,10 +12,10 @@ proc run {} {
     read_verilog top.v
     synth_design -top top
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
     set_property CFGBVS VCCO [current_design]
     set_property CONFIG_VOLTAGE 3.3 [current_design]

fuzzers/005-tilegrid/ps7_int/generate.tcl

@@ -12,10 +12,10 @@ proc run {} {
     read_verilog top.v
     synth_design -top top
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
     set_property CFGBVS VCCO [current_design]
     set_property CONFIG_VOLTAGE 3.3 [current_design]

fuzzers/005-tilegrid/util.tcl

@@ -80,12 +80,16 @@ proc loc_dut_col_sites { dut_columns cellpre cellpost } {
 
 proc make_io_pad_sites {} {
     # get all possible IOB pins
+    set io_pad_sites [dict create]
     foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] {
         set site [get_sites -of_objects $pad]
         if {[llength $site] == 0} {
             continue
         }
-        if [string match IOB33* [get_property SITE_TYPE $site]] {
+        # High-range (HR) banks expose IOB33 sites; high-performance (HP) banks
+        # (e.g. Virtex-7 "VX" parts) expose IOB18 sites.
+        set site_type [get_property SITE_TYPE $site]
+        if {[string match IOB33* $site_type] || [string match IOB18* $site_type]} {
             dict append io_pad_sites $site $pad
         }
     }
@@ -114,10 +118,10 @@ proc make_iob_sites {} {
 }
 
 proc assign_iobs_old {} {
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
 }
 
 proc assign_iobs {} {
@@ -129,9 +133,9 @@ proc assign_iobs {} {
     # Basic pins
     # XXX: not all pads are valid, but seems to be working for now
     # Maybe better to set to XRAY_PIN_* and take out of the list?
-    set_property -dict "PACKAGE_PIN [lindex $iopad 0] IOSTANDARD LVCMOS33" [get_ports clk]
+    set_property -dict "PACKAGE_PIN [lindex $iopad 0] IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-    set_property -dict "PACKAGE_PIN [lindex $iopad 1] IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN [lindex $iopad 1] IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
-    set_property -dict "PACKAGE_PIN [lindex $iopad 2] IOSTANDARD LVCMOS33" [get_ports stb]
+    set_property -dict "PACKAGE_PIN [lindex $iopad 2] IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
 
     # din bus
     set fixed_pins 3
@@ -139,7 +143,7 @@ proc assign_iobs {} {
     for {set i 0} {$i < [llength $iports]} {incr i} {
         set pad [lindex $iopad [expr $i+$fixed_pins]]
         set port [lindex $iports $i]
-        set_property -dict "PACKAGE_PIN $pad IOSTANDARD LVCMOS33" $port
+        set_property -dict "PACKAGE_PIN $pad IOSTANDARD $::env(XRAY_IOSTANDARD)" $port
     }
 }
 

fuzzers/007-timing/bel/runme.tcl

@@ -13,8 +13,8 @@ proc create_design {} {
     read_verilog $::env(SRC_DIR)/top.v
     synth_design -top top -flatten_hierarchy none
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
     set_property CFGBVS VCCO [current_design]
     set_property CONFIG_VOLTAGE 3.3 [current_design]

fuzzers/007-timing/routing-bels/runme.tcl

@@ -13,8 +13,8 @@ proc create_design {} {
     read_verilog $::env(SRC_DIR)/top.v
     synth_design -top top -flatten_hierarchy none
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
     set_property CFGBVS VCCO [current_design]
     set_property CONFIG_VOLTAGE 3.3 [current_design]

fuzzers/010-clb-lutinit/generate.tcl

@@ -10,10 +10,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog ../../top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
 
 set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
         [get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]

fuzzers/011-clb-ffconfig/generate.tcl

@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
 create_pblock roi
 

fuzzers/011-clb-ffconfig/top.py

@@ -18,7 +18,7 @@ from prims import *
 # INCREMENT is the amount of additional CLBN to be instantiated in the design.
 # This makes the fuzzer compilation more robust against failures.
 INCREMENT = os.getenv('CLBN', 0)
-CLBN = 600 + int(INCREMENT)
+CLBN = 200 + int(INCREMENT)
 print('//Requested CLBs: %s' % str(CLBN))
 
 f = open("top.txt", "w")

fuzzers/012-clb-n5ffmux/generate.tcl

@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
 create_pblock roi
 

fuzzers/013-clb-ncy0/generate.tcl

@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
 create_pblock roi
 

fuzzers/014-clb-ffsrcemux/generate.tcl

@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
 create_pblock roi
 

fuzzers/014-clb-ffsrcemux/top.py

@@ -18,7 +18,7 @@ from prjxray import verilog
 # INCREMENT is the amount of additional CLBN to be instantiated in the design.
 # This makes the fuzzer compilation more robust against failures.
 INCREMENT = os.getenv('CLBN', 0)
-CLBN = 600 + int(INCREMENT)
+CLBN = 200 + int(INCREMENT)
 print('//Requested CLBs: %s' % str(CLBN))
 
 

fuzzers/015-clb-nffmux/generate.sh

@@ -8,6 +8,6 @@
 # SPDX-License-Identifier: ISC
 
 set -ex
-if [ $(${XRAY_VIVADO} -h |grep Vivado |cut -d\  -f 2) != "v2017.2" ] ; then echo "FIXME: requires Vivado 2017.2. See https://github.com/SymbiFlow/prjxray/issues/14"; exit 1; fi
+# (v7: gate disabled, 2020.1 required) if [ $(${XRAY_VIVADO} -h |grep Vivado |cut -d\  -f 2) != "v2017.2" ] ; then echo "FIXME: requires Vivado 2017.2. See https://github.com/SymbiFlow/prjxray/issues/14"; exit 1; fi
 source ${XRAY_DIR}/utils/top_generate.sh
 

fuzzers/015-clb-nffmux/generate.tcl

@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
 create_pblock roi
 

fuzzers/015-clb-nffmux/top.py

@@ -16,7 +16,7 @@ from prjxray import verilog
 # INCREMENT is the amount of additional CLBN to be instantiated in the design.
 # This makes the fuzzer compilation more robust against failures.
 INCREMENT = os.getenv('CLBN', 0)
-CLBN = 600 + int(INCREMENT)
+CLBN = 200 + int(INCREMENT)
 print('//Requested CLBs: %s' % str(CLBN))
 
 

fuzzers/016-clb-noutmux/generate.sh

@@ -8,6 +8,6 @@
 # SPDX-License-Identifier: ISC
 
 set -ex
-if [ $(${XRAY_VIVADO} -h |grep Vivado |cut -d\  -f 2) != "v2017.2" ] ; then echo "FIXME: requires Vivado 2017.2. See https://github.com/SymbiFlow/prjxray/issues/14"; exit 1; fi
+# (v7: gate disabled, 2020.1 required) if [ $(${XRAY_VIVADO} -h |grep Vivado |cut -d\  -f 2) != "v2017.2" ] ; then echo "FIXME: requires Vivado 2017.2. See https://github.com/SymbiFlow/prjxray/issues/14"; exit 1; fi
 source ${XRAY_DIR}/utils/top_generate.sh
 

fuzzers/016-clb-noutmux/generate.tcl

@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
 create_pblock roi
 

fuzzers/016-clb-noutmux/top.py

@@ -16,7 +16,7 @@ from prjxray import verilog
 # INCREMENT is the amount of additional CLBN to be instantiated in the design.
 # This makes the fuzzer compilation more robust against failures.
 INCREMENT = os.getenv('CLBN', 0)
-CLBN = 600 + int(INCREMENT)
+CLBN = 200 + int(INCREMENT)
 print('//Requested CLBs: %s' % str(CLBN))
 
 

fuzzers/017-clb-precyinit/generate.tcl

@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
 create_pblock roi
 

fuzzers/018-clb-ram/generate.py

@@ -76,7 +76,14 @@ for l in f:
         # Each one of: SRL16E, SRLC32E, LUT6
         bels = [p0, p1, p2, p3]
         verbose and print('  %s %s %s %s' % tuple(bels))
-        assert bels == bels_tcl
+        # Skip slices Vivado placed outside the dumped pblock (bels_tcl all
+        # None) or repacked differently, instead of asserting -- mirrors the
+        # RAM-path "if ram != has_bel_tcl: continue" below. This makes the
+        # fuzzer robust to the ROI-edge case (e.g. virtex7's grid-ROI yields a
+        # SLICE column just outside the XRAY_ROI pblock); other families always
+        # match, so this is a no-op for them.
+        if bels != bels_tcl:
+            continue
 
         # Clock Enable (CE) clock gate only enabled if we have clocked elements
         # A pure LUT6 does not, but everything else should

fuzzers/018-clb-ram/generate.tcl

@@ -10,10 +10,10 @@ proc build {} {
     read_verilog top.v
     synth_design -top top
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
     create_pblock roi
 

fuzzers/019-clb-ndi1mux/generate.tcl

@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
 create_pblock roi
 

fuzzers/025-bram-config/generate.tcl

@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
 create_pblock roi
 

fuzzers/025-bram-config/minitest/runme.tcl

@@ -10,10 +10,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog $::env(TOP_V)
 synth_design -top top -flatten_hierarchy none -verilog_define ROI=$::env(PROJECT)
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
 create_pblock roi
 

fuzzers/026-bram-data/minitest/runme.tcl

@@ -10,10 +10,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog $::env(TOP_V)
 synth_design -top top -flatten_hierarchy none -verilog_define ROI=$::env(PROJECT)
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
 create_pblock roi
 

fuzzers/030-iob/minitest/runme.tcl

@@ -10,10 +10,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog $::env(TOP_V)
 synth_design -top top -flatten_hierarchy none -verilog_define ROI=$::env(PROJECT)
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
 # set_property roi/dut
 

fuzzers/030-iob/minitest/template.tcl

@@ -11,10 +11,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog $::env(TOP_V)
 synth_design -top top -flatten_hierarchy none
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
@@ -27,6 +27,6 @@ route_design
 write_checkpoint -force design.dcp
 
 # set port [create_port -direction OUT myport]
-# set_property -dict "PACKAGE_PIN D19 IOSTANDARD LVCMOS33" $port
+# set_property -dict "PACKAGE_PIN D19 IOSTANDARD $::env(XRAY_IOSTANDARD)" $port
 # set_property PULLTYPE PULLUP $port
 # set_property PULLTYPE PULLDOWN $port

fuzzers/030-iob18-sing/Makefile

@@ -0,0 +1,40 @@
+# Copyright (C) 2017-2022  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+#
+# SING-row IOB18 basic-config fuzzer (DRIVE/SLEW/PULLTYPE/STEPDOWN) for the
+# single IOB18 site in each *_SING tile.  Replaces the hand-copied (and
+# mis-addressed) LIOB18_SING entries with real measurements.
+#
+# Unlike regular IOB18 (where L+R share the 'iob18' segbits db and segmaker
+# emits a normalised IOB18. prefix), SING tiles have SEPARATE liob18_sing /
+# riob18_sing dbs, so segmaker emits LIOB18_SING. / RIOB18_SING. and the two
+# sides must be solved independently.  process_rdb.py still re-emits the
+# IOB18. prefix, which the per-side mergedb cases rewrite to LIOB18_SING. /
+# RIOB18_SING.
+N := 30
+include ../fuzzer.mk
+
+database: build/segbits_liob18_sing.db build/segbits_riob18_sing.db
+
+# Per-side: segmatch -> drop unresolved (<.. candidates>, which process_rdb
+# cannot parse) -> process_rdb enum-merge -> dbfixup.
+build/segbits_liob18_sing.db: $(SPECIMENS_OK)
+	${XRAY_SEGMATCH} -o build/raw_l.rdb $$(find -name 'segdata_liob18_sing.txt')
+	python3 process_rdb.py build/raw_l.rdb > build/proc_l.rdb
+	${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in build/proc_l.rdb --seg-fn-out $@
+
+build/segbits_riob18_sing.db: $(SPECIMENS_OK)
+	${XRAY_SEGMATCH} -o build/raw_r.rdb $$(find -name 'segdata_riob18_sing.txt')
+	python3 process_rdb.py build/raw_r.rdb > build/proc_r.rdb
+	${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in build/proc_r.rdb --seg-fn-out $@
+
+pushdb:
+	${XRAY_MERGEDB} liob18_sing build/segbits_liob18_sing.db
+	${XRAY_MERGEDB} riob18_sing build/segbits_riob18_sing.db
+
+.PHONY: database pushdb

fuzzers/030-iob18-sing/derive_drive_from_liob18.py

@@ -0,0 +1,64 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2022  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+"""
+Fallback for SING IOB DRIVE/STEPDOWN: the *_SING tiles have only ~28 IOB18
+sites on the whole device, too few for segmatch to isolate the multi-bit DRIVE
+enum (the OUT bit stays <N candidates>).  The SING IOB18 is the *same* IOB18
+primitive as the regular LIOB18/RIOB18 tiles, and the SING fuzz that DID
+resolve (IN/SLEW/PULLTYPE, and the DRIVE candidate bits 38_32/38_34/39_23/39_55)
+matches the regular tile bit-for-bit.  So derive the unresolved SING features
+from the REAL virtex7 LIOB18/RIOB18 measurements (origin 030-iob18) rather than
+leave them hand-copied/absent.
+
+Emits, on stdout, the requested feature group(s) for the *_SING tile type,
+copied from the same feature on the regular tile.  Intended to be appended to
+the per-side SING db before pushdb, for ONLY the features the SING fuzz could
+not solve (default: DRIVE and STEPDOWN).
+"""
+import argparse
+
+
+def load(fn):
+    d = {}
+    for line in open(fn):
+        line = line.strip()
+        if not line:
+            continue
+        tag, _, bits = line.partition(' ')
+        d[tag] = bits
+    return d
+
+
+def main():
+    ap = argparse.ArgumentParser()
+    ap.add_argument('--src-db', required=True, help='segbits_liob18.db (real)')
+    ap.add_argument('--src-prefix', default='LIOB18')
+    ap.add_argument('--dst-prefix', default='LIOB18_SING')
+    ap.add_argument(
+        '--groups', nargs='+', default=['DRIVE', 'STEPDOWN'],
+        help='feature groups to derive (substring match after the site)')
+    args = ap.parse_args()
+
+    src = load(args.src_db)
+    for tag, bits in sorted(src.items()):
+        if not tag.startswith(args.src_prefix + '.'):
+            continue
+        # tag = PREFIX.IOB_Yn.<iostds>.<group>[.<enum>]
+        rest = tag[len(args.src_prefix) + 1:]
+        parts = rest.split('.')
+        if len(parts) < 3:
+            continue
+        group = parts[2]
+        if group not in args.groups:
+            continue
+        print('{}.{} {}'.format(args.dst_prefix, rest, bits))
+
+
+if __name__ == '__main__':
+    main()

fuzzers/030-iob18-sing/generate.py

@@ -0,0 +1,94 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2022  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+"""
+SING-row sibling of 030-iob18.  Tags the basic IOB18 config (IN_USE / OUT / IN /
+IN_ONLY / IN_DIFF / PULLTYPE / DRIVE / SLEW / STEPDOWN) for the single IOB18
+site in each *_SING tile, per the OBUF / IBUF / unused type chosen in top.py.
+
+Reuses 030-iob18's drive_opts / enum-zero convention so the merged feature
+names (after process_rdb.py) match nextpnr, e.g.
+LVCMOS15_LVCMOS18.DRIVE.I12_I16_I2_I4_I6_I8.  Single-ended only.
+"""
+from prjxray.segmaker import Segmaker
+from prjxray import segmaker
+from prjxray import verilog
+import json
+
+LVCMOS = ['LVCMOS12', 'LVCMOS15', 'LVCMOS18']
+
+
+def bitfilter(frame, word):
+    # SING tile frames differ from regular LIOB18; let segmatch find them.
+    return True
+
+
+def mk_drive_opt(iostandard, drive):
+    if drive is None:
+        drive = '_FIXED'
+    return '{}.DRIVE.I{}'.format(iostandard, drive)
+
+
+def main():
+    print("Loading tags")
+    segmk = Segmaker("design.bits")
+
+    with open('params.jl', 'r') as f:
+        design = json.load(f)
+
+    for d in design:
+        site = d['site']
+        iostandard = verilog.unquote(d['IOSTANDARD'])
+        typ = d['type']  # 'OBUF', 'IBUF', or None (unused)
+
+        in_use = 1 if typ is not None else 0
+        is_out = 1 if typ == 'OBUF' else 0
+        is_in = 1 if typ == 'IBUF' else 0
+
+        segmk.add_site_tag(site, 'INOUT', 0)
+        segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), in_use)
+        segmk.add_site_tag(site, '{}.OUT'.format(iostandard), is_out)
+        segmk.add_site_tag(site, '{}.IN'.format(iostandard), is_in)
+        segmk.add_site_tag(site, '{}.IN_ONLY'.format(iostandard), is_in)
+        segmk.add_site_tag(site, '{}.IN_DIFF'.format(iostandard), 0)
+
+        # PULLTYPE applies whenever the IOB is in use.
+        if in_use:
+            segmaker.add_site_group_zero(
+                segmk, site, "PULLTYPE.",
+                ("NONE", "KEEPER", "PULLDOWN", "PULLUP"), "PULLDOWN",
+                verilog.unquote(d['PULLTYPE']))
+
+        # DRIVE / SLEW / STEPDOWN only meaningful for output buffers.
+        if typ == 'OBUF':
+            drive_opts = set()
+            for opt in LVCMOS:
+                for drive_opt in ("2", "4", "6", "8", "12", "16"):
+                    if drive_opt in ["12", "16"] and opt == "LVCMOS12":
+                        continue
+                    drive_opts.add(mk_drive_opt(opt, drive_opt))
+            segmaker.add_site_group_zero(
+                segmk, site, '', drive_opts, mk_drive_opt('LVCMOS25', '12'),
+                mk_drive_opt(iostandard, d['DRIVE']))
+
+            if d['SLEW']:
+                for opt in ["SLOW", "FAST"]:
+                    segmk.add_site_tag(
+                        site, iostandard + ".SLEW." + opt,
+                        opt == verilog.unquote(d['SLEW']))
+
+            segmk.add_site_tag(site, '{}.STEPDOWN'.format(iostandard), 1)
+
+    segmk.compile(bitfilter=bitfilter)
+    segmk.write(allow_empty=True)
+
+
+if __name__ == "__main__":
+    main()

fuzzers/030-iob18-sing/generate.tcl

@@ -0,0 +1,107 @@
+# Copyright (C) 2017-2022  The Project X-Ray Authors
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+source "$::env(XRAY_DIR)/utils/utils.tcl"
+
+proc make_io_pin_sites {} {
+    # get all possible IOB pins
+    foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] {
+        set site [get_sites -of_objects $pad]
+        if {[llength $site] == 0} {
+            continue
+        }
+        if [string match IOB18* [get_property SITE_TYPE $site]] {
+            dict append io_pin_sites $site $pad
+        }
+    }
+    return $io_pin_sites
+}
+
+proc load_pin_lines {} {
+    # IOB_X0Y103 clk input
+    # IOB_X0Y129 do[0] output
+
+    set fp [open "params.csv" r]
+    gets $fp line
+
+    set pin_lines {}
+    for {gets $fp line} {$line != ""} {gets $fp line} {
+        lappend pin_lines [split $line ","]
+    }
+    close $fp
+    return $pin_lines
+}
+
+proc loc_pins {} {
+    set pin_lines [load_pin_lines]
+    set io_pin_sites [make_io_pin_sites]
+
+    puts "Looping"
+    for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} {
+        set line [lindex $pin_lines $idx]
+        puts "$line"
+
+        set site_str [lindex $line 1]
+        set pin_str [lindex $line 2]
+        set iostandard [lindex $line 3]
+        set drive [lindex $line 4]
+        set slew [lindex $line 5]
+        set pulltype [lindex $line 6]
+
+        # Have: site
+        # Want: pin for site
+
+        set site [get_sites $site_str]
+        set pad_bel [get_bels -of_objects $site -filter {TYPE =~ PAD && NAME =~ IOB_*}]
+        # set port [get_ports -of_objects $site]
+        set port [get_ports $pin_str]
+        set tile [get_tiles -of_objects $site]
+
+        set pin [dict get $io_pin_sites $site]
+
+        set props {}
+        #lappend props PACKAGE_PIN $pin
+        lappend props IOSTANDARD $iostandard
+        lappend props PULLTYPE $pulltype
+
+        if {$drive != "None"} {
+            lappend props DRIVE $drive
+        }
+
+        if {$slew != "None"} {
+            lappend props SLEW $slew
+        }
+
+        puts $props
+
+        set_property -dict "$props" $port
+    }
+}
+
+proc run {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    loc_pins
+
+    set_property CFGBVS GND [current_design]
+    set_property CONFIG_VOLTAGE 1.8 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-79}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-144}]
+
+    write_checkpoint -force design_pre_place.dcp
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+}
+
+run

fuzzers/030-iob18-sing/iostandards.py

@@ -0,0 +1,17 @@
+LVCMOS       = ['LVCMOS12', 'LVCMOS15', 'LVCMOS18']
+
+# TODO: add support for digitally controlled impedance (_DCI) and termination (_T)
+SSTL         = ['SSTL15',  #'SSTL15_DCI',  'SSTL15_T_DCI'
+                'SSTL135', #'SSTL135_DCI', 'SSTL135_T_DCI'
+                'SSTL12',  #'SSTL12_DCI',  'SSTL12_T_DCI'
+               ]
+
+# TODO: add support for digitally controlled impedance (_DCI) and termination (_T)
+DIFF_SSTL15  = ['DIFF_SSTL15',  ] # 'DIFF_SSTL15_DCI',  'DIFF_SSTL15_T_DCI']
+DIFF_SSTL135 = ['DIFF_SSTL135', ] # 'DIFF_SSTL135_DCI', 'DIFF_SSTL135_T_DCI']
+DIFF_SSTL12  = ['DIFF_SSTL12',  ] # 'DIFF_SSTL12_DCI',  'DIFF_SSTL12_T_DCI']
+DIFF_SSTL    = DIFF_SSTL15 + DIFF_SSTL135 + DIFF_SSTL12
+
+LVDS         = ['LVDS']
+
+DIFF         = DIFF_SSTL + LVDS

fuzzers/030-iob18-sing/params.csv

@@ -0,0 +1,23 @@
+tile,site,pin,iostandard,drive,slew,pulltype
+LIOB18_SING_X81Y1,IOB_X0Y0,di[0],LVCMOS15,6,FAST,PULLUP
+LIOB18_SING_X81Y103,IOB_X0Y99,di[1],LVCMOS15,2,SLOW,KEEPER
+LIOB18_SING_X81Y155,IOB_X0Y149,di[2],LVCMOS15,2,SLOW,PULLDOWN
+LIOB18_SING_X81Y157,IOB_X0Y150,do[0],LVCMOS15,4,FAST,PULLDOWN
+LIOB18_SING_X81Y209,IOB_X0Y200,do[1],LVCMOS15,16,SLOW,PULLUP
+LIOB18_SING_X81Y259,IOB_X0Y249,do[2],LVCMOS15,4,SLOW,PULLDOWN
+LIOB18_SING_X81Y261,IOB_X0Y250,di[3],LVCMOS15,16,FAST,KEEPER
+LIOB18_SING_X81Y311,IOB_X0Y299,di[4],LVCMOS15,6,SLOW,KEEPER
+LIOB18_SING_X81Y313,IOB_X0Y300,di[5],LVCMOS15,12,FAST,NONE
+LIOB18_SING_X81Y363,IOB_X0Y349,di[6],LVCMOS15,16,FAST,PULLUP
+LIOB18_SING_X81Y51,IOB_X0Y49,di[7],LVCMOS15,12,FAST,PULLUP
+RIOB18_SING_X312Y1,IOB_X1Y0,di[8],LVCMOS15,12,FAST,NONE
+RIOB18_SING_X312Y103,IOB_X1Y99,di[9],LVCMOS15,2,SLOW,PULLUP
+RIOB18_SING_X312Y157,IOB_X1Y150,di[10],LVCMOS15,8,FAST,PULLDOWN
+RIOB18_SING_X312Y207,IOB_X1Y199,do[3],LVCMOS15,16,FAST,NONE
+RIOB18_SING_X312Y259,IOB_X1Y249,di[11],LVCMOS15,12,SLOW,PULLUP
+RIOB18_SING_X312Y261,IOB_X1Y250,di[12],LVCMOS15,2,SLOW,NONE
+RIOB18_SING_X312Y311,IOB_X1Y299,di[13],LVCMOS15,2,FAST,NONE
+RIOB18_SING_X312Y313,IOB_X1Y300,di[14],LVCMOS15,16,FAST,PULLDOWN
+RIOB18_SING_X312Y363,IOB_X1Y349,di[15],LVCMOS15,6,SLOW,NONE
+RIOB18_SING_X312Y51,IOB_X1Y49,di[16],LVCMOS15,4,SLOW,KEEPER
+RIOB18_SING_X312Y53,IOB_X1Y50,do[4],LVCMOS15,16,FAST,NONE

fuzzers/030-iob18-sing/params.jl

@@ -0,0 +1,282 @@
+[
+  {
+    "tile": "LIOB18_SING_X81Y1",
+    "site": "IOB_X0Y0",
+    "type": "IBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 6,
+    "SLEW": "\"FAST\"",
+    "PULLTYPE": "\"PULLUP\"",
+    "pin": "di[0]"
+  },
+  {
+    "tile": "LIOB18_SING_X81Y103",
+    "site": "IOB_X0Y99",
+    "type": "IBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 2,
+    "SLEW": "\"SLOW\"",
+    "PULLTYPE": "\"KEEPER\"",
+    "pin": "di[1]"
+  },
+  {
+    "tile": "LIOB18_SING_X81Y105",
+    "site": "IOB_X0Y100",
+    "type": null,
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 12,
+    "SLEW": "\"FAST\"",
+    "PULLTYPE": "\"KEEPER\"",
+    "pin": null
+  },
+  {
+    "tile": "LIOB18_SING_X81Y155",
+    "site": "IOB_X0Y149",
+    "type": "IBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 2,
+    "SLEW": "\"SLOW\"",
+    "PULLTYPE": "\"PULLDOWN\"",
+    "pin": "di[2]"
+  },
+  {
+    "tile": "LIOB18_SING_X81Y157",
+    "site": "IOB_X0Y150",
+    "type": "OBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 4,
+    "SLEW": "\"FAST\"",
+    "PULLTYPE": "\"PULLDOWN\"",
+    "pin": "do[0]"
+  },
+  {
+    "tile": "LIOB18_SING_X81Y207",
+    "site": "IOB_X0Y199",
+    "type": null,
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 12,
+    "SLEW": "\"SLOW\"",
+    "PULLTYPE": "\"NONE\"",
+    "pin": null
+  },
+  {
+    "tile": "LIOB18_SING_X81Y209",
+    "site": "IOB_X0Y200",
+    "type": "OBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 16,
+    "SLEW": "\"SLOW\"",
+    "PULLTYPE": "\"PULLUP\"",
+    "pin": "do[1]"
+  },
+  {
+    "tile": "LIOB18_SING_X81Y259",
+    "site": "IOB_X0Y249",
+    "type": "OBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 4,
+    "SLEW": "\"SLOW\"",
+    "PULLTYPE": "\"PULLDOWN\"",
+    "pin": "do[2]"
+  },
+  {
+    "tile": "LIOB18_SING_X81Y261",
+    "site": "IOB_X0Y250",
+    "type": "IBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 16,
+    "SLEW": "\"FAST\"",
+    "PULLTYPE": "\"KEEPER\"",
+    "pin": "di[3]"
+  },
+  {
+    "tile": "LIOB18_SING_X81Y311",
+    "site": "IOB_X0Y299",
+    "type": "IBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 6,
+    "SLEW": "\"SLOW\"",
+    "PULLTYPE": "\"KEEPER\"",
+    "pin": "di[4]"
+  },
+  {
+    "tile": "LIOB18_SING_X81Y313",
+    "site": "IOB_X0Y300",
+    "type": "IBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 12,
+    "SLEW": "\"FAST\"",
+    "PULLTYPE": "\"NONE\"",
+    "pin": "di[5]"
+  },
+  {
+    "tile": "LIOB18_SING_X81Y363",
+    "site": "IOB_X0Y349",
+    "type": "IBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 16,
+    "SLEW": "\"FAST\"",
+    "PULLTYPE": "\"PULLUP\"",
+    "pin": "di[6]"
+  },
+  {
+    "tile": "LIOB18_SING_X81Y51",
+    "site": "IOB_X0Y49",
+    "type": "IBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 12,
+    "SLEW": "\"FAST\"",
+    "PULLTYPE": "\"PULLUP\"",
+    "pin": "di[7]"
+  },
+  {
+    "tile": "LIOB18_SING_X81Y53",
+    "site": "IOB_X0Y50",
+    "type": null,
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 12,
+    "SLEW": "\"SLOW\"",
+    "PULLTYPE": "\"NONE\"",
+    "pin": null
+  },
+  {
+    "tile": "RIOB18_SING_X312Y1",
+    "site": "IOB_X1Y0",
+    "type": "IBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 12,
+    "SLEW": "\"FAST\"",
+    "PULLTYPE": "\"NONE\"",
+    "pin": "di[8]"
+  },
+  {
+    "tile": "RIOB18_SING_X312Y103",
+    "site": "IOB_X1Y99",
+    "type": "IBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 2,
+    "SLEW": "\"SLOW\"",
+    "PULLTYPE": "\"PULLUP\"",
+    "pin": "di[9]"
+  },
+  {
+    "tile": "RIOB18_SING_X312Y105",
+    "site": "IOB_X1Y100",
+    "type": null,
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 12,
+    "SLEW": "\"FAST\"",
+    "PULLTYPE": "\"KEEPER\"",
+    "pin": null
+  },
+  {
+    "tile": "RIOB18_SING_X312Y155",
+    "site": "IOB_X1Y149",
+    "type": null,
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 12,
+    "SLEW": "\"FAST\"",
+    "PULLTYPE": "\"KEEPER\"",
+    "pin": null
+  },
+  {
+    "tile": "RIOB18_SING_X312Y157",
+    "site": "IOB_X1Y150",
+    "type": "IBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 8,
+    "SLEW": "\"FAST\"",
+    "PULLTYPE": "\"PULLDOWN\"",
+    "pin": "di[10]"
+  },
+  {
+    "tile": "RIOB18_SING_X312Y207",
+    "site": "IOB_X1Y199",
+    "type": "OBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 16,
+    "SLEW": "\"FAST\"",
+    "PULLTYPE": "\"NONE\"",
+    "pin": "do[3]"
+  },
+  {
+    "tile": "RIOB18_SING_X312Y209",
+    "site": "IOB_X1Y200",
+    "type": null,
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 4,
+    "SLEW": "\"SLOW\"",
+    "PULLTYPE": "\"PULLUP\"",
+    "pin": null
+  },
+  {
+    "tile": "RIOB18_SING_X312Y259",
+    "site": "IOB_X1Y249",
+    "type": "IBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 12,
+    "SLEW": "\"SLOW\"",
+    "PULLTYPE": "\"PULLUP\"",
+    "pin": "di[11]"
+  },
+  {
+    "tile": "RIOB18_SING_X312Y261",
+    "site": "IOB_X1Y250",
+    "type": "IBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 2,
+    "SLEW": "\"SLOW\"",
+    "PULLTYPE": "\"NONE\"",
+    "pin": "di[12]"
+  },
+  {
+    "tile": "RIOB18_SING_X312Y311",
+    "site": "IOB_X1Y299",
+    "type": "IBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 2,
+    "SLEW": "\"FAST\"",
+    "PULLTYPE": "\"NONE\"",
+    "pin": "di[13]"
+  },
+  {
+    "tile": "RIOB18_SING_X312Y313",
+    "site": "IOB_X1Y300",
+    "type": "IBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 16,
+    "SLEW": "\"FAST\"",
+    "PULLTYPE": "\"PULLDOWN\"",
+    "pin": "di[14]"
+  },
+  {
+    "tile": "RIOB18_SING_X312Y363",
+    "site": "IOB_X1Y349",
+    "type": "IBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 6,
+    "SLEW": "\"SLOW\"",
+    "PULLTYPE": "\"NONE\"",
+    "pin": "di[15]"
+  },
+  {
+    "tile": "RIOB18_SING_X312Y51",
+    "site": "IOB_X1Y49",
+    "type": "IBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 4,
+    "SLEW": "\"SLOW\"",
+    "PULLTYPE": "\"KEEPER\"",
+    "pin": "di[16]"
+  },
+  {
+    "tile": "RIOB18_SING_X312Y53",
+    "site": "IOB_X1Y50",
+    "type": "OBUF",
+    "IOSTANDARD": "\"LVCMOS15\"",
+    "DRIVE": 16,
+    "SLEW": "\"FAST\"",
+    "PULLTYPE": "\"NONE\"",
+    "pin": "do[4]"
+  }
+]

fuzzers/030-iob18-sing/process_rdb.py

@@ -0,0 +1,266 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2022  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+""" IOB bits are more complicated than can be easily expressed to segmaker.
+There are couple cases that need to be handled here:
+
+- There are some bits that are always set for IN-only ports, but are cleared
+  selectively for OUT and INOUT ports.
+- There are bits per each IOSTANDARD, in addition to drive patterns.  These
+  can be merged to provide unique "(IOSTANDARD, DRIVE)" bit sets.
+"""
+import argparse
+import os
+
+
+def get_name(l):
+    parts = l.strip().split(' ')
+    return parts[0]
+
+
+def get_site(l):
+    return get_name(l).split('.')[1]
+
+
+def parse_bits(l):
+    parts = l.strip().split(' ')
+    # Any segmatch marker (<0 candidates>, <5 candidates>, <const0>, <const1>)
+    # means "no solved bits"; treat uniformly as empty so a site that has some
+    # unresolved DRIVE/SLEW entries still keeps the group (avoids KeyError) and
+    # the resolved siblings drive the enum-merge.
+    if parts[1].startswith('<'):
+        return frozenset()
+    else:
+        return frozenset(parts[1:])
+
+
+def filter_negbits(site, feature, bits):
+    lvds_bits = frozenset(['!38_24', "!38_48", "!39_33", '!39_47', '!39_49'])
+    if "IOB_Y0" in feature and not "LVDS" in feature:
+        bits = bits.difference(lvds_bits)
+    if feature.endswith("IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN"):
+        bits = bits.difference(frozenset(['!39_01']))
+    if feature.endswith("IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN"):
+        bits = bits.difference(frozenset(['!38_126']))
+
+    return bits
+
+
+def process_features_sets(iostandard_lines):
+    sites = {}
+
+    for iostd_type, iostd_list in iostandard_lines.items():
+        for iostd_line in iostd_list:
+            feature = get_name(iostd_line)
+            feature_parts = feature.split('.')
+            site = get_site(iostd_line)
+            iostandard = feature_parts[2]
+
+            bits = parse_bits(iostd_line)
+
+            key = (site, iostd_type)
+            if key not in sites:
+                sites[key] = {}
+
+            group = feature_parts[3]
+            if group not in sites[key]:
+                sites[key][group] = {}
+
+            if group in ['DRIVE', 'SLEW']:
+                enum = feature_parts[4]
+                sites[key][group][(iostandard, enum)] = bits
+            elif group in ['IN', 'IN_DIFF', 'IN_ONLY', 'IN_USE', 'OUT',
+                           'STEPDOWN', 'ZIBUF_LOW_PWR']:
+                sites[key][group][(iostandard, None)] = bits
+            else:
+                assert False, group
+
+    for site in sites:
+        for iostandard, enum in sites[site]['DRIVE']:
+            sites[site]['DRIVE'][(iostandard, enum)] |= sites[site]['OUT'][(
+                iostandard, None)]
+
+        for iostandard, enum in sites[site]['IN']:
+            sites[site]['IN_ONLY'][(iostandard, enum)] -= sites[site]['IN'][(
+                iostandard, enum)]
+
+    common_bits = {}
+    for site, iostd_type in sites:
+        for group in sites[(site, iostd_type)]:
+            if (site, group) not in common_bits:
+                common_bits[(site, group)] = set()
+
+            for bits in sites[(site, iostd_type)][group].values():
+                common_bits[(site, group)] |= bits
+
+    slew_in_drives = {}
+
+    for site, iostd_type in sites:
+        common_bits[(site, 'IN')] |= common_bits[(site, 'IN_DIFF')]
+        common_bits[(site, 'IN_DIFF')] |= common_bits[(site, 'IN')]
+
+        # Only DIFF IOSTANDARDS such as LVDS or TMDS do not have DRIVE or SLEW features
+        if iostd_type == "NORMAL":
+            key = (site, iostd_type)
+            common_bits[(site, 'DRIVE')] -= common_bits[(site, 'SLEW')]
+            common_bits[(site, 'IN_ONLY')] |= common_bits[(site, 'DRIVE')]
+
+            for iostandard, enum in sites[key]['DRIVE']:
+                slew_in_drive = common_bits[
+                    (site, 'SLEW')] & sites[key]['DRIVE'][(iostandard, enum)]
+                if slew_in_drive:
+                    if (key, iostandard) not in slew_in_drives:
+                        slew_in_drives[(key, iostandard)] = set()
+
+                    slew_in_drives[(key, iostandard)] |= slew_in_drive
+                    sites[key]['DRIVE'][(iostandard, enum)] -= slew_in_drive
+
+    for site, iostandard in slew_in_drives:
+        for _, enum in sites[site]['SLEW']:
+            sites[site]['SLEW'][(iostandard,
+                                 enum)] |= slew_in_drives[(site, iostandard)]
+
+    for site in sites:
+        for iostandard, enum in sites[site]['DRIVE']:
+            sites[site]['DRIVE'][(iostandard, enum)] |= sites[site]['IN_USE'][(
+                iostandard, None)]
+
+        for iostandard, enum in sites[site]['IN']:
+            _, iostd_type = site
+            if iostd_type == "ONLY_DIFF":
+                sites[site]['IN_DIFF'][(iostandard, enum)] = \
+                        sites[site]['IN'][(iostandard, enum)]
+            elif sites[site]['IN_DIFF'][(iostandard, enum)]:
+                sites[site]['IN_DIFF'][(iostandard, enum)] |= \
+                        sites[site]['IN'][(iostandard, enum)]
+
+    for site, iostd_type in sites:
+        if iostd_type == "NORMAL":
+            del sites[(site, iostd_type)]['OUT']
+
+    allow_zero = ['SLEW']
+
+    common_groups = dict()
+    for site, iostd_type in sites:
+        if site not in common_groups:
+            common_groups[site] = dict()
+
+        key = (site, iostd_type)
+        for group in sites[key]:
+            if iostd_type == "ONLY_DIFF" and group == "IN":
+                continue
+
+            # Merge features that are identical.
+            #
+            # For example:
+            #
+            #  IOB18.IOB_Y1.LVCMOS15.IN 38_42 39_41
+            #  IOB18.IOB_Y1.LVCMOS18.IN 38_42 39_41
+            #
+            # Must be grouped.
+            for (iostandard, enum), bits in sites[key][group].items():
+                if (bits, group) not in common_groups[site]:
+                    common_groups[site][(bits, group)] = {
+                        'IOSTANDARDS': set(),
+                        'enums': set(),
+                    }
+
+                common_groups[site][(bits,
+                                     group)]['IOSTANDARDS'].add(iostandard)
+                if enum is not None:
+                    common_groups[site][(bits, group)]['enums'].add(enum)
+
+    # On Virtex-7 some Y1 IN groups differ from their Y0 counterparts by a
+    # single bit (e.g. LVCMOS* sets 39_01 while SSTL* does not), so the
+    # name-harmonisation below must not fold two distinct-bit groups onto one
+    # feature name -- doing so emits duplicate db lines that break dbfixup.
+    # Require identical bits before adopting a visited name for virtex7; other
+    # families never produce two-group Y1 IN splits, so they are unaffected.
+    require_same_bits = os.environ.get('XRAY_DATABASE') == 'virtex7'
+
+    visited_iostandards = list()
+    for site, groups in common_groups.items():
+        for (bits, group), v in groups.items():
+            iostandards = v['IOSTANDARDS']
+            enums = v['enums']
+
+            # It happens that some features appear only in one of the IOB sites and not
+            # in the other. This makes it hard to assign the correct features to the correct
+            # site in the P&R toolchain.
+            #
+            # The following code makes sure that the same set of iostandards
+            # (even if not really present at a site location) appears for each site
+            for visited_iostandard, visited_group, visited_enums, visited_bits in visited_iostandards:
+                same_enum = enums == visited_enums
+                same_group = group == visited_group
+                compatible_iostd = any(
+                    x in iostandards for x in visited_iostandard)
+                take_visited_iostd = len(visited_iostandard) > len(iostandards)
+                same_bits = bits == visited_bits
+                if same_enum and same_group and compatible_iostd and take_visited_iostd \
+                        and (same_bits or not require_same_bits):
+                    iostandards = visited_iostandard
+                    break
+
+            visited_iostandards.append((iostandards, group, enums, bits))
+
+            iostandards_string = '_'.join(sorted(iostandards))
+
+            if enums:
+                feature = 'IOB18.{site}.{iostandards}.{group}.{enums}'.format(
+                    site=site,
+                    iostandards=iostandards_string,
+                    group=group,
+                    enums='_'.join(sorted(enums)),
+                )
+            else:
+                feature = 'IOB18.{site}.{iostandards}.{group}'.format(
+                    site=site,
+                    iostandards=iostandards_string,
+                    group=group,
+                )
+
+            if not bits and group not in allow_zero:
+                continue
+
+            neg_bits = frozenset(
+                '!{}'.format(b) for b in (common_bits[(site, group)] - bits))
+            neg_bits = filter_negbits(site, feature, neg_bits)
+            print('{} {}'.format(feature, ' '.join(sorted(bits | neg_bits))))
+
+
+def main():
+    parser = argparse.ArgumentParser(
+        description="Convert IOB rdb into good rdb."
+        "")
+    parser.add_argument('input_rdb')
+
+    args = parser.parse_args()
+
+    iostandard_lines = {
+        "NORMAL": list(),
+        "ONLY_DIFF": list(),
+    }
+
+    with open(args.input_rdb) as f:
+        for l in f:
+            if ('.SSTL' in l or '.LVCMOS' in l
+                    or '.LVTTL' in l) and 'IOB_' in l:
+                iostandard_lines["NORMAL"].append(l)
+            elif ('.TMDS' in l or 'LVDS' in l):
+                iostandard_lines["ONLY_DIFF"].append(l)
+            else:
+                print(l.strip())
+
+    process_features_sets(iostandard_lines)
+
+
+if __name__ == "__main__":
+    main()

fuzzers/030-iob18-sing/top.py

@@ -0,0 +1,126 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2022  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+"""
+SING-row IOB18 basic-config fuzzer design.  For each IOB18 site that lives in a
+*_SING tile, randomly instantiate OBUF / IBUF / nothing.  The mix of driven,
+input-only and unused sites gives segmaker the 0-reference it needs to resolve
+the OUT / DRIVE / IN_USE bits (an all-output design leaves them const-1).
+
+DRIVE / SLEW / PULLTYPE are applied to the ports by generate.tcl's loc_pins
+from params.csv; the per-site type is recorded in params.jl for generate.py.
+"""
+import json
+import os
+import random
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray import verilog
+from prjxray.db import Database
+
+# HP banks: low-voltage standards only.
+IOSTANDARDS = ['LVCMOS12', 'LVCMOS15', 'LVCMOS18']
+PULLS = ["NONE", "KEEPER", "PULLDOWN", "PULLUP"]
+SLEWS = ['FAST', 'SLOW']
+# OBUF (drive out), IBUF (input only) and unused, weighted toward variety.
+TYPES = ['OBUF', 'OBUF', 'IBUF', 'IBUF', None, None]
+
+
+def drives_for(iostandard):
+    if iostandard == 'LVCMOS12':
+        return [2, 4, 6, 8]
+    return [2, 4, 6, 8, 12, 16]
+
+
+def gen_sites():
+    db = Database(util.get_db_root(), util.get_part())
+    grid = db.grid()
+    for tile_name in sorted(grid.tiles()):
+        gridinfo = grid.gridinfo_at_loc(grid.loc_of_tilename(tile_name))
+        if not gridinfo.tile_type.endswith("_SING"):
+            continue
+        for site_name, site_type in gridinfo.sites.items():
+            if site_type == 'IOB18':
+                yield tile_name, site_name
+
+
+def main():
+    # One IOSTANDARD per specimen: all SING IOBs share it so a bank never sees
+    # conflicting VCCO (DRC BIVC-1).  Variety across the N specimens gives
+    # process_rdb the LVCMOS12/15/18 set it merges into the DRIVE enum names.
+    iostandard = random.choice(IOSTANDARDS)
+    params = []
+    for tile, site in gen_sites():
+        params.append(
+            {
+                'tile': tile,
+                'site': site,
+                'type': random.choice(TYPES),
+                'IOSTANDARD': verilog.quote(iostandard),
+                'DRIVE': random.choice(drives_for(iostandard)),
+                'SLEW': verilog.quote(random.choice(SLEWS)),
+                'PULLTYPE': verilog.quote(random.choice(PULLS)),
+            })
+
+    # params.csv for generate.tcl's loc_pins (tile,site,pin,iostd,drive,slew,pull)
+    lines = ['tile,site,pin,iostandard,drive,slew,pulltype']
+    n_in = n_out = 0
+    for p in params:
+        if p['type'] == 'OBUF':
+            p['pin'] = 'do[{}]'.format(n_out)
+            n_out += 1
+        elif p['type'] == 'IBUF':
+            p['pin'] = 'di[{}]'.format(n_in)
+            n_in += 1
+        else:
+            p['pin'] = None
+            continue
+        lines.append(
+            ','.join(
+                map(
+                    str, (
+                        p['tile'], p['site'], p['pin'],
+                        verilog.unquote(p['IOSTANDARD']), p['DRIVE'],
+                        verilog.unquote(p['SLEW']),
+                        verilog.unquote(p['PULLTYPE'])))))
+    open('params.csv', 'w').write('\n'.join(lines) + '\n')
+
+    with open('params.jl', 'w') as f:
+        json.dump(params, f, indent=2)
+
+    # Verilog: one OBUF / IBUF per used site, LOC'd; unused sites get nothing.
+    # OBUFs are driven by a DONT_TOUCH LUT source (no external clock port, which
+    # would be an unplaceable terminal); DRIVE/SLEW/PULLTYPE come from loc_pins.
+    print('module top(output wire [{no}:0] do, input wire [{ni}:0] di);'.format(
+        no=max(n_out - 1, 0), ni=max(n_in - 1, 0)))
+    print('    wire src;')
+    print('    (* KEEP, DONT_TOUCH *) '
+          'LUT6 #(.INIT(64\'hAAAAAAAAAAAAAAAA)) srclut '
+          '(.O(src), .I0(1\'b0), .I1(1\'b0), .I2(1\'b0), '
+          '.I3(1\'b0), .I4(1\'b0), .I5(1\'b0));')
+    for idx, p in enumerate(params):
+        if p['type'] == 'OBUF':
+            print(
+                '''
+    (* KEEP, DONT_TOUCH, LOC = "{site}" *)
+    OBUF obuf_{idx} (.I(src), .O({pin}));'''.format(
+                    site=p['site'], idx=idx, pin=p['pin']))
+        elif p['type'] == 'IBUF':
+            print(
+                '''
+    wire ib_{idx};
+    (* KEEP, DONT_TOUCH, LOC = "{site}" *)
+    IBUF ibuf_{idx} (.I({pin}), .O(ib_{idx}));'''.format(
+                    site=p['site'], idx=idx, pin=p['pin']))
+    print('endmodule')
+
+
+if __name__ == '__main__':
+    main()

fuzzers/030-iob18/Makefile

@@ -16,7 +16,12 @@ build/iobanks.txt: write_io_banks.tcl
 	cd build/ && ${XRAY_VIVADO} -mode batch -source ../write_io_banks.tcl
 
 build/segbits_riob18.rdb: $(SPECIMENS_OK)
-	${XRAY_SEGMATCH} -c 23 -o build/segbits_riob18.rdb $$(find -name segdata_riob18.txt)
+	# Glob both L- and R-side segdata: top.py iterates IOB18 sites on both
+	# sides of the chip, but kintex7's R-only Makefile only used the R-side
+	# files. Virtex-7 xc7vx485tffg1761-2 has IOB18 banks on both sides, so
+	# include segdata_liob18.txt too. IOB18 architecture is symmetric so
+	# segmatch will derive consistent bit positions across L and R samples.
+	${XRAY_SEGMATCH} -c 23 -o build/segbits_riob18.rdb $$(find -name 'segdata_[rl]iob18.txt')
 
 build/segbits_riob18.db: build/segbits_riob18.rdb process_rdb.py bits.dbf
 #   delete the Y1 LVDS tags because they are empty anyway and are missing the DRIVE tag which upsets process_rdb.py
@@ -24,9 +29,14 @@ build/segbits_riob18.db: build/segbits_riob18.rdb process_rdb.py bits.dbf
 	python3 process_rdb.py build/segbits_riob18.rdb > build/segbits_riob18_processed.rdb
 	${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --groups tag_groups.txt --seg-fn-in build/segbits_riob18_processed.rdb --seg-fn-out $@
 	# TODO: This is a hack. See https://github.com/f4pga/prjxray/issues/2073
-	echo 'RIOB18.IOB_Y0.SSTL12_SSTL135_SSTL15.IN !38_126 39_127' >> $@
+	# Use the prefix-less form 'IOB18.' so mergedb.sh's per-side sed (which
+	# rewrites '^IOB18\.' to either 'RIOB18.' or 'LIOB18.') applies to this
+	# manual entry as well. The previous hard-coded 'RIOB18.' would land
+	# verbatim in segbits_liob18.db and bit2fasm would KeyError on the
+	# missing 'LIOB18.IOB_Y0.SSTL12_SSTL135_SSTL15.IN'.
+	echo 'IOB18.IOB_Y0.SSTL12_SSTL135_SSTL15.IN !38_126 39_127' >> $@
 	sort -o $@ $@
-	${XRAY_MASKMERGE} build/mask_riob18.db $$(find -name segdata_riob18.txt)
+	${XRAY_MASKMERGE} build/mask_riob18.db $$(find -name 'segdata_[rl]iob18.txt')
 
 build/segbits_hclk_ioi.rdb: $(SPECIMENS_OK)
 	${XRAY_SEGMATCH} -c 10 -o build/segbits_hclk_ioi.rdb $$(find -name segdata_hclk_ioi.txt)
@@ -37,6 +47,11 @@ build/segbits_hclk_ioi.db: build/segbits_hclk_ioi.rdb
 pushdb:
 	${XRAY_MERGEDB} riob18 build/segbits_riob18.db
 	${XRAY_MERGEDB} mask_riob18 build/mask_riob18.db
+	# Mirror to L-side for parts with HP-bank IOB18 on both sides
+	# (virtex7 xc7vx485tffg1761-2). The same .db content is correct for
+	# LIOB18 because IOB18 tile architecture is symmetric.
+	${XRAY_MERGEDB} liob18 build/segbits_riob18.db
+	${XRAY_MERGEDB} mask_liob18 build/mask_riob18.db
 
 	${XRAY_MERGEDB} hclk_ioi build/segbits_hclk_ioi.db
 

fuzzers/030-iob18/process_rdb.py

@@ -17,6 +17,7 @@ There are couple cases that need to be handled here:
   can be merged to provide unique "(IOSTANDARD, DRIVE)" bit sets.
 """
 import argparse
+import os
 
 
 def get_name(l):
@@ -172,6 +173,14 @@ def process_features_sets(iostandard_lines):
                 if enum is not None:
                     common_groups[site][(bits, group)]['enums'].add(enum)
 
+    # On Virtex-7 some Y1 IN groups differ from their Y0 counterparts by a
+    # single bit (e.g. LVCMOS* sets 39_01 while SSTL* does not), so the
+    # name-harmonisation below must not fold two distinct-bit groups onto one
+    # feature name -- doing so emits duplicate db lines that break dbfixup.
+    # Require identical bits before adopting a visited name for virtex7; other
+    # families never produce two-group Y1 IN splits, so they are unaffected.
+    require_same_bits = os.environ.get('XRAY_DATABASE') == 'virtex7'
+
     visited_iostandards = list()
     for site, groups in common_groups.items():
         for (bits, group), v in groups.items():
@@ -184,17 +193,19 @@ def process_features_sets(iostandard_lines):
             #
             # The following code makes sure that the same set of iostandards
             # (even if not really present at a site location) appears for each site
-            for visited_iostandard, visited_group, visited_enums in visited_iostandards:
+            for visited_iostandard, visited_group, visited_enums, visited_bits in visited_iostandards:
                 same_enum = enums == visited_enums
                 same_group = group == visited_group
                 compatible_iostd = any(
                     x in iostandards for x in visited_iostandard)
                 take_visited_iostd = len(visited_iostandard) > len(iostandards)
-                if same_enum and same_group and compatible_iostd and take_visited_iostd:
+                same_bits = bits == visited_bits
+                if same_enum and same_group and compatible_iostd and take_visited_iostd \
+                        and (same_bits or not require_same_bits):
                     iostandards = visited_iostandard
                     break
 
-            visited_iostandards.append((iostandards, group, enums))
+            visited_iostandards.append((iostandards, group, enums, bits))
 
             iostandards_string = '_'.join(sorted(iostandards))
 

fuzzers/033-mon-xadc/generate.tcl

@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
 
 create_pblock roi
 

fuzzers/034-cmt-pll-pips/generate.tcl

@@ -7,28 +7,10 @@
 # SPDX-License-Identifier: ISC
 source "$::env(XRAY_DIR)/utils/utils.tcl"
 
-proc write_pip_txtdata {filename} {
+# Local write_pip_txtdata override removed — utils.tcl (sourced above)
-    puts "FUZ([pwd]): Writing $filename."
+# has been patched with a bulk-fetch version that is ~4x faster on
-    set fp [open $filename w]
+# xc7vx485tffg1761-2. Keeping this shadow would re-introduce hours of
-    set nets [get_nets -hierarchical]
+# per-net Tcl overhead.
-    set nnets [llength $nets]
-    set neti 0
-    foreach net $nets {
-        incr neti
-        if {($neti % 100) == 0 } {
-            puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)"
-        }
-        foreach pip [get_pips -of_objects $net] {
-            set tile [get_tiles -of_objects $pip]
-            set src_wire [get_wires -uphill -of_objects $pip]
-            set dst_wire [get_wires -downhill -of_objects $pip]
-            set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
-            set dir_prop [get_property IS_DIRECTIONAL $pip]
-            puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
-        }
-    }
-    close $fp
-}
 
 proc write_used_wires {filename} {
     puts "FUZ([pwd]): Writing $filename."

fuzzers/034b-cmt-mmcm-pips/generate.tcl

@@ -7,28 +7,10 @@
 # SPDX-License-Identifier: ISC
 source "$::env(XRAY_DIR)/utils/utils.tcl"
 
-proc write_pip_txtdata {filename} {
+# Local write_pip_txtdata override removed — utils.tcl (sourced above)
-    puts "FUZ([pwd]): Writing $filename."
+# has been patched with a bulk-fetch version that is ~4x faster on
-    set fp [open $filename w]
+# xc7vx485tffg1761-2. Keeping this shadow would re-introduce hours of
-    set nets [get_nets -hierarchical]
+# per-net Tcl overhead.
-    set nnets [llength $nets]
-    set neti 0
-    foreach net $nets {
-        incr neti
-        if {($neti % 100) == 0 } {
-            puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)"
-        }
-        foreach pip [get_pips -of_objects $net] {
-            set tile [get_tiles -of_objects $pip]
-            set src_wire [get_wires -uphill -of_objects $pip]
-            set dst_wire [get_wires -downhill -of_objects $pip]
-            set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
-            set dir_prop [get_property IS_DIRECTIONAL $pip]
-            puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
-        }
-    }
-    close $fp
-}
 
 proc write_used_wires {filename} {
     puts "FUZ([pwd]): Writing $filename."

fuzzers/035-iob-ilogic/Makefile

@@ -39,7 +39,7 @@ pushdb: build/segbits_rioi.db
 	${XRAY_MERGEDB} mask_rioi3 build/mask_xioi3.db
 	${XRAY_MERGEDB} mask_rioi3_tbytesrc build/mask_xioi3.db
 	${XRAY_MERGEDB} mask_rioi3_tbyteterm build/mask_xioi3.db
-ifeq ($(XRAY_DATABASE), $(filter ${XRAY_DATABASE}, kintex7 zynq7))
+ifneq (,$(filter $(XRAY_DATABASE),kintex7 zynq7 virtex7))
 	${XRAY_MERGEDB} rioi build/segbits_rioi.db
 	${XRAY_MERGEDB} rioi_tbytesrc build/segbits_rioi.db
 	${XRAY_MERGEDB} rioi_tbyteterm build/segbits_rioi.db

fuzzers/035-iob18-ilogic/Makefile

@@ -0,0 +1,42 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+#
+# IOB18 (HP-bank) ILOGIC fuzzer for Virtex-7.  The kintex7 035-iob-ilogic
+# fuzzer targets IOB33/HR sites that do not exist on this part, so its LIOI/
+# RIOI results were transplanted.  This variant places ISERDESE2/IDDR on real
+# IOB18 sites on BOTH the L and R columns and measures the ILOGIC config bits
+# (incl. ZINV_D) directly.
+N := 30
+include ../fuzzer.mk
+
+database: build/segbits_iob18_ilogic.db
+
+build/segbits_iob18_ilogic.rdb: $(SPECIMENS_OK)
+	${XRAY_SEGMATCH} -c 6 -o build/segbits_iob18_ilogic.rdb2 $$(find -name segdata_*.txt)
+	# ISERDES features belong to 035b-iob18-iserdes; DYN_* are solved there too.
+	grep -v ".ISERDES." build/segbits_iob18_ilogic.rdb2 | grep -v "DYN_" >$@
+
+build/segbits_iob18_ilogic.db: build/segbits_iob18_ilogic.rdb
+	${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --groups tag_groups.txt --seg-fn-in $^ --seg-fn-out $@
+	${XRAY_MASKMERGE} build/mask_iob18_ilogic.db $$(find -name segdata_*.txt)
+
+pushdb:
+	${XRAY_MERGEDB} lioi build/segbits_iob18_ilogic.db
+	${XRAY_MERGEDB} lioi_tbytesrc build/segbits_iob18_ilogic.db
+	${XRAY_MERGEDB} lioi_tbyteterm build/segbits_iob18_ilogic.db
+	${XRAY_MERGEDB} rioi build/segbits_iob18_ilogic.db
+	${XRAY_MERGEDB} rioi_tbytesrc build/segbits_iob18_ilogic.db
+	${XRAY_MERGEDB} rioi_tbyteterm build/segbits_iob18_ilogic.db
+	${XRAY_MERGEDB} mask_lioi build/mask_iob18_ilogic.db
+	${XRAY_MERGEDB} mask_lioi_tbytesrc build/mask_iob18_ilogic.db
+	${XRAY_MERGEDB} mask_lioi_tbyteterm build/mask_iob18_ilogic.db
+	${XRAY_MERGEDB} mask_rioi build/mask_iob18_ilogic.db
+	${XRAY_MERGEDB} mask_rioi_tbytesrc build/mask_iob18_ilogic.db
+	${XRAY_MERGEDB} mask_rioi_tbyteterm build/mask_iob18_ilogic.db
+
+.PHONY: database pushdb

fuzzers/035-iob18-ilogic/generate.py

@@ -0,0 +1,259 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+from prjxray.segmaker import Segmaker
+from prjxray import verilog
+import json
+
+# Set to true to enable additional tags useful for tracing bit toggles.
+DEBUG_FUZZER = False
+
+
+def bitfilter(frame, word):
+    if frame < 25 or frame > 31:
+        return False
+
+    return True
+
+
+def handle_data_width(segmk, d):
+    if 'DATA_WIDTH' not in d:
+        return
+
+    site = d['ilogic_loc']
+
+    # It appears several widths end up with the same bitstream pattern.
+    # This groups those widths together for documentation.
+    widths = [
+        [2],
+        [3],
+        [4, 6],
+        [5, 7],
+        [8],
+        [10],
+        [14],
+    ]
+
+    width_map = {}
+
+    for ws in widths:
+        for w in ws:
+            width_map[w] = 'W{}'.format('_'.join(map(str, ws)))
+
+    zero_opt = 2
+    W_OPT_ZERO = width_map[zero_opt]
+    if d['DATA_WIDTH'] == zero_opt:
+        segmk.add_site_tag(site, 'ISERDES.DATA_WIDTH.{}'.format(W_OPT_ZERO), 1)
+
+        for opt in width_map.values():
+            if opt == W_OPT_ZERO:
+                continue
+
+            segmk.add_site_tag(site, 'ISERDES.DATA_WIDTH.{}'.format(opt), 0)
+    else:
+        w_opt = width_map[d['DATA_WIDTH']]
+        if w_opt != W_OPT_ZERO:
+            segmk.add_site_tag(
+                site, 'ISERDES.DATA_WIDTH.{}'.format(W_OPT_ZERO), 0)
+            segmk.add_site_tag(site, 'ISERDES.DATA_WIDTH.{}'.format(w_opt), 1)
+
+
+def handle_data_rate(segmk, d):
+    if 'DATA_WIDTH' not in d:
+        return
+
+    site = d['ilogic_loc']
+
+    for opt in ['SDR', 'DDR']:
+        segmk.add_site_tag(
+            site, 'ISERDES.DATA_RATE.{}'.format(opt),
+            verilog.unquote(d['DATA_RATE']) == opt)
+
+
+def main():
+    print("Loading tags")
+    segmk = Segmaker("design.bits")
+
+    with open('params.jl', 'r') as f:
+        design = json.load(f)
+
+        for d in design:
+            site = d['ilogic_loc']
+
+            handle_data_width(segmk, d)
+            handle_data_rate(segmk, d)
+
+            segmk.add_site_tag(site, 'ISERDES.IN_USE', d['use_iserdese2'])
+
+            if 'NUM_CE' in d:
+                segmk.add_site_tag(site, 'ISERDES.NUM_CE.N2', d['NUM_CE'] == 2)
+
+            segmk.add_site_tag(
+                site, 'IDDR_OR_ISERDES.IN_USE', d['use_iserdese2']
+                or d['iddr_mux_config'] != 'none')
+
+            if 'INTERFACE_TYPE' in d:
+                for opt in (
+                        'MEMORY',
+                        'MEMORY_DDR3',
+                        'MEMORY_QDR',
+                        'NETWORKING',
+                        'OVERSAMPLE',
+                ):
+                    segmk.add_site_tag(
+                        site, 'ISERDES.INTERFACE_TYPE.{}'.format(opt),
+                        opt == verilog.unquote(d['INTERFACE_TYPE']))
+                    segmk.add_site_tag(
+                        site, 'ISERDES.INTERFACE_TYPE.Z_{}'.format(opt),
+                        opt != verilog.unquote(d['INTERFACE_TYPE']))
+
+                segmk.add_site_tag(
+                    site, 'ISERDES.INTERFACE_TYPE.NOT_MEMORY',
+                    'MEMORY' not in verilog.unquote(d['INTERFACE_TYPE']))
+
+            if d['iddr_mux_config'] != 'none':
+                segmk.add_site_tag(site, 'IFF.ZINIT_Q1', not d['INIT_Q1'])
+                segmk.add_site_tag(site, 'IFF.ZINIT_Q2', not d['INIT_Q2'])
+
+                if 'DYN_CLKDIV_INV_EN' in d:
+                    segmk.add_site_tag(
+                        site, 'DYN_CLKDIV_INV_EN',
+                        verilog.unquote(d['DYN_CLKDIV_INV_EN']) == 'TRUE')
+
+                if 'DYN_CLK_INV_EN' in d:
+                    segmk.add_site_tag(
+                        site, 'DYN_CLK_INV_EN',
+                        verilog.unquote(d['DYN_CLK_INV_EN']) == 'TRUE')
+
+                if 'INIT_Q3' in d:
+                    segmk.add_site_tag(site, 'IFF.ZINIT_Q3', not d['INIT_Q3'])
+                    segmk.add_site_tag(site, 'IFF.ZINIT_Q4', not d['INIT_Q4'])
+                    segmk.add_site_tag(
+                        site, 'IFF.ZSRVAL_Q1', not d['SRVAL_Q1'])
+                    segmk.add_site_tag(
+                        site, 'IFF.ZSRVAL_Q2', not d['SRVAL_Q2'])
+                    segmk.add_site_tag(
+                        site, 'IFF.ZSRVAL_Q3', not d['SRVAL_Q3'])
+                    segmk.add_site_tag(
+                        site, 'IFF.ZSRVAL_Q4', not d['SRVAL_Q4'])
+
+                if 'IS_CLK_INVERTED' in d and not d['DISABLE_CLOCKS']:
+                    if verilog.unquote(d['INTERFACE_TYPE']) == 'MEMORY_DDR3':
+                        segmk.add_site_tag(
+                            site, 'IFF.INV_CLK', d['IS_CLK_INVERTED'])
+                        segmk.add_site_tag(
+                            site, 'IFF.INV_CLKB', d['IS_CLKB_INVERTED'])
+                        segmk.add_site_tag(
+                            site, 'IFF.ZINV_CLK', not d['IS_CLK_INVERTED'])
+                        segmk.add_site_tag(
+                            site, 'IFF.ZINV_CLKB', not d['IS_CLKB_INVERTED'])
+
+                        segmk.add_site_tag(
+                            site, 'IFF.ZINV_CLK_XOR',
+                            d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED'])
+                        segmk.add_site_tag(
+                            site, 'IFF.ZINV_CLK_NXOR',
+                            not (d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED']))
+
+                        segmk.add_site_tag(
+                            site, 'IFF.ZINV_CLK_OR', d['IS_CLK_INVERTED']
+                            or d['IS_CLKB_INVERTED'])
+                        segmk.add_site_tag(
+                            site, 'IFF.ZINV_CLK_NOR', not (
+                                d['IS_CLK_INVERTED'] or d['IS_CLKB_INVERTED']))
+                        segmk.add_site_tag(
+                            site, 'IFF.ZINV_CLK_AND', d['IS_CLK_INVERTED']
+                            and d['IS_CLKB_INVERTED'])
+                        segmk.add_site_tag(
+                            site, 'IFF.ZINV_CLK_NAND', not (
+                                d['IS_CLK_INVERTED']
+                                and d['IS_CLKB_INVERTED']))
+
+                if 'IS_OCLK_INVERTED' in d and not d['DISABLE_CLOCKS']:
+                    segmk.add_site_tag(
+                        site, 'IFF.INV_OCLK', d['IS_OCLK_INVERTED'])
+                    segmk.add_site_tag(
+                        site, 'IFF.ZINV_OCLK', not d['IS_OCLK_INVERTED'])
+                    segmk.add_site_tag(
+                        site, 'IFF.INV_OCLKB', d['IS_OCLKB_INVERTED'])
+                    segmk.add_site_tag(
+                        site, 'IFF.ZINV_OCLKB', not d['IS_OCLKB_INVERTED'])
+
+                if 'IS_CLKDIV_INVERTED' in d and not d['DISABLE_CLOCKS'] and \
+                    verilog.unquote(d['INTERFACE_TYPE']) == 'MEMORY':
+                    segmk.add_site_tag(
+                        site, 'IFF.INV_CLKDIV', d['IS_CLKDIV_INVERTED'])
+                    segmk.add_site_tag(
+                        site, 'IFF.ZINV_CLKDIV', not d['IS_CLKDIV_INVERTED'])
+
+                if 'IS_C_INVERTED' in d:
+                    segmk.add_site_tag(
+                        site, 'IFF.ZINV_C', not d['IS_C_INVERTED'])
+
+                segmk.add_site_tag(site, 'ZINV_D', not d['IS_D_INVERTED'])
+
+                if 'SRTYPE' in d:
+                    for opt in ['ASYNC', 'SYNC']:
+                        segmk.add_site_tag(
+                            site, 'IFF.SRTYPE.{}'.format(opt),
+                            verilog.unquote(d['SRTYPE']) == opt)
+
+                if 'DDR_CLK_EDGE' in d:
+                    for opt in ['OPPOSITE_EDGE', 'SAME_EDGE',
+                                'SAME_EDGE_PIPELINED']:
+                        segmk.add_site_tag(
+                            site, 'IFF.DDR_CLK_EDGE.{}'.format(opt),
+                            verilog.unquote(d['DDR_CLK_EDGE']) == opt)
+
+            if d['iddr_mux_config'] == 'direct':
+                segmk.add_site_tag(site, 'IFFDELMUXE3.P0', 0)
+                segmk.add_site_tag(site, 'IFFDELMUXE3.P1', 1)
+                segmk.add_site_tag(site, 'IFFDELMUXE3.P2', 0)
+            elif d['iddr_mux_config'] == 'idelay':
+                segmk.add_site_tag(site, 'IFFDELMUXE3.P0', 1)
+                segmk.add_site_tag(site, 'IFFDELMUXE3.P1', 0)
+                segmk.add_site_tag(site, 'IFFDELMUXE3.P2', 0)
+            elif d['iddr_mux_config'] == 'none':
+                segmk.add_site_tag(site, 'IFFDELMUXE3.P0', 0)
+                segmk.add_site_tag(site, 'IFFDELMUXE3.P1', 0)
+                segmk.add_site_tag(site, 'IFFDELMUXE3.P2', 0)
+            else:
+                assert False, d['mux_config']
+
+            if d['mux_config'] == 'direct':
+                segmk.add_site_tag(site, 'IDELMUXE3.P0', 0)
+                segmk.add_site_tag(site, 'IDELMUXE3.P1', 1)
+                segmk.add_site_tag(site, 'IDELMUXE3.P2', 0)
+
+            elif d['mux_config'] == 'idelay':
+                segmk.add_site_tag(site, 'IDELMUXE3.P0', 1)
+                segmk.add_site_tag(site, 'IDELMUXE3.P1', 0)
+                segmk.add_site_tag(site, 'IDELMUXE3.P2', 0)
+
+            elif d['mux_config'] == 'none':
+                segmk.add_site_tag(site, 'IDELMUXE3.P0', 0)
+                segmk.add_site_tag(site, 'IDELMUXE3.P1', 0)
+                segmk.add_site_tag(site, 'IDELMUXE3.P2', 0)
+            else:
+                assert False, d['mux_config']
+
+            if DEBUG_FUZZER:
+                for k in d:
+                    segmk.add_site_tag(
+                        site, 'param_' + k + '_' + str(d[k]).replace(
+                            ' ', '').replace('\n', ''), 1)
+
+    segmk.compile(bitfilter=bitfilter)
+    segmk.write(allow_empty=True)
+
+
+if __name__ == "__main__":
+    main()

fuzzers/035-iob18-ilogic/generate.tcl

@@ -0,0 +1,39 @@
+# Copyright (C) 2017-2022  The Project X-Ray Authors
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+create_project -force -part $::env(XRAY_PART) design design
+read_verilog top.v
+synth_design -top top
+
+set_property CFGBVS GND [current_design]
+set_property CONFIG_VOLTAGE 1.8 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
+
+set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
+set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-79}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-81}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-84}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-85}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-87}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-85}]
+set_property IS_ENABLED 0 [get_drc_checks {AVAL-28}]
+# ISERDES/ILOGIC fuzzer deliberately builds "invalid" clocking and D-inversion
+# mux configs to observe their bits; suppress the DRCs that would block bitgen.
+set_property IS_ENABLED 0 [get_drc_checks {REQP-105}]
+set_property IS_ENABLED 0 [get_drc_checks {PDRC-26}]
+set_property IS_ENABLED 0 [get_drc_checks {PDRC-158}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-1580}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-1581}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-1582}]
+
+place_design
+route_design
+
+write_checkpoint -force design.dcp
+write_bitstream -force design.bit

fuzzers/035-iob18-ilogic/params.csv

@@ -0,0 +1,672 @@
+tile,site,pin,iostandard,drive,slew
+LIOB18_X81Y10,IOB_X0Y10,dio[0],LVCMOS18,6,FAST,PULLDOWN
+LIOB18_X81Y101,IOB_X0Y97,dio[1],LVCMOS18,6,FAST,PULLUP
+LIOB18_X81Y101,IOB_X0Y98,dio[2],LVCMOS18,4,FAST,PULLDOWN
+LIOB18_X81Y106,IOB_X0Y101,dio[3],LVCMOS18,6,FAST,KEEPER
+LIOB18_X81Y106,IOB_X0Y102,dio[4],LVCMOS18,6,FAST,PULLDOWN
+LIOB18_X81Y108,IOB_X0Y103,dio[5],LVCMOS18,2,SLOW,KEEPER
+LIOB18_X81Y108,IOB_X0Y104,dio[6],LVCMOS18,16,FAST,PULLUP
+LIOB18_X81Y110,IOB_X0Y105,dio[7],LVCMOS18,16,SLOW,NONE
+LIOB18_X81Y110,IOB_X0Y106,dio[8],LVCMOS18,2,FAST,PULLUP
+LIOB18_X81Y112,IOB_X0Y107,dio[9],LVCMOS18,6,SLOW,PULLDOWN
+LIOB18_X81Y112,IOB_X0Y108,dio[10],LVCMOS18,4,SLOW,NONE
+LIOB18_X81Y114,IOB_X0Y109,dio[11],LVCMOS18,16,SLOW,PULLDOWN
+LIOB18_X81Y114,IOB_X0Y110,dio[12],LVCMOS18,6,FAST,KEEPER
+LIOB18_X81Y116,IOB_X0Y111,dio[13],LVCMOS18,8,FAST,NONE
+LIOB18_X81Y116,IOB_X0Y112,dio[14],LVCMOS18,8,FAST,PULLUP
+LIOB18_X81Y118,IOB_X0Y113,dio[15],LVCMOS18,12,SLOW,PULLUP
+LIOB18_X81Y118,IOB_X0Y114,dio[16],LVCMOS18,6,FAST,NONE
+LIOB18_X81Y12,IOB_X0Y11,dio[17],LVCMOS18,6,FAST,NONE
+LIOB18_X81Y12,IOB_X0Y12,dio[18],LVCMOS18,8,FAST,PULLUP
+LIOB18_X81Y120,IOB_X0Y115,dio[19],LVCMOS18,16,FAST,KEEPER
+LIOB18_X81Y120,IOB_X0Y116,dio[20],LVCMOS18,6,SLOW,KEEPER
+LIOB18_X81Y122,IOB_X0Y117,dio[21],LVCMOS18,6,FAST,KEEPER
+LIOB18_X81Y122,IOB_X0Y118,dio[22],LVCMOS18,2,FAST,NONE
+LIOB18_X81Y124,IOB_X0Y119,dio[23],LVCMOS18,12,SLOW,PULLDOWN
+LIOB18_X81Y124,IOB_X0Y120,dio[24],LVCMOS18,12,SLOW,PULLUP
+LIOB18_X81Y126,IOB_X0Y121,dio[25],LVCMOS18,8,FAST,PULLUP
+LIOB18_X81Y126,IOB_X0Y122,dio[26],LVCMOS18,2,SLOW,PULLUP
+LIOB18_X81Y128,IOB_X0Y123,dio[27],LVCMOS18,2,FAST,NONE
+LIOB18_X81Y128,IOB_X0Y124,dio[28],LVCMOS18,16,FAST,PULLUP
+LIOB18_X81Y131,IOB_X0Y125,dio[29],LVCMOS18,6,SLOW,PULLDOWN
+LIOB18_X81Y131,IOB_X0Y126,dio[30],LVCMOS18,2,SLOW,PULLUP
+LIOB18_X81Y133,IOB_X0Y127,dio[31],LVCMOS18,8,FAST,KEEPER
+LIOB18_X81Y133,IOB_X0Y128,dio[32],LVCMOS18,16,FAST,NONE
+LIOB18_X81Y135,IOB_X0Y129,dio[33],LVCMOS18,4,FAST,NONE
+LIOB18_X81Y135,IOB_X0Y130,dio[34],LVCMOS18,4,FAST,NONE
+LIOB18_X81Y137,IOB_X0Y131,dio[35],LVCMOS18,16,SLOW,PULLDOWN
+LIOB18_X81Y137,IOB_X0Y132,dio[36],LVCMOS18,4,FAST,NONE
+LIOB18_X81Y139,IOB_X0Y133,dio[37],LVCMOS18,12,SLOW,KEEPER
+LIOB18_X81Y139,IOB_X0Y134,dio[38],LVCMOS18,4,SLOW,NONE
+LIOB18_X81Y14,IOB_X0Y13,dio[39],LVCMOS18,8,SLOW,PULLUP
+LIOB18_X81Y14,IOB_X0Y14,dio[40],LVCMOS18,4,FAST,KEEPER
+LIOB18_X81Y141,IOB_X0Y135,dio[41],LVCMOS18,16,SLOW,PULLDOWN
+LIOB18_X81Y141,IOB_X0Y136,dio[42],LVCMOS18,6,FAST,PULLUP
+LIOB18_X81Y143,IOB_X0Y137,dio[43],LVCMOS18,12,SLOW,KEEPER
+LIOB18_X81Y143,IOB_X0Y138,dio[44],LVCMOS18,4,FAST,PULLDOWN
+LIOB18_X81Y145,IOB_X0Y139,dio[45],LVCMOS18,8,SLOW,PULLDOWN
+LIOB18_X81Y145,IOB_X0Y140,dio[46],LVCMOS18,2,FAST,NONE
+LIOB18_X81Y147,IOB_X0Y141,dio[47],LVCMOS18,2,SLOW,NONE
+LIOB18_X81Y147,IOB_X0Y142,dio[48],LVCMOS18,8,SLOW,PULLUP
+LIOB18_X81Y149,IOB_X0Y143,dio[49],LVCMOS18,16,FAST,PULLDOWN
+LIOB18_X81Y149,IOB_X0Y144,dio[50],LVCMOS18,4,FAST,PULLDOWN
+LIOB18_X81Y151,IOB_X0Y145,dio[51],LVCMOS18,6,FAST,KEEPER
+LIOB18_X81Y151,IOB_X0Y146,dio[52],LVCMOS18,12,SLOW,NONE
+LIOB18_X81Y153,IOB_X0Y147,dio[53],LVCMOS18,4,FAST,KEEPER
+LIOB18_X81Y153,IOB_X0Y148,dio[54],LVCMOS18,16,SLOW,PULLDOWN
+LIOB18_X81Y158,IOB_X0Y151,dio[55],LVCMOS18,16,SLOW,NONE
+LIOB18_X81Y158,IOB_X0Y152,dio[56],LVCMOS18,4,SLOW,NONE
+LIOB18_X81Y16,IOB_X0Y15,dio[57],LVCMOS18,8,SLOW,KEEPER
+LIOB18_X81Y16,IOB_X0Y16,dio[58],LVCMOS18,12,SLOW,NONE
+LIOB18_X81Y160,IOB_X0Y153,dio[59],LVCMOS18,2,FAST,PULLUP
+LIOB18_X81Y160,IOB_X0Y154,dio[60],LVCMOS18,6,FAST,KEEPER
+LIOB18_X81Y162,IOB_X0Y155,dio[61],LVCMOS18,4,FAST,NONE
+LIOB18_X81Y162,IOB_X0Y156,dio[62],LVCMOS18,6,SLOW,PULLUP
+LIOB18_X81Y164,IOB_X0Y157,dio[63],LVCMOS18,4,FAST,NONE
+LIOB18_X81Y164,IOB_X0Y158,dio[64],LVCMOS18,2,FAST,PULLDOWN
+LIOB18_X81Y166,IOB_X0Y159,dio[65],LVCMOS18,4,FAST,NONE
+LIOB18_X81Y166,IOB_X0Y160,dio[66],LVCMOS18,16,SLOW,NONE
+LIOB18_X81Y168,IOB_X0Y161,dio[67],LVCMOS18,6,SLOW,NONE
+LIOB18_X81Y168,IOB_X0Y162,dio[68],LVCMOS18,4,SLOW,KEEPER
+LIOB18_X81Y170,IOB_X0Y163,dio[69],LVCMOS18,12,FAST,PULLUP
+LIOB18_X81Y170,IOB_X0Y164,dio[70],LVCMOS18,2,SLOW,NONE
+LIOB18_X81Y172,IOB_X0Y165,dio[71],LVCMOS18,12,FAST,PULLUP
+LIOB18_X81Y172,IOB_X0Y166,dio[72],LVCMOS18,8,SLOW,NONE
+LIOB18_X81Y174,IOB_X0Y167,dio[73],LVCMOS18,8,FAST,PULLDOWN
+LIOB18_X81Y174,IOB_X0Y168,dio[74],LVCMOS18,8,FAST,PULLUP
+LIOB18_X81Y176,IOB_X0Y169,dio[75],LVCMOS18,16,FAST,PULLUP
+LIOB18_X81Y176,IOB_X0Y170,dio[76],LVCMOS18,4,FAST,NONE
+LIOB18_X81Y178,IOB_X0Y171,dio[77],LVCMOS18,8,SLOW,NONE
+LIOB18_X81Y178,IOB_X0Y172,dio[78],LVCMOS18,12,SLOW,PULLDOWN
+LIOB18_X81Y18,IOB_X0Y17,dio[79],LVCMOS18,12,FAST,PULLUP
+LIOB18_X81Y18,IOB_X0Y18,dio[80],LVCMOS18,2,FAST,KEEPER
+LIOB18_X81Y180,IOB_X0Y173,dio[81],LVCMOS18,8,SLOW,PULLUP
+LIOB18_X81Y180,IOB_X0Y174,dio[82],LVCMOS18,16,SLOW,PULLDOWN
+LIOB18_X81Y183,IOB_X0Y175,dio[83],LVCMOS18,6,SLOW,PULLDOWN
+LIOB18_X81Y183,IOB_X0Y176,dio[84],LVCMOS18,8,FAST,PULLDOWN
+LIOB18_X81Y185,IOB_X0Y177,dio[85],LVCMOS18,2,SLOW,NONE
+LIOB18_X81Y185,IOB_X0Y178,dio[86],LVCMOS18,8,SLOW,PULLUP
+LIOB18_X81Y187,IOB_X0Y179,dio[87],LVCMOS18,8,FAST,NONE
+LIOB18_X81Y187,IOB_X0Y180,dio[88],LVCMOS18,16,SLOW,KEEPER
+LIOB18_X81Y189,IOB_X0Y181,dio[89],LVCMOS18,16,SLOW,PULLUP
+LIOB18_X81Y189,IOB_X0Y182,dio[90],LVCMOS18,6,FAST,NONE
+LIOB18_X81Y191,IOB_X0Y183,dio[91],LVCMOS18,4,SLOW,KEEPER
+LIOB18_X81Y191,IOB_X0Y184,dio[92],LVCMOS18,16,SLOW,NONE
+LIOB18_X81Y193,IOB_X0Y185,dio[93],LVCMOS18,2,SLOW,KEEPER
+LIOB18_X81Y193,IOB_X0Y186,dio[94],LVCMOS18,6,SLOW,PULLUP
+LIOB18_X81Y195,IOB_X0Y187,dio[95],LVCMOS18,6,SLOW,PULLUP
+LIOB18_X81Y195,IOB_X0Y188,dio[96],LVCMOS18,4,SLOW,KEEPER
+LIOB18_X81Y197,IOB_X0Y189,dio[97],LVCMOS18,8,SLOW,PULLUP
+LIOB18_X81Y197,IOB_X0Y190,dio[98],LVCMOS18,6,SLOW,PULLDOWN
+LIOB18_X81Y199,IOB_X0Y191,dio[99],LVCMOS18,8,SLOW,NONE
+LIOB18_X81Y199,IOB_X0Y192,dio[100],LVCMOS18,2,FAST,KEEPER
+LIOB18_X81Y2,IOB_X0Y1,dio[101],LVCMOS18,12,SLOW,PULLDOWN
+LIOB18_X81Y2,IOB_X0Y2,dio[102],LVCMOS18,6,SLOW,NONE
+LIOB18_X81Y20,IOB_X0Y19,dio[103],LVCMOS18,6,SLOW,KEEPER
+LIOB18_X81Y20,IOB_X0Y20,dio[104],LVCMOS18,6,FAST,PULLUP
+LIOB18_X81Y201,IOB_X0Y193,dio[105],LVCMOS18,6,FAST,NONE
+LIOB18_X81Y201,IOB_X0Y194,dio[106],LVCMOS18,2,SLOW,PULLDOWN
+LIOB18_X81Y203,IOB_X0Y195,dio[107],LVCMOS18,2,SLOW,PULLDOWN
+LIOB18_X81Y203,IOB_X0Y196,dio[108],LVCMOS18,2,SLOW,NONE
+LIOB18_X81Y205,IOB_X0Y197,dio[109],LVCMOS18,12,SLOW,NONE
+LIOB18_X81Y205,IOB_X0Y198,dio[110],LVCMOS18,16,FAST,PULLUP
+LIOB18_X81Y210,IOB_X0Y201,dio[111],LVCMOS18,8,SLOW,KEEPER
+LIOB18_X81Y210,IOB_X0Y202,dio[112],LVCMOS18,12,FAST,KEEPER
+LIOB18_X81Y212,IOB_X0Y203,dio[113],LVCMOS18,6,FAST,KEEPER
+LIOB18_X81Y212,IOB_X0Y204,dio[114],LVCMOS18,6,SLOW,NONE
+LIOB18_X81Y214,IOB_X0Y205,dio[115],LVCMOS18,12,SLOW,PULLUP
+LIOB18_X81Y214,IOB_X0Y206,dio[116],LVCMOS18,2,FAST,KEEPER
+LIOB18_X81Y216,IOB_X0Y207,dio[117],LVCMOS18,6,SLOW,KEEPER
+LIOB18_X81Y216,IOB_X0Y208,dio[118],LVCMOS18,6,FAST,PULLDOWN
+LIOB18_X81Y218,IOB_X0Y209,dio[119],LVCMOS18,12,SLOW,PULLUP
+LIOB18_X81Y218,IOB_X0Y210,dio[120],LVCMOS18,4,SLOW,PULLUP
+LIOB18_X81Y22,IOB_X0Y21,dio[121],LVCMOS18,8,SLOW,PULLDOWN
+LIOB18_X81Y22,IOB_X0Y22,dio[122],LVCMOS18,16,FAST,KEEPER
+LIOB18_X81Y220,IOB_X0Y211,dio[123],LVCMOS18,12,SLOW,PULLUP
+LIOB18_X81Y220,IOB_X0Y212,dio[124],LVCMOS18,2,FAST,KEEPER
+LIOB18_X81Y222,IOB_X0Y213,dio[125],LVCMOS18,12,FAST,PULLDOWN
+LIOB18_X81Y222,IOB_X0Y214,dio[126],LVCMOS18,2,SLOW,PULLDOWN
+LIOB18_X81Y224,IOB_X0Y215,dio[127],LVCMOS18,4,SLOW,PULLUP
+LIOB18_X81Y224,IOB_X0Y216,dio[128],LVCMOS18,6,FAST,NONE
+LIOB18_X81Y226,IOB_X0Y217,dio[129],LVCMOS18,8,FAST,PULLDOWN
+LIOB18_X81Y226,IOB_X0Y218,dio[130],LVCMOS18,2,FAST,KEEPER
+LIOB18_X81Y228,IOB_X0Y219,dio[131],LVCMOS18,2,FAST,KEEPER
+LIOB18_X81Y228,IOB_X0Y220,dio[132],LVCMOS18,6,SLOW,PULLUP
+LIOB18_X81Y230,IOB_X0Y221,dio[133],LVCMOS18,2,SLOW,KEEPER
+LIOB18_X81Y230,IOB_X0Y222,dio[134],LVCMOS18,16,FAST,PULLDOWN
+LIOB18_X81Y232,IOB_X0Y223,dio[135],LVCMOS18,8,FAST,PULLUP
+LIOB18_X81Y232,IOB_X0Y224,dio[136],LVCMOS18,6,SLOW,NONE
+LIOB18_X81Y235,IOB_X0Y225,dio[137],LVCMOS18,16,SLOW,PULLUP
+LIOB18_X81Y235,IOB_X0Y226,dio[138],LVCMOS18,8,FAST,KEEPER
+LIOB18_X81Y237,IOB_X0Y227,dio[139],LVCMOS18,6,FAST,PULLUP
+LIOB18_X81Y237,IOB_X0Y228,dio[140],LVCMOS18,16,SLOW,PULLDOWN
+LIOB18_X81Y239,IOB_X0Y229,dio[141],LVCMOS18,12,FAST,PULLDOWN
+LIOB18_X81Y239,IOB_X0Y230,dio[142],LVCMOS18,16,FAST,PULLUP
+LIOB18_X81Y24,IOB_X0Y23,dio[143],LVCMOS18,4,SLOW,KEEPER
+LIOB18_X81Y24,IOB_X0Y24,dio[144],LVCMOS18,12,SLOW,KEEPER
+LIOB18_X81Y241,IOB_X0Y231,dio[145],LVCMOS18,12,SLOW,NONE
+LIOB18_X81Y241,IOB_X0Y232,dio[146],LVCMOS18,16,FAST,KEEPER
+LIOB18_X81Y243,IOB_X0Y233,dio[147],LVCMOS18,12,SLOW,NONE
+LIOB18_X81Y243,IOB_X0Y234,dio[148],LVCMOS18,8,SLOW,PULLDOWN
+LIOB18_X81Y245,IOB_X0Y235,dio[149],LVCMOS18,12,SLOW,PULLUP
+LIOB18_X81Y245,IOB_X0Y236,dio[150],LVCMOS18,8,SLOW,PULLUP
+LIOB18_X81Y247,IOB_X0Y237,dio[151],LVCMOS18,8,FAST,KEEPER
+LIOB18_X81Y247,IOB_X0Y238,dio[152],LVCMOS18,2,FAST,PULLDOWN
+LIOB18_X81Y249,IOB_X0Y239,dio[153],LVCMOS18,2,SLOW,KEEPER
+LIOB18_X81Y249,IOB_X0Y240,dio[154],LVCMOS18,16,SLOW,NONE
+LIOB18_X81Y251,IOB_X0Y241,dio[155],LVCMOS18,8,SLOW,KEEPER
+LIOB18_X81Y251,IOB_X0Y242,dio[156],LVCMOS18,12,SLOW,KEEPER
+LIOB18_X81Y253,IOB_X0Y243,dio[157],LVCMOS18,2,FAST,PULLUP
+LIOB18_X81Y253,IOB_X0Y244,dio[158],LVCMOS18,16,FAST,PULLUP
+LIOB18_X81Y255,IOB_X0Y245,dio[159],LVCMOS18,4,SLOW,NONE
+LIOB18_X81Y255,IOB_X0Y246,dio[160],LVCMOS18,16,SLOW,PULLUP
+LIOB18_X81Y257,IOB_X0Y247,dio[161],LVCMOS18,6,FAST,PULLDOWN
+LIOB18_X81Y257,IOB_X0Y248,dio[162],LVCMOS18,12,SLOW,PULLDOWN
+LIOB18_X81Y262,IOB_X0Y251,dio[163],LVCMOS18,16,SLOW,PULLUP
+LIOB18_X81Y262,IOB_X0Y252,dio[164],LVCMOS18,6,SLOW,NONE
+LIOB18_X81Y264,IOB_X0Y253,dio[165],LVCMOS18,12,SLOW,PULLUP
+LIOB18_X81Y264,IOB_X0Y254,dio[166],LVCMOS18,6,SLOW,NONE
+LIOB18_X81Y266,IOB_X0Y255,dio[167],LVCMOS18,6,FAST,KEEPER
+LIOB18_X81Y266,IOB_X0Y256,dio[168],LVCMOS18,4,SLOW,PULLUP
+LIOB18_X81Y268,IOB_X0Y257,dio[169],LVCMOS18,8,FAST,KEEPER
+LIOB18_X81Y268,IOB_X0Y258,dio[170],LVCMOS18,6,FAST,PULLDOWN
+LIOB18_X81Y27,IOB_X0Y25,dio[171],LVCMOS18,8,FAST,NONE
+LIOB18_X81Y27,IOB_X0Y26,dio[172],LVCMOS18,8,FAST,NONE
+LIOB18_X81Y270,IOB_X0Y259,dio[173],LVCMOS18,12,FAST,NONE
+LIOB18_X81Y270,IOB_X0Y260,dio[174],LVCMOS18,8,SLOW,PULLUP
+LIOB18_X81Y272,IOB_X0Y261,dio[175],LVCMOS18,12,SLOW,NONE
+LIOB18_X81Y272,IOB_X0Y262,dio[176],LVCMOS18,12,FAST,KEEPER
+LIOB18_X81Y274,IOB_X0Y263,dio[177],LVCMOS18,12,FAST,PULLUP
+LIOB18_X81Y274,IOB_X0Y264,dio[178],LVCMOS18,2,SLOW,PULLDOWN
+LIOB18_X81Y276,IOB_X0Y265,dio[179],LVCMOS18,2,FAST,KEEPER
+LIOB18_X81Y276,IOB_X0Y266,dio[180],LVCMOS18,6,FAST,NONE
+LIOB18_X81Y278,IOB_X0Y267,dio[181],LVCMOS18,6,SLOW,PULLDOWN
+LIOB18_X81Y278,IOB_X0Y268,dio[182],LVCMOS18,4,FAST,PULLDOWN
+LIOB18_X81Y280,IOB_X0Y269,dio[183],LVCMOS18,16,FAST,PULLUP
+LIOB18_X81Y280,IOB_X0Y270,dio[184],LVCMOS18,12,FAST,PULLDOWN
+LIOB18_X81Y282,IOB_X0Y271,dio[185],LVCMOS18,6,FAST,KEEPER
+LIOB18_X81Y282,IOB_X0Y272,dio[186],LVCMOS18,2,SLOW,KEEPER
+LIOB18_X81Y284,IOB_X0Y273,dio[187],LVCMOS18,12,SLOW,PULLDOWN
+LIOB18_X81Y284,IOB_X0Y274,dio[188],LVCMOS18,2,SLOW,KEEPER
+LIOB18_X81Y287,IOB_X0Y275,dio[189],LVCMOS18,4,FAST,PULLDOWN
+LIOB18_X81Y287,IOB_X0Y276,dio[190],LVCMOS18,8,SLOW,KEEPER
+LIOB18_X81Y289,IOB_X0Y277,dio[191],LVCMOS18,8,FAST,KEEPER
+LIOB18_X81Y289,IOB_X0Y278,dio[192],LVCMOS18,2,FAST,PULLDOWN
+LIOB18_X81Y29,IOB_X0Y27,dio[193],LVCMOS18,16,SLOW,PULLUP
+LIOB18_X81Y29,IOB_X0Y28,dio[194],LVCMOS18,16,FAST,NONE
+LIOB18_X81Y291,IOB_X0Y279,dio[195],LVCMOS18,2,FAST,NONE
+LIOB18_X81Y291,IOB_X0Y280,dio[196],LVCMOS18,12,SLOW,KEEPER
+LIOB18_X81Y293,IOB_X0Y281,dio[197],LVCMOS18,8,FAST,NONE
+LIOB18_X81Y293,IOB_X0Y282,dio[198],LVCMOS18,16,FAST,PULLUP
+LIOB18_X81Y295,IOB_X0Y283,dio[199],LVCMOS18,4,SLOW,KEEPER
+LIOB18_X81Y295,IOB_X0Y284,dio[200],LVCMOS18,12,SLOW,KEEPER
+LIOB18_X81Y297,IOB_X0Y285,dio[201],LVCMOS18,12,FAST,PULLUP
+LIOB18_X81Y297,IOB_X0Y286,dio[202],LVCMOS18,2,FAST,NONE
+LIOB18_X81Y299,IOB_X0Y287,dio[203],LVCMOS18,16,SLOW,PULLUP
+LIOB18_X81Y299,IOB_X0Y288,dio[204],LVCMOS18,12,SLOW,PULLDOWN
+LIOB18_X81Y301,IOB_X0Y289,dio[205],LVCMOS18,8,SLOW,NONE
+LIOB18_X81Y301,IOB_X0Y290,dio[206],LVCMOS18,12,FAST,KEEPER
+LIOB18_X81Y303,IOB_X0Y291,dio[207],LVCMOS18,12,FAST,KEEPER
+LIOB18_X81Y303,IOB_X0Y292,dio[208],LVCMOS18,8,FAST,PULLUP
+LIOB18_X81Y305,IOB_X0Y293,dio[209],LVCMOS18,6,SLOW,KEEPER
+LIOB18_X81Y305,IOB_X0Y294,dio[210],LVCMOS18,6,SLOW,NONE
+LIOB18_X81Y307,IOB_X0Y295,dio[211],LVCMOS18,8,SLOW,PULLUP
+LIOB18_X81Y307,IOB_X0Y296,dio[212],LVCMOS18,6,SLOW,PULLUP
+LIOB18_X81Y309,IOB_X0Y297,dio[213],LVCMOS18,8,SLOW,PULLDOWN
+LIOB18_X81Y309,IOB_X0Y298,dio[214],LVCMOS18,4,FAST,PULLDOWN
+LIOB18_X81Y31,IOB_X0Y29,dio[215],LVCMOS18,4,SLOW,NONE
+LIOB18_X81Y31,IOB_X0Y30,dio[216],LVCMOS18,12,SLOW,PULLDOWN
+LIOB18_X81Y314,IOB_X0Y301,dio[217],LVCMOS18,8,SLOW,PULLDOWN
+LIOB18_X81Y314,IOB_X0Y302,dio[218],LVCMOS18,2,FAST,PULLUP
+LIOB18_X81Y316,IOB_X0Y303,dio[219],LVCMOS18,8,FAST,KEEPER
+LIOB18_X81Y316,IOB_X0Y304,dio[220],LVCMOS18,12,SLOW,NONE
+LIOB18_X81Y318,IOB_X0Y305,dio[221],LVCMOS18,8,SLOW,PULLDOWN
+LIOB18_X81Y318,IOB_X0Y306,dio[222],LVCMOS18,12,SLOW,NONE
+LIOB18_X81Y320,IOB_X0Y307,dio[223],LVCMOS18,12,SLOW,KEEPER
+LIOB18_X81Y320,IOB_X0Y308,dio[224],LVCMOS18,8,FAST,PULLUP
+LIOB18_X81Y322,IOB_X0Y309,dio[225],LVCMOS18,12,FAST,NONE
+LIOB18_X81Y322,IOB_X0Y310,dio[226],LVCMOS18,8,SLOW,KEEPER
+LIOB18_X81Y324,IOB_X0Y311,dio[227],LVCMOS18,12,SLOW,NONE
+LIOB18_X81Y324,IOB_X0Y312,dio[228],LVCMOS18,4,SLOW,KEEPER
+LIOB18_X81Y326,IOB_X0Y313,dio[229],LVCMOS18,8,FAST,PULLUP
+LIOB18_X81Y326,IOB_X0Y314,dio[230],LVCMOS18,16,FAST,KEEPER
+LIOB18_X81Y328,IOB_X0Y315,dio[231],LVCMOS18,16,SLOW,PULLUP
+LIOB18_X81Y328,IOB_X0Y316,dio[232],LVCMOS18,6,FAST,NONE
+LIOB18_X81Y33,IOB_X0Y31,dio[233],LVCMOS18,8,FAST,PULLUP
+LIOB18_X81Y33,IOB_X0Y32,dio[234],LVCMOS18,6,FAST,PULLUP
+LIOB18_X81Y330,IOB_X0Y317,dio[235],LVCMOS18,16,FAST,KEEPER
+LIOB18_X81Y330,IOB_X0Y318,dio[236],LVCMOS18,16,SLOW,PULLUP
+LIOB18_X81Y332,IOB_X0Y319,dio[237],LVCMOS18,8,SLOW,PULLDOWN
+LIOB18_X81Y332,IOB_X0Y320,dio[238],LVCMOS18,16,FAST,PULLDOWN
+LIOB18_X81Y334,IOB_X0Y321,dio[239],LVCMOS18,12,SLOW,KEEPER
+LIOB18_X81Y334,IOB_X0Y322,dio[240],LVCMOS18,2,SLOW,KEEPER
+LIOB18_X81Y336,IOB_X0Y323,dio[241],LVCMOS18,8,SLOW,KEEPER
+LIOB18_X81Y336,IOB_X0Y324,dio[242],LVCMOS18,8,SLOW,NONE
+LIOB18_X81Y339,IOB_X0Y325,dio[243],LVCMOS18,6,FAST,PULLDOWN
+LIOB18_X81Y339,IOB_X0Y326,dio[244],LVCMOS18,4,SLOW,NONE
+LIOB18_X81Y341,IOB_X0Y327,dio[245],LVCMOS18,6,FAST,PULLUP
+LIOB18_X81Y341,IOB_X0Y328,dio[246],LVCMOS18,2,SLOW,NONE
+LIOB18_X81Y343,IOB_X0Y329,dio[247],LVCMOS18,12,SLOW,PULLUP
+LIOB18_X81Y343,IOB_X0Y330,dio[248],LVCMOS18,2,FAST,NONE
+LIOB18_X81Y345,IOB_X0Y331,dio[249],LVCMOS18,16,FAST,NONE
+LIOB18_X81Y345,IOB_X0Y332,dio[250],LVCMOS18,12,FAST,NONE
+LIOB18_X81Y347,IOB_X0Y333,dio[251],LVCMOS18,6,SLOW,NONE
+LIOB18_X81Y347,IOB_X0Y334,dio[252],LVCMOS18,4,FAST,NONE
+LIOB18_X81Y349,IOB_X0Y335,dio[253],LVCMOS18,4,FAST,PULLDOWN
+LIOB18_X81Y349,IOB_X0Y336,dio[254],LVCMOS18,16,SLOW,KEEPER
+LIOB18_X81Y35,IOB_X0Y33,dio[255],LVCMOS18,2,FAST,PULLUP
+LIOB18_X81Y35,IOB_X0Y34,dio[256],LVCMOS18,12,FAST,PULLDOWN
+LIOB18_X81Y351,IOB_X0Y337,dio[257],LVCMOS18,2,SLOW,NONE
+LIOB18_X81Y351,IOB_X0Y338,dio[258],LVCMOS18,12,FAST,NONE
+LIOB18_X81Y353,IOB_X0Y339,dio[259],LVCMOS18,8,SLOW,NONE
+LIOB18_X81Y353,IOB_X0Y340,dio[260],LVCMOS18,16,FAST,NONE
+LIOB18_X81Y355,IOB_X0Y341,dio[261],LVCMOS18,6,FAST,PULLUP
+LIOB18_X81Y355,IOB_X0Y342,dio[262],LVCMOS18,16,FAST,KEEPER
+LIOB18_X81Y357,IOB_X0Y343,dio[263],LVCMOS18,2,SLOW,PULLDOWN
+LIOB18_X81Y357,IOB_X0Y344,dio[264],LVCMOS18,6,SLOW,PULLDOWN
+LIOB18_X81Y359,IOB_X0Y345,dio[265],LVCMOS18,12,SLOW,PULLDOWN
+LIOB18_X81Y359,IOB_X0Y346,dio[266],LVCMOS18,6,FAST,PULLDOWN
+LIOB18_X81Y361,IOB_X0Y347,dio[267],LVCMOS18,12,FAST,PULLDOWN
+LIOB18_X81Y361,IOB_X0Y348,dio[268],LVCMOS18,16,FAST,PULLUP
+LIOB18_X81Y37,IOB_X0Y35,dio[269],LVCMOS18,6,FAST,PULLDOWN
+LIOB18_X81Y37,IOB_X0Y36,dio[270],LVCMOS18,2,FAST,NONE
+LIOB18_X81Y39,IOB_X0Y37,dio[271],LVCMOS18,6,FAST,PULLUP
+LIOB18_X81Y39,IOB_X0Y38,dio[272],LVCMOS18,16,FAST,KEEPER
+LIOB18_X81Y4,IOB_X0Y3,dio[273],LVCMOS18,16,SLOW,KEEPER
+LIOB18_X81Y4,IOB_X0Y4,dio[274],LVCMOS18,8,FAST,PULLUP
+LIOB18_X81Y41,IOB_X0Y39,dio[275],LVCMOS18,12,SLOW,KEEPER
+LIOB18_X81Y41,IOB_X0Y40,dio[276],LVCMOS18,8,SLOW,PULLUP
+LIOB18_X81Y43,IOB_X0Y41,dio[277],LVCMOS18,16,SLOW,NONE
+LIOB18_X81Y43,IOB_X0Y42,dio[278],LVCMOS18,6,FAST,PULLDOWN
+LIOB18_X81Y45,IOB_X0Y43,dio[279],LVCMOS18,16,SLOW,KEEPER
+LIOB18_X81Y45,IOB_X0Y44,dio[280],LVCMOS18,16,SLOW,NONE
+LIOB18_X81Y47,IOB_X0Y45,dio[281],LVCMOS18,4,FAST,KEEPER
+LIOB18_X81Y47,IOB_X0Y46,dio[282],LVCMOS18,4,FAST,NONE
+LIOB18_X81Y49,IOB_X0Y47,dio[283],LVCMOS18,12,SLOW,NONE
+LIOB18_X81Y49,IOB_X0Y48,dio[284],LVCMOS18,8,FAST,KEEPER
+LIOB18_X81Y54,IOB_X0Y51,dio[285],LVCMOS18,12,FAST,KEEPER
+LIOB18_X81Y54,IOB_X0Y52,dio[286],LVCMOS18,2,SLOW,PULLDOWN
+LIOB18_X81Y56,IOB_X0Y53,dio[287],LVCMOS18,16,FAST,NONE
+LIOB18_X81Y56,IOB_X0Y54,dio[288],LVCMOS18,8,SLOW,KEEPER
+LIOB18_X81Y58,IOB_X0Y55,dio[289],LVCMOS18,4,SLOW,KEEPER
+LIOB18_X81Y58,IOB_X0Y56,dio[290],LVCMOS18,8,FAST,PULLDOWN
+LIOB18_X81Y6,IOB_X0Y5,dio[291],LVCMOS18,8,SLOW,KEEPER
+LIOB18_X81Y6,IOB_X0Y6,dio[292],LVCMOS18,6,SLOW,PULLUP
+LIOB18_X81Y60,IOB_X0Y57,dio[293],LVCMOS18,16,FAST,PULLDOWN
+LIOB18_X81Y60,IOB_X0Y58,dio[294],LVCMOS18,6,SLOW,KEEPER
+LIOB18_X81Y62,IOB_X0Y59,dio[295],LVCMOS18,6,FAST,KEEPER
+LIOB18_X81Y62,IOB_X0Y60,dio[296],LVCMOS18,6,FAST,PULLDOWN
+LIOB18_X81Y64,IOB_X0Y61,dio[297],LVCMOS18,8,SLOW,PULLUP
+LIOB18_X81Y64,IOB_X0Y62,dio[298],LVCMOS18,2,SLOW,NONE
+LIOB18_X81Y66,IOB_X0Y63,dio[299],LVCMOS18,16,FAST,PULLUP
+LIOB18_X81Y66,IOB_X0Y64,dio[300],LVCMOS18,16,SLOW,PULLUP
+LIOB18_X81Y68,IOB_X0Y65,dio[301],LVCMOS18,2,SLOW,KEEPER
+LIOB18_X81Y68,IOB_X0Y66,dio[302],LVCMOS18,4,FAST,KEEPER
+LIOB18_X81Y70,IOB_X0Y67,dio[303],LVCMOS18,2,FAST,PULLUP
+LIOB18_X81Y70,IOB_X0Y68,dio[304],LVCMOS18,4,SLOW,NONE
+LIOB18_X81Y72,IOB_X0Y69,dio[305],LVCMOS18,4,SLOW,KEEPER
+LIOB18_X81Y72,IOB_X0Y70,dio[306],LVCMOS18,8,SLOW,PULLDOWN
+LIOB18_X81Y74,IOB_X0Y71,dio[307],LVCMOS18,2,FAST,PULLDOWN
+LIOB18_X81Y74,IOB_X0Y72,dio[308],LVCMOS18,6,SLOW,NONE
+LIOB18_X81Y76,IOB_X0Y73,dio[309],LVCMOS18,8,SLOW,NONE
+LIOB18_X81Y76,IOB_X0Y74,dio[310],LVCMOS18,12,FAST,KEEPER
+LIOB18_X81Y79,IOB_X0Y75,dio[311],LVCMOS18,2,SLOW,KEEPER
+LIOB18_X81Y79,IOB_X0Y76,dio[312],LVCMOS18,12,SLOW,NONE
+LIOB18_X81Y8,IOB_X0Y7,dio[313],LVCMOS18,4,SLOW,PULLDOWN
+LIOB18_X81Y8,IOB_X0Y8,dio[314],LVCMOS18,12,FAST,NONE
+LIOB18_X81Y81,IOB_X0Y77,dio[315],LVCMOS18,12,SLOW,KEEPER
+LIOB18_X81Y81,IOB_X0Y78,dio[316],LVCMOS18,2,FAST,NONE
+LIOB18_X81Y83,IOB_X0Y79,dio[317],LVCMOS18,16,FAST,NONE
+LIOB18_X81Y83,IOB_X0Y80,dio[318],LVCMOS18,16,SLOW,PULLDOWN
+LIOB18_X81Y85,IOB_X0Y81,dio[319],LVCMOS18,4,SLOW,PULLDOWN
+LIOB18_X81Y85,IOB_X0Y82,dio[320],LVCMOS18,4,FAST,PULLDOWN
+LIOB18_X81Y87,IOB_X0Y83,dio[321],LVCMOS18,8,SLOW,PULLUP
+LIOB18_X81Y87,IOB_X0Y84,dio[322],LVCMOS18,6,FAST,NONE
+LIOB18_X81Y89,IOB_X0Y85,dio[323],LVCMOS18,16,FAST,PULLDOWN
+LIOB18_X81Y89,IOB_X0Y86,dio[324],LVCMOS18,16,SLOW,KEEPER
+LIOB18_X81Y91,IOB_X0Y87,dio[325],LVCMOS18,6,SLOW,KEEPER
+LIOB18_X81Y91,IOB_X0Y88,dio[326],LVCMOS18,8,SLOW,PULLUP
+LIOB18_X81Y93,IOB_X0Y89,dio[327],LVCMOS18,8,SLOW,PULLUP
+LIOB18_X81Y93,IOB_X0Y90,dio[328],LVCMOS18,16,FAST,NONE
+LIOB18_X81Y95,IOB_X0Y91,dio[329],LVCMOS18,12,FAST,PULLUP
+LIOB18_X81Y95,IOB_X0Y92,dio[330],LVCMOS18,16,FAST,PULLUP
+LIOB18_X81Y97,IOB_X0Y93,dio[331],LVCMOS18,16,FAST,PULLUP
+LIOB18_X81Y97,IOB_X0Y94,dio[332],LVCMOS18,12,SLOW,PULLUP
+LIOB18_X81Y99,IOB_X0Y95,dio[333],LVCMOS18,6,FAST,PULLUP
+LIOB18_X81Y99,IOB_X0Y96,dio[334],LVCMOS18,4,FAST,NONE
+RIOB18_X312Y10,IOB_X1Y9,dio[335],LVCMOS18,6,SLOW,PULLDOWN
+RIOB18_X312Y10,IOB_X1Y10,dio[336],LVCMOS18,2,FAST,PULLUP
+RIOB18_X312Y101,IOB_X1Y97,dio[337],LVCMOS18,4,FAST,PULLUP
+RIOB18_X312Y101,IOB_X1Y98,dio[338],LVCMOS18,6,SLOW,KEEPER
+RIOB18_X312Y106,IOB_X1Y101,dio[339],LVCMOS18,12,SLOW,PULLUP
+RIOB18_X312Y106,IOB_X1Y102,dio[340],LVCMOS18,6,SLOW,PULLUP
+RIOB18_X312Y108,IOB_X1Y103,dio[341],LVCMOS18,8,FAST,NONE
+RIOB18_X312Y108,IOB_X1Y104,dio[342],LVCMOS18,6,SLOW,PULLDOWN
+RIOB18_X312Y110,IOB_X1Y105,dio[343],LVCMOS18,6,FAST,PULLUP
+RIOB18_X312Y110,IOB_X1Y106,dio[344],LVCMOS18,2,FAST,KEEPER
+RIOB18_X312Y112,IOB_X1Y107,dio[345],LVCMOS18,2,FAST,NONE
+RIOB18_X312Y112,IOB_X1Y108,dio[346],LVCMOS18,6,SLOW,NONE
+RIOB18_X312Y114,IOB_X1Y109,dio[347],LVCMOS18,8,FAST,PULLUP
+RIOB18_X312Y114,IOB_X1Y110,dio[348],LVCMOS18,16,FAST,PULLUP
+RIOB18_X312Y116,IOB_X1Y111,dio[349],LVCMOS18,16,FAST,PULLDOWN
+RIOB18_X312Y116,IOB_X1Y112,dio[350],LVCMOS18,12,SLOW,PULLUP
+RIOB18_X312Y118,IOB_X1Y113,dio[351],LVCMOS18,8,SLOW,PULLUP
+RIOB18_X312Y118,IOB_X1Y114,dio[352],LVCMOS18,4,FAST,KEEPER
+RIOB18_X312Y12,IOB_X1Y11,dio[353],LVCMOS18,2,FAST,KEEPER
+RIOB18_X312Y12,IOB_X1Y12,dio[354],LVCMOS18,4,SLOW,PULLUP
+RIOB18_X312Y120,IOB_X1Y115,dio[355],LVCMOS18,6,SLOW,KEEPER
+RIOB18_X312Y120,IOB_X1Y116,dio[356],LVCMOS18,16,SLOW,PULLDOWN
+RIOB18_X312Y122,IOB_X1Y117,dio[357],LVCMOS18,16,SLOW,PULLUP
+RIOB18_X312Y122,IOB_X1Y118,dio[358],LVCMOS18,6,FAST,PULLDOWN
+RIOB18_X312Y124,IOB_X1Y119,dio[359],LVCMOS18,6,FAST,NONE
+RIOB18_X312Y124,IOB_X1Y120,dio[360],LVCMOS18,2,FAST,PULLDOWN
+RIOB18_X312Y126,IOB_X1Y121,dio[361],LVCMOS18,12,FAST,PULLUP
+RIOB18_X312Y126,IOB_X1Y122,dio[362],LVCMOS18,12,FAST,KEEPER
+RIOB18_X312Y128,IOB_X1Y123,dio[363],LVCMOS18,6,SLOW,PULLDOWN
+RIOB18_X312Y128,IOB_X1Y124,dio[364],LVCMOS18,6,FAST,NONE
+RIOB18_X312Y131,IOB_X1Y125,dio[365],LVCMOS18,4,FAST,PULLUP
+RIOB18_X312Y131,IOB_X1Y126,dio[366],LVCMOS18,6,FAST,NONE
+RIOB18_X312Y133,IOB_X1Y127,dio[367],LVCMOS18,2,SLOW,PULLDOWN
+RIOB18_X312Y133,IOB_X1Y128,dio[368],LVCMOS18,8,SLOW,NONE
+RIOB18_X312Y135,IOB_X1Y129,dio[369],LVCMOS18,12,SLOW,KEEPER
+RIOB18_X312Y135,IOB_X1Y130,dio[370],LVCMOS18,12,SLOW,NONE
+RIOB18_X312Y137,IOB_X1Y131,dio[371],LVCMOS18,4,SLOW,PULLDOWN
+RIOB18_X312Y137,IOB_X1Y132,dio[372],LVCMOS18,6,SLOW,PULLDOWN
+RIOB18_X312Y139,IOB_X1Y133,dio[373],LVCMOS18,16,SLOW,PULLUP
+RIOB18_X312Y139,IOB_X1Y134,dio[374],LVCMOS18,8,FAST,KEEPER
+RIOB18_X312Y14,IOB_X1Y13,dio[375],LVCMOS18,8,SLOW,NONE
+RIOB18_X312Y14,IOB_X1Y14,dio[376],LVCMOS18,16,SLOW,PULLUP
+RIOB18_X312Y141,IOB_X1Y135,dio[377],LVCMOS18,16,FAST,KEEPER
+RIOB18_X312Y141,IOB_X1Y136,dio[378],LVCMOS18,2,FAST,NONE
+RIOB18_X312Y143,IOB_X1Y137,dio[379],LVCMOS18,2,FAST,KEEPER
+RIOB18_X312Y143,IOB_X1Y138,dio[380],LVCMOS18,6,SLOW,PULLUP
+RIOB18_X312Y145,IOB_X1Y139,dio[381],LVCMOS18,6,FAST,PULLDOWN
+RIOB18_X312Y145,IOB_X1Y140,dio[382],LVCMOS18,8,FAST,NONE
+RIOB18_X312Y147,IOB_X1Y141,dio[383],LVCMOS18,4,FAST,NONE
+RIOB18_X312Y147,IOB_X1Y142,dio[384],LVCMOS18,4,FAST,NONE
+RIOB18_X312Y149,IOB_X1Y143,dio[385],LVCMOS18,8,SLOW,NONE
+RIOB18_X312Y149,IOB_X1Y144,dio[386],LVCMOS18,12,SLOW,NONE
+RIOB18_X312Y151,IOB_X1Y145,dio[387],LVCMOS18,12,SLOW,PULLDOWN
+RIOB18_X312Y151,IOB_X1Y146,dio[388],LVCMOS18,16,SLOW,KEEPER
+RIOB18_X312Y153,IOB_X1Y147,dio[389],LVCMOS18,12,FAST,PULLDOWN
+RIOB18_X312Y153,IOB_X1Y148,dio[390],LVCMOS18,16,SLOW,KEEPER
+RIOB18_X312Y158,IOB_X1Y151,dio[391],LVCMOS18,4,SLOW,KEEPER
+RIOB18_X312Y158,IOB_X1Y152,dio[392],LVCMOS18,8,SLOW,PULLDOWN
+RIOB18_X312Y16,IOB_X1Y15,dio[393],LVCMOS18,16,SLOW,KEEPER
+RIOB18_X312Y16,IOB_X1Y16,dio[394],LVCMOS18,12,SLOW,PULLUP
+RIOB18_X312Y160,IOB_X1Y153,dio[395],LVCMOS18,4,SLOW,PULLDOWN
+RIOB18_X312Y160,IOB_X1Y154,dio[396],LVCMOS18,6,SLOW,KEEPER
+RIOB18_X312Y162,IOB_X1Y155,dio[397],LVCMOS18,2,FAST,KEEPER
+RIOB18_X312Y162,IOB_X1Y156,dio[398],LVCMOS18,8,SLOW,PULLUP
+RIOB18_X312Y164,IOB_X1Y157,dio[399],LVCMOS18,8,FAST,PULLUP
+RIOB18_X312Y164,IOB_X1Y158,dio[400],LVCMOS18,8,SLOW,NONE
+RIOB18_X312Y166,IOB_X1Y159,dio[401],LVCMOS18,8,FAST,NONE
+RIOB18_X312Y166,IOB_X1Y160,dio[402],LVCMOS18,2,SLOW,NONE
+RIOB18_X312Y168,IOB_X1Y161,dio[403],LVCMOS18,6,SLOW,KEEPER
+RIOB18_X312Y168,IOB_X1Y162,dio[404],LVCMOS18,6,FAST,NONE
+RIOB18_X312Y170,IOB_X1Y163,dio[405],LVCMOS18,4,SLOW,PULLDOWN
+RIOB18_X312Y170,IOB_X1Y164,dio[406],LVCMOS18,4,FAST,PULLDOWN
+RIOB18_X312Y172,IOB_X1Y165,dio[407],LVCMOS18,8,SLOW,NONE
+RIOB18_X312Y172,IOB_X1Y166,dio[408],LVCMOS18,6,SLOW,KEEPER
+RIOB18_X312Y174,IOB_X1Y167,dio[409],LVCMOS18,2,FAST,PULLDOWN
+RIOB18_X312Y174,IOB_X1Y168,dio[410],LVCMOS18,16,FAST,KEEPER
+RIOB18_X312Y176,IOB_X1Y169,dio[411],LVCMOS18,16,FAST,NONE
+RIOB18_X312Y176,IOB_X1Y170,dio[412],LVCMOS18,12,SLOW,KEEPER
+RIOB18_X312Y178,IOB_X1Y171,dio[413],LVCMOS18,8,FAST,PULLUP
+RIOB18_X312Y178,IOB_X1Y172,dio[414],LVCMOS18,16,FAST,KEEPER
+RIOB18_X312Y18,IOB_X1Y17,dio[415],LVCMOS18,8,SLOW,PULLDOWN
+RIOB18_X312Y18,IOB_X1Y18,dio[416],LVCMOS18,8,SLOW,NONE
+RIOB18_X312Y180,IOB_X1Y173,dio[417],LVCMOS18,12,SLOW,PULLDOWN
+RIOB18_X312Y180,IOB_X1Y174,dio[418],LVCMOS18,6,FAST,PULLDOWN
+RIOB18_X312Y183,IOB_X1Y175,dio[419],LVCMOS18,4,FAST,PULLUP
+RIOB18_X312Y183,IOB_X1Y176,dio[420],LVCMOS18,6,SLOW,PULLUP
+RIOB18_X312Y185,IOB_X1Y177,dio[421],LVCMOS18,12,FAST,PULLUP
+RIOB18_X312Y185,IOB_X1Y178,dio[422],LVCMOS18,2,SLOW,PULLDOWN
+RIOB18_X312Y187,IOB_X1Y179,dio[423],LVCMOS18,4,FAST,NONE
+RIOB18_X312Y187,IOB_X1Y180,dio[424],LVCMOS18,4,FAST,NONE
+RIOB18_X312Y189,IOB_X1Y181,dio[425],LVCMOS18,16,FAST,PULLUP
+RIOB18_X312Y189,IOB_X1Y182,dio[426],LVCMOS18,6,SLOW,PULLDOWN
+RIOB18_X312Y191,IOB_X1Y183,dio[427],LVCMOS18,6,SLOW,NONE
+RIOB18_X312Y191,IOB_X1Y184,dio[428],LVCMOS18,16,SLOW,PULLDOWN
+RIOB18_X312Y193,IOB_X1Y185,dio[429],LVCMOS18,8,FAST,PULLUP
+RIOB18_X312Y193,IOB_X1Y186,dio[430],LVCMOS18,12,FAST,PULLUP
+RIOB18_X312Y195,IOB_X1Y187,dio[431],LVCMOS18,4,FAST,NONE
+RIOB18_X312Y195,IOB_X1Y188,dio[432],LVCMOS18,8,SLOW,PULLUP
+RIOB18_X312Y197,IOB_X1Y189,dio[433],LVCMOS18,16,FAST,PULLDOWN
+RIOB18_X312Y197,IOB_X1Y190,dio[434],LVCMOS18,4,SLOW,NONE
+RIOB18_X312Y199,IOB_X1Y191,dio[435],LVCMOS18,8,FAST,NONE
+RIOB18_X312Y199,IOB_X1Y192,dio[436],LVCMOS18,6,SLOW,PULLUP
+RIOB18_X312Y2,IOB_X1Y1,dio[437],LVCMOS18,8,SLOW,NONE
+RIOB18_X312Y2,IOB_X1Y2,dio[438],LVCMOS18,6,SLOW,KEEPER
+RIOB18_X312Y20,IOB_X1Y19,dio[439],LVCMOS18,12,FAST,PULLUP
+RIOB18_X312Y20,IOB_X1Y20,dio[440],LVCMOS18,16,SLOW,PULLUP
+RIOB18_X312Y201,IOB_X1Y193,dio[441],LVCMOS18,12,SLOW,NONE
+RIOB18_X312Y201,IOB_X1Y194,dio[442],LVCMOS18,8,SLOW,KEEPER
+RIOB18_X312Y203,IOB_X1Y195,dio[443],LVCMOS18,6,FAST,PULLDOWN
+RIOB18_X312Y203,IOB_X1Y196,dio[444],LVCMOS18,16,SLOW,PULLDOWN
+RIOB18_X312Y205,IOB_X1Y197,dio[445],LVCMOS18,16,SLOW,PULLUP
+RIOB18_X312Y205,IOB_X1Y198,dio[446],LVCMOS18,6,FAST,NONE
+RIOB18_X312Y210,IOB_X1Y201,dio[447],LVCMOS18,4,FAST,KEEPER
+RIOB18_X312Y210,IOB_X1Y202,dio[448],LVCMOS18,8,FAST,PULLDOWN
+RIOB18_X312Y212,IOB_X1Y203,dio[449],LVCMOS18,2,SLOW,PULLUP
+RIOB18_X312Y212,IOB_X1Y204,dio[450],LVCMOS18,6,SLOW,KEEPER
+RIOB18_X312Y214,IOB_X1Y205,dio[451],LVCMOS18,12,FAST,PULLDOWN
+RIOB18_X312Y214,IOB_X1Y206,dio[452],LVCMOS18,8,FAST,NONE
+RIOB18_X312Y216,IOB_X1Y207,dio[453],LVCMOS18,8,FAST,KEEPER
+RIOB18_X312Y216,IOB_X1Y208,dio[454],LVCMOS18,12,SLOW,NONE
+RIOB18_X312Y218,IOB_X1Y209,dio[455],LVCMOS18,8,SLOW,KEEPER
+RIOB18_X312Y218,IOB_X1Y210,dio[456],LVCMOS18,4,SLOW,PULLDOWN
+RIOB18_X312Y22,IOB_X1Y21,dio[457],LVCMOS18,16,SLOW,PULLDOWN
+RIOB18_X312Y22,IOB_X1Y22,dio[458],LVCMOS18,16,SLOW,KEEPER
+RIOB18_X312Y220,IOB_X1Y211,dio[459],LVCMOS18,2,SLOW,NONE
+RIOB18_X312Y220,IOB_X1Y212,dio[460],LVCMOS18,12,FAST,KEEPER
+RIOB18_X312Y222,IOB_X1Y213,dio[461],LVCMOS18,6,FAST,PULLDOWN
+RIOB18_X312Y222,IOB_X1Y214,dio[462],LVCMOS18,2,FAST,NONE
+RIOB18_X312Y224,IOB_X1Y215,dio[463],LVCMOS18,16,FAST,NONE
+RIOB18_X312Y224,IOB_X1Y216,dio[464],LVCMOS18,12,FAST,NONE
+RIOB18_X312Y226,IOB_X1Y217,dio[465],LVCMOS18,6,FAST,PULLUP
+RIOB18_X312Y226,IOB_X1Y218,dio[466],LVCMOS18,6,SLOW,PULLDOWN
+RIOB18_X312Y228,IOB_X1Y219,dio[467],LVCMOS18,8,FAST,NONE
+RIOB18_X312Y228,IOB_X1Y220,dio[468],LVCMOS18,8,SLOW,PULLDOWN
+RIOB18_X312Y230,IOB_X1Y221,dio[469],LVCMOS18,4,SLOW,PULLDOWN
+RIOB18_X312Y230,IOB_X1Y222,dio[470],LVCMOS18,16,FAST,NONE
+RIOB18_X312Y232,IOB_X1Y223,dio[471],LVCMOS18,8,FAST,NONE
+RIOB18_X312Y232,IOB_X1Y224,dio[472],LVCMOS18,8,SLOW,PULLDOWN
+RIOB18_X312Y235,IOB_X1Y225,dio[473],LVCMOS18,4,SLOW,PULLDOWN
+RIOB18_X312Y235,IOB_X1Y226,dio[474],LVCMOS18,8,SLOW,PULLDOWN
+RIOB18_X312Y237,IOB_X1Y227,dio[475],LVCMOS18,16,FAST,PULLDOWN
+RIOB18_X312Y237,IOB_X1Y228,dio[476],LVCMOS18,8,SLOW,KEEPER
+RIOB18_X312Y239,IOB_X1Y229,dio[477],LVCMOS18,4,SLOW,NONE
+RIOB18_X312Y239,IOB_X1Y230,dio[478],LVCMOS18,8,SLOW,KEEPER
+RIOB18_X312Y24,IOB_X1Y23,dio[479],LVCMOS18,16,SLOW,NONE
+RIOB18_X312Y24,IOB_X1Y24,dio[480],LVCMOS18,6,SLOW,KEEPER
+RIOB18_X312Y241,IOB_X1Y231,dio[481],LVCMOS18,8,SLOW,NONE
+RIOB18_X312Y241,IOB_X1Y232,dio[482],LVCMOS18,6,SLOW,PULLUP
+RIOB18_X312Y243,IOB_X1Y233,dio[483],LVCMOS18,2,SLOW,PULLDOWN
+RIOB18_X312Y243,IOB_X1Y234,dio[484],LVCMOS18,2,SLOW,PULLUP
+RIOB18_X312Y245,IOB_X1Y235,dio[485],LVCMOS18,6,SLOW,KEEPER
+RIOB18_X312Y245,IOB_X1Y236,dio[486],LVCMOS18,8,SLOW,PULLDOWN
+RIOB18_X312Y247,IOB_X1Y237,dio[487],LVCMOS18,16,FAST,NONE
+RIOB18_X312Y247,IOB_X1Y238,dio[488],LVCMOS18,2,SLOW,NONE
+RIOB18_X312Y249,IOB_X1Y239,dio[489],LVCMOS18,16,FAST,PULLUP
+RIOB18_X312Y249,IOB_X1Y240,dio[490],LVCMOS18,2,SLOW,PULLDOWN
+RIOB18_X312Y251,IOB_X1Y241,dio[491],LVCMOS18,12,FAST,PULLUP
+RIOB18_X312Y251,IOB_X1Y242,dio[492],LVCMOS18,8,SLOW,KEEPER
+RIOB18_X312Y253,IOB_X1Y243,dio[493],LVCMOS18,6,SLOW,PULLUP
+RIOB18_X312Y253,IOB_X1Y244,dio[494],LVCMOS18,16,FAST,KEEPER
+RIOB18_X312Y255,IOB_X1Y245,dio[495],LVCMOS18,2,SLOW,PULLDOWN
+RIOB18_X312Y255,IOB_X1Y246,dio[496],LVCMOS18,2,SLOW,NONE
+RIOB18_X312Y257,IOB_X1Y247,dio[497],LVCMOS18,8,SLOW,PULLUP
+RIOB18_X312Y257,IOB_X1Y248,dio[498],LVCMOS18,16,SLOW,PULLUP
+RIOB18_X312Y262,IOB_X1Y251,dio[499],LVCMOS18,16,SLOW,PULLDOWN
+RIOB18_X312Y262,IOB_X1Y252,dio[500],LVCMOS18,2,SLOW,KEEPER
+RIOB18_X312Y264,IOB_X1Y253,dio[501],LVCMOS18,6,FAST,PULLDOWN
+RIOB18_X312Y264,IOB_X1Y254,dio[502],LVCMOS18,16,SLOW,NONE
+RIOB18_X312Y266,IOB_X1Y255,dio[503],LVCMOS18,12,SLOW,KEEPER
+RIOB18_X312Y266,IOB_X1Y256,dio[504],LVCMOS18,12,FAST,PULLDOWN
+RIOB18_X312Y268,IOB_X1Y257,dio[505],LVCMOS18,6,FAST,KEEPER
+RIOB18_X312Y268,IOB_X1Y258,dio[506],LVCMOS18,4,FAST,NONE
+RIOB18_X312Y27,IOB_X1Y25,dio[507],LVCMOS18,16,FAST,NONE
+RIOB18_X312Y27,IOB_X1Y26,dio[508],LVCMOS18,8,FAST,KEEPER
+RIOB18_X312Y270,IOB_X1Y259,dio[509],LVCMOS18,2,FAST,PULLDOWN
+RIOB18_X312Y270,IOB_X1Y260,dio[510],LVCMOS18,2,FAST,PULLUP
+RIOB18_X312Y272,IOB_X1Y261,dio[511],LVCMOS18,16,SLOW,PULLDOWN
+RIOB18_X312Y272,IOB_X1Y262,dio[512],LVCMOS18,4,SLOW,PULLDOWN
+RIOB18_X312Y274,IOB_X1Y263,dio[513],LVCMOS18,8,FAST,PULLUP
+RIOB18_X312Y274,IOB_X1Y264,dio[514],LVCMOS18,16,FAST,NONE
+RIOB18_X312Y276,IOB_X1Y265,dio[515],LVCMOS18,4,FAST,PULLDOWN
+RIOB18_X312Y276,IOB_X1Y266,dio[516],LVCMOS18,6,SLOW,PULLUP
+RIOB18_X312Y278,IOB_X1Y267,dio[517],LVCMOS18,8,SLOW,NONE
+RIOB18_X312Y278,IOB_X1Y268,dio[518],LVCMOS18,4,SLOW,PULLUP
+RIOB18_X312Y280,IOB_X1Y269,dio[519],LVCMOS18,12,FAST,PULLUP
+RIOB18_X312Y280,IOB_X1Y270,dio[520],LVCMOS18,16,SLOW,PULLUP
+RIOB18_X312Y282,IOB_X1Y271,dio[521],LVCMOS18,16,SLOW,NONE
+RIOB18_X312Y282,IOB_X1Y272,dio[522],LVCMOS18,8,SLOW,PULLDOWN
+RIOB18_X312Y284,IOB_X1Y273,dio[523],LVCMOS18,8,SLOW,PULLDOWN
+RIOB18_X312Y284,IOB_X1Y274,dio[524],LVCMOS18,2,SLOW,KEEPER
+RIOB18_X312Y287,IOB_X1Y275,dio[525],LVCMOS18,2,FAST,PULLDOWN
+RIOB18_X312Y287,IOB_X1Y276,dio[526],LVCMOS18,6,FAST,PULLDOWN
+RIOB18_X312Y289,IOB_X1Y277,dio[527],LVCMOS18,16,SLOW,PULLDOWN
+RIOB18_X312Y289,IOB_X1Y278,dio[528],LVCMOS18,4,FAST,PULLDOWN
+RIOB18_X312Y29,IOB_X1Y27,dio[529],LVCMOS18,4,SLOW,PULLDOWN
+RIOB18_X312Y29,IOB_X1Y28,dio[530],LVCMOS18,8,FAST,NONE
+RIOB18_X312Y291,IOB_X1Y279,dio[531],LVCMOS18,8,SLOW,PULLDOWN
+RIOB18_X312Y291,IOB_X1Y280,dio[532],LVCMOS18,16,FAST,PULLDOWN
+RIOB18_X312Y293,IOB_X1Y281,dio[533],LVCMOS18,8,FAST,PULLDOWN
+RIOB18_X312Y293,IOB_X1Y282,dio[534],LVCMOS18,6,SLOW,NONE
+RIOB18_X312Y295,IOB_X1Y283,dio[535],LVCMOS18,2,FAST,NONE
+RIOB18_X312Y295,IOB_X1Y284,dio[536],LVCMOS18,8,FAST,NONE
+RIOB18_X312Y297,IOB_X1Y285,dio[537],LVCMOS18,16,FAST,PULLDOWN
+RIOB18_X312Y297,IOB_X1Y286,dio[538],LVCMOS18,4,SLOW,KEEPER
+RIOB18_X312Y299,IOB_X1Y287,dio[539],LVCMOS18,12,SLOW,PULLUP
+RIOB18_X312Y299,IOB_X1Y288,dio[540],LVCMOS18,6,SLOW,PULLDOWN
+RIOB18_X312Y301,IOB_X1Y289,dio[541],LVCMOS18,2,SLOW,PULLDOWN
+RIOB18_X312Y301,IOB_X1Y290,dio[542],LVCMOS18,4,SLOW,PULLUP
+RIOB18_X312Y303,IOB_X1Y291,dio[543],LVCMOS18,16,FAST,PULLUP
+RIOB18_X312Y303,IOB_X1Y292,dio[544],LVCMOS18,16,SLOW,KEEPER
+RIOB18_X312Y305,IOB_X1Y293,dio[545],LVCMOS18,12,FAST,NONE
+RIOB18_X312Y305,IOB_X1Y294,dio[546],LVCMOS18,8,FAST,KEEPER
+RIOB18_X312Y307,IOB_X1Y295,dio[547],LVCMOS18,12,SLOW,NONE
+RIOB18_X312Y307,IOB_X1Y296,dio[548],LVCMOS18,16,SLOW,PULLUP
+RIOB18_X312Y309,IOB_X1Y297,dio[549],LVCMOS18,4,FAST,KEEPER
+RIOB18_X312Y309,IOB_X1Y298,dio[550],LVCMOS18,4,SLOW,NONE
+RIOB18_X312Y31,IOB_X1Y29,dio[551],LVCMOS18,6,SLOW,KEEPER
+RIOB18_X312Y31,IOB_X1Y30,dio[552],LVCMOS18,2,SLOW,NONE
+RIOB18_X312Y314,IOB_X1Y301,dio[553],LVCMOS18,2,SLOW,KEEPER
+RIOB18_X312Y314,IOB_X1Y302,dio[554],LVCMOS18,8,FAST,KEEPER
+RIOB18_X312Y316,IOB_X1Y303,dio[555],LVCMOS18,2,FAST,KEEPER
+RIOB18_X312Y316,IOB_X1Y304,dio[556],LVCMOS18,6,FAST,PULLUP
+RIOB18_X312Y318,IOB_X1Y305,dio[557],LVCMOS18,16,FAST,PULLUP
+RIOB18_X312Y318,IOB_X1Y306,dio[558],LVCMOS18,4,SLOW,PULLUP
+RIOB18_X312Y320,IOB_X1Y307,dio[559],LVCMOS18,8,SLOW,PULLDOWN
+RIOB18_X312Y320,IOB_X1Y308,dio[560],LVCMOS18,8,SLOW,PULLDOWN
+RIOB18_X312Y322,IOB_X1Y309,dio[561],LVCMOS18,6,SLOW,PULLDOWN
+RIOB18_X312Y322,IOB_X1Y310,dio[562],LVCMOS18,4,FAST,KEEPER
+RIOB18_X312Y324,IOB_X1Y311,dio[563],LVCMOS18,4,FAST,KEEPER
+RIOB18_X312Y324,IOB_X1Y312,dio[564],LVCMOS18,6,FAST,NONE
+RIOB18_X312Y326,IOB_X1Y313,dio[565],LVCMOS18,8,FAST,PULLUP
+RIOB18_X312Y326,IOB_X1Y314,dio[566],LVCMOS18,6,SLOW,PULLUP
+RIOB18_X312Y328,IOB_X1Y315,dio[567],LVCMOS18,12,FAST,NONE
+RIOB18_X312Y328,IOB_X1Y316,dio[568],LVCMOS18,2,FAST,PULLUP
+RIOB18_X312Y33,IOB_X1Y31,dio[569],LVCMOS18,12,FAST,NONE
+RIOB18_X312Y33,IOB_X1Y32,dio[570],LVCMOS18,12,FAST,PULLUP
+RIOB18_X312Y330,IOB_X1Y317,dio[571],LVCMOS18,4,FAST,KEEPER
+RIOB18_X312Y330,IOB_X1Y318,dio[572],LVCMOS18,8,FAST,NONE
+RIOB18_X312Y332,IOB_X1Y319,dio[573],LVCMOS18,8,SLOW,KEEPER
+RIOB18_X312Y332,IOB_X1Y320,dio[574],LVCMOS18,12,FAST,NONE
+RIOB18_X312Y334,IOB_X1Y321,dio[575],LVCMOS18,16,FAST,NONE
+RIOB18_X312Y334,IOB_X1Y322,dio[576],LVCMOS18,16,SLOW,KEEPER
+RIOB18_X312Y336,IOB_X1Y323,dio[577],LVCMOS18,6,FAST,NONE
+RIOB18_X312Y336,IOB_X1Y324,dio[578],LVCMOS18,4,FAST,NONE
+RIOB18_X312Y339,IOB_X1Y325,dio[579],LVCMOS18,16,FAST,KEEPER
+RIOB18_X312Y339,IOB_X1Y326,dio[580],LVCMOS18,16,SLOW,NONE
+RIOB18_X312Y341,IOB_X1Y327,dio[581],LVCMOS18,6,SLOW,NONE
+RIOB18_X312Y341,IOB_X1Y328,dio[582],LVCMOS18,2,SLOW,PULLUP
+RIOB18_X312Y343,IOB_X1Y329,dio[583],LVCMOS18,16,SLOW,PULLUP
+RIOB18_X312Y343,IOB_X1Y330,dio[584],LVCMOS18,8,SLOW,KEEPER
+RIOB18_X312Y345,IOB_X1Y331,dio[585],LVCMOS18,12,SLOW,PULLUP
+RIOB18_X312Y345,IOB_X1Y332,dio[586],LVCMOS18,16,FAST,PULLUP
+RIOB18_X312Y347,IOB_X1Y333,dio[587],LVCMOS18,8,FAST,NONE
+RIOB18_X312Y347,IOB_X1Y334,dio[588],LVCMOS18,6,SLOW,KEEPER
+RIOB18_X312Y349,IOB_X1Y335,dio[589],LVCMOS18,4,FAST,PULLUP
+RIOB18_X312Y349,IOB_X1Y336,dio[590],LVCMOS18,12,SLOW,PULLDOWN
+RIOB18_X312Y35,IOB_X1Y33,dio[591],LVCMOS18,6,SLOW,PULLDOWN
+RIOB18_X312Y35,IOB_X1Y34,dio[592],LVCMOS18,4,SLOW,PULLUP
+RIOB18_X312Y351,IOB_X1Y337,dio[593],LVCMOS18,6,SLOW,KEEPER
+RIOB18_X312Y351,IOB_X1Y338,dio[594],LVCMOS18,8,FAST,KEEPER
+RIOB18_X312Y353,IOB_X1Y339,dio[595],LVCMOS18,6,FAST,PULLDOWN
+RIOB18_X312Y353,IOB_X1Y340,dio[596],LVCMOS18,6,SLOW,KEEPER
+RIOB18_X312Y355,IOB_X1Y341,dio[597],LVCMOS18,8,FAST,NONE
+RIOB18_X312Y355,IOB_X1Y342,dio[598],LVCMOS18,8,SLOW,PULLDOWN
+RIOB18_X312Y357,IOB_X1Y343,dio[599],LVCMOS18,6,FAST,NONE
+RIOB18_X312Y357,IOB_X1Y344,dio[600],LVCMOS18,8,SLOW,KEEPER
+RIOB18_X312Y359,IOB_X1Y345,dio[601],LVCMOS18,8,SLOW,NONE
+RIOB18_X312Y359,IOB_X1Y346,dio[602],LVCMOS18,16,SLOW,PULLDOWN
+RIOB18_X312Y361,IOB_X1Y347,dio[603],LVCMOS18,8,FAST,NONE
+RIOB18_X312Y361,IOB_X1Y348,dio[604],LVCMOS18,6,FAST,PULLDOWN
+RIOB18_X312Y37,IOB_X1Y35,dio[605],LVCMOS18,4,SLOW,KEEPER
+RIOB18_X312Y37,IOB_X1Y36,dio[606],LVCMOS18,12,SLOW,PULLDOWN
+RIOB18_X312Y39,IOB_X1Y37,dio[607],LVCMOS18,4,FAST,PULLUP
+RIOB18_X312Y39,IOB_X1Y38,dio[608],LVCMOS18,6,FAST,PULLDOWN
+RIOB18_X312Y4,IOB_X1Y3,dio[609],LVCMOS18,16,FAST,PULLDOWN
+RIOB18_X312Y4,IOB_X1Y4,dio[610],LVCMOS18,12,SLOW,PULLUP
+RIOB18_X312Y41,IOB_X1Y39,dio[611],LVCMOS18,6,SLOW,NONE
+RIOB18_X312Y41,IOB_X1Y40,dio[612],LVCMOS18,16,SLOW,NONE
+RIOB18_X312Y43,IOB_X1Y41,dio[613],LVCMOS18,16,FAST,NONE
+RIOB18_X312Y43,IOB_X1Y42,dio[614],LVCMOS18,12,FAST,PULLUP
+RIOB18_X312Y45,IOB_X1Y43,dio[615],LVCMOS18,6,FAST,PULLDOWN
+RIOB18_X312Y45,IOB_X1Y44,dio[616],LVCMOS18,6,SLOW,PULLDOWN
+RIOB18_X312Y47,IOB_X1Y45,dio[617],LVCMOS18,12,FAST,PULLUP
+RIOB18_X312Y47,IOB_X1Y46,dio[618],LVCMOS18,2,SLOW,NONE
+RIOB18_X312Y49,IOB_X1Y47,dio[619],LVCMOS18,2,FAST,PULLUP
+RIOB18_X312Y49,IOB_X1Y48,dio[620],LVCMOS18,4,SLOW,PULLDOWN
+RIOB18_X312Y54,IOB_X1Y51,dio[621],LVCMOS18,12,SLOW,PULLDOWN
+RIOB18_X312Y54,IOB_X1Y52,dio[622],LVCMOS18,2,FAST,PULLDOWN
+RIOB18_X312Y56,IOB_X1Y53,dio[623],LVCMOS18,6,SLOW,NONE
+RIOB18_X312Y56,IOB_X1Y54,dio[624],LVCMOS18,4,SLOW,PULLDOWN
+RIOB18_X312Y58,IOB_X1Y55,dio[625],LVCMOS18,8,SLOW,KEEPER
+RIOB18_X312Y58,IOB_X1Y56,dio[626],LVCMOS18,12,SLOW,PULLUP
+RIOB18_X312Y6,IOB_X1Y5,dio[627],LVCMOS18,6,SLOW,PULLUP
+RIOB18_X312Y6,IOB_X1Y6,dio[628],LVCMOS18,16,FAST,PULLDOWN
+RIOB18_X312Y60,IOB_X1Y57,dio[629],LVCMOS18,8,FAST,KEEPER
+RIOB18_X312Y60,IOB_X1Y58,dio[630],LVCMOS18,2,FAST,PULLDOWN
+RIOB18_X312Y62,IOB_X1Y59,dio[631],LVCMOS18,6,SLOW,PULLUP
+RIOB18_X312Y62,IOB_X1Y60,dio[632],LVCMOS18,4,SLOW,PULLDOWN
+RIOB18_X312Y64,IOB_X1Y61,dio[633],LVCMOS18,2,FAST,KEEPER
+RIOB18_X312Y64,IOB_X1Y62,dio[634],LVCMOS18,2,SLOW,PULLUP
+RIOB18_X312Y66,IOB_X1Y63,dio[635],LVCMOS18,6,FAST,PULLUP
+RIOB18_X312Y66,IOB_X1Y64,dio[636],LVCMOS18,6,FAST,PULLDOWN
+RIOB18_X312Y68,IOB_X1Y65,dio[637],LVCMOS18,4,SLOW,KEEPER
+RIOB18_X312Y68,IOB_X1Y66,dio[638],LVCMOS18,2,FAST,PULLUP
+RIOB18_X312Y70,IOB_X1Y67,dio[639],LVCMOS18,12,SLOW,NONE
+RIOB18_X312Y70,IOB_X1Y68,dio[640],LVCMOS18,16,FAST,PULLDOWN
+RIOB18_X312Y72,IOB_X1Y69,dio[641],LVCMOS18,8,FAST,PULLDOWN
+RIOB18_X312Y72,IOB_X1Y70,dio[642],LVCMOS18,8,FAST,PULLDOWN
+RIOB18_X312Y74,IOB_X1Y71,dio[643],LVCMOS18,12,SLOW,NONE
+RIOB18_X312Y74,IOB_X1Y72,dio[644],LVCMOS18,6,FAST,KEEPER
+RIOB18_X312Y76,IOB_X1Y73,dio[645],LVCMOS18,2,SLOW,KEEPER
+RIOB18_X312Y76,IOB_X1Y74,dio[646],LVCMOS18,4,FAST,NONE
+RIOB18_X312Y79,IOB_X1Y75,dio[647],LVCMOS18,2,SLOW,NONE
+RIOB18_X312Y79,IOB_X1Y76,dio[648],LVCMOS18,6,SLOW,KEEPER
+RIOB18_X312Y8,IOB_X1Y7,dio[649],LVCMOS18,6,SLOW,PULLDOWN
+RIOB18_X312Y8,IOB_X1Y8,dio[650],LVCMOS18,16,FAST,PULLUP
+RIOB18_X312Y81,IOB_X1Y77,dio[651],LVCMOS18,2,SLOW,NONE
+RIOB18_X312Y81,IOB_X1Y78,dio[652],LVCMOS18,2,FAST,KEEPER
+RIOB18_X312Y83,IOB_X1Y79,dio[653],LVCMOS18,8,FAST,NONE
+RIOB18_X312Y83,IOB_X1Y80,dio[654],LVCMOS18,4,FAST,NONE
+RIOB18_X312Y85,IOB_X1Y81,dio[655],LVCMOS18,12,FAST,KEEPER
+RIOB18_X312Y85,IOB_X1Y82,dio[656],LVCMOS18,6,FAST,PULLDOWN
+RIOB18_X312Y87,IOB_X1Y83,dio[657],LVCMOS18,12,SLOW,KEEPER
+RIOB18_X312Y87,IOB_X1Y84,dio[658],LVCMOS18,6,FAST,NONE
+RIOB18_X312Y89,IOB_X1Y85,dio[659],LVCMOS18,4,FAST,KEEPER
+RIOB18_X312Y89,IOB_X1Y86,dio[660],LVCMOS18,12,SLOW,PULLUP
+RIOB18_X312Y91,IOB_X1Y87,dio[661],LVCMOS18,6,SLOW,NONE
+RIOB18_X312Y91,IOB_X1Y88,dio[662],LVCMOS18,12,SLOW,NONE
+RIOB18_X312Y93,IOB_X1Y89,dio[663],LVCMOS18,6,FAST,KEEPER
+RIOB18_X312Y93,IOB_X1Y90,dio[664],LVCMOS18,8,FAST,PULLDOWN
+RIOB18_X312Y95,IOB_X1Y91,dio[665],LVCMOS18,2,SLOW,NONE
+RIOB18_X312Y95,IOB_X1Y92,dio[666],LVCMOS18,4,FAST,PULLDOWN
+RIOB18_X312Y97,IOB_X1Y93,dio[667],LVCMOS18,12,FAST,KEEPER
+RIOB18_X312Y97,IOB_X1Y94,dio[668],LVCMOS18,8,SLOW,KEEPER
+RIOB18_X312Y99,IOB_X1Y95,dio[669],LVCMOS18,4,FAST,KEEPER
+RIOB18_X312Y99,IOB_X1Y96,dio[670],LVCMOS18,8,FAST,KEEPER

fuzzers/035-iob18-ilogic/tag_groups.txt

@@ -0,0 +1,8 @@
+IOI.ILOGIC_Y0.IDELMUXE3.P0 IOI.ILOGIC_Y0.IDELMUXE3.P1
+IOI.ILOGIC_Y0.IFFDELMUXE3.P0 IOI.ILOGIC_Y0.IFFDELMUXE3.P1
+IOI.ILOGIC_Y0.IFF.SRTYPE.ASYNC IOI.ILOGIC_Y0.IFF.SRTYPE.SYNC
+IOI.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE IOI.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE IOI.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED
+IOI.ILOGIC_Y1.IDELMUXE3.P0 IOI.ILOGIC_Y1.IDELMUXE3.P1
+IOI.ILOGIC_Y1.IFFDELMUXE3.P0 IOI.ILOGIC_Y1.IFFDELMUXE3.P1
+IOI.ILOGIC_Y1.IFF.SRTYPE.ASYNC IOI.ILOGIC_Y1.IFF.SRTYPE.SYNC
+IOI.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE IOI.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE IOI.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED

fuzzers/035-iob18-ilogic/top.py

@@ -0,0 +1,517 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+import json
+import io
+import os
+import random
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray import lut_maker
+from prjxray import verilog
+from prjxray.db import Database
+
+
+def gen_sites():
+    '''
+    IOB18S: main IOB of a diff pair
+    IOB18M: secondary IOB of a diff pair
+
+    Virtex-7 "VX" parts are high-performance-bank only (IOB18 / IOI = LIOI,
+    RIOI and their TBYTESRC/TBYTETERM variants); there are no IOB33/HR sites,
+    so the kintex7 035-iob-ilogic fuzzer cannot run here.  Cover BOTH the L-
+    and R-side IOB18 columns so LIOI and RIOI get real measurements rather
+    than a transplant.  SING rows are excluded (their ILOGIC is fuzzed
+    separately and has a different frame window).
+    '''
+    db = Database(util.get_db_root(), util.get_part())
+    grid = db.grid()
+    for tile_name in sorted(grid.tiles()):
+        if "IOB18" not in tile_name or "SING" in tile_name:
+            continue
+        loc = grid.loc_of_tilename(tile_name)
+        gridinfo = grid.gridinfo_at_loc(loc)
+
+        for site_name, site_type in gridinfo.sites.items():
+            if site_type in ['IOB18S', 'IOB18M']:
+                yield tile_name, site_name
+
+
+def write_params(params):
+    pinstr = 'tile,site,pin,iostandard,drive,slew\n'
+    for vals in params:
+        pinstr += ','.join(map(str, vals)) + '\n'
+
+    open('params.csv', 'w').write(pinstr)
+
+
+def use_iserdese2(p, luts, connects):
+    iobdelay = random.choice((
+        'NONE',
+        'BOTH',
+        'IBUF',
+        'IFD',
+    ))
+
+    p['IOBDELAY'] = verilog.quote(iobdelay)
+    p['INIT_Q1'] = random.randint(0, 1)
+    p['INIT_Q2'] = random.randint(0, 1)
+    p['INIT_Q3'] = random.randint(0, 1)
+    p['INIT_Q4'] = random.randint(0, 1)
+
+    p['SRVAL_Q1'] = random.randint(0, 1)
+    p['SRVAL_Q2'] = random.randint(0, 1)
+    p['SRVAL_Q3'] = random.randint(0, 1)
+    p['SRVAL_Q4'] = random.randint(0, 1)
+    p['NUM_CE'] = random.randint(1, 2)
+
+    p['IS_CLK_INVERTED'] = random.randint(0, 1)
+    p['IS_CLKB_INVERTED'] = random.randint(0, 1)
+    p['IS_OCLK_INVERTED'] = random.randint(0, 1)
+    p['IS_OCLKB_INVERTED'] = random.randint(0, 1)
+    p['IS_CLKDIV_INVERTED'] = random.randint(0, 1)
+    p['IS_D_INVERTED'] = random.randint(0, 1)
+    p['INTERFACE_TYPE'] = verilog.quote(
+        random.choice(
+            (
+                'MEMORY',
+                'MEMORY_DDR3',
+                'MEMORY_QDR',
+                'NETWORKING',
+                'OVERSAMPLE',
+            )))
+    p['DATA_RATE'] = verilog.quote(random.choice((
+        'SDR',
+        'DDR',
+    )))
+    if verilog.unquote(p['DATA_RATE']) == 'SDR':
+        data_widths = [2, 3, 4, 5, 6, 7, 8]
+    else:
+        data_widths = [4, 6, 8]
+
+    p['DATA_WIDTH'] = random.choice(data_widths)
+    p['SERDES_MODE'] = verilog.quote(random.choice(('MASTER', 'SLAVE')))
+
+    use_delay = iobdelay != 'NONE'
+
+    if iobdelay == 'NONE':
+        p['mux_config'] = 'direct'
+        p['iddr_mux_config'] = 'direct'
+    elif iobdelay == 'BOTH':
+        p['mux_config'] = 'idelay'
+        p['iddr_mux_config'] = 'idelay'
+    elif iobdelay == 'IBUF':
+        p['mux_config'] = 'idelay'
+        p['iddr_mux_config'] = 'direct'
+    elif iobdelay == 'IFD':
+        p['mux_config'] = 'direct'
+        p['iddr_mux_config'] = 'idelay'
+
+    p['OFB_USED'] = verilog.quote(random.choice(('TRUE', 'FALSE')))
+    p['DYN_CLKDIV_INV_EN'] = verilog.quote(random.choice(('TRUE', 'FALSE')))
+    p['DYN_CLK_INV_EN'] = verilog.quote(random.choice(('TRUE', 'FALSE')))
+
+    if use_delay:
+        print(
+            """
+    wire idelay_{site};
+
+    (* KEEP, DONT_TOUCH, LOC = "{idelay_loc}" *)
+    IDELAYE2 #(
+    ) idelay_site_{site} (
+        .IDATAIN({iwire}),
+        .DATAOUT(idelay_{site})
+        );""".format(**p),
+            file=connects)
+
+        p['ddly_connection'] = '.DDLY(idelay_{site}),'.format(**p)
+    else:
+        p['ddly_connection'] = ''
+
+    if verilog.unquote(p['OFB_USED']) == 'TRUE':
+        p['ODATA_RATE'] = verilog.quote(random.choice((
+            'SDR',
+            'DDR',
+        )))
+        if verilog.unquote(p['ODATA_RATE']) == 'SDR':
+            data_widths = [2, 3, 4, 5, 6, 7, 8]
+        else:
+            data_widths = [4, 6, 8]
+
+        p['ODATA_WIDTH'] = random.choice(data_widths)
+        p['OSERDES_MODE'] = verilog.quote(random.choice(('MASTER', 'SLAVE')))
+
+        if p['ODATA_WIDTH'] == 4 and verilog.unquote(p['ODATA_RATE']) == 'DDR':
+            p['TRISTATE_WIDTH'] = 4
+        else:
+            p['TRISTATE_WIDTH'] = 1
+
+        print(
+            """
+    wire tfb_{site};
+    wire ofb_{site};
+
+    (* KEEP, DONT_TOUCH, LOC = "{ologic_loc}" *)
+    OSERDESE2 #(
+        .SERDES_MODE({OSERDES_MODE}),
+        .DATA_RATE_TQ({ODATA_RATE}),
+        .DATA_RATE_OQ({ODATA_RATE}),
+        .DATA_WIDTH({ODATA_WIDTH}),
+        .TRISTATE_WIDTH({TRISTATE_WIDTH})
+    ) oserdese2_{site} (
+        .CLK(0),
+        .CLKDIV(0),
+        .D1(0),
+        .TFB(tfb_{site}),
+        .OQ({owire}),
+        .TQ({twire}),
+        .OFB(ofb_{site})
+        );""".format(**p),
+            file=connects)
+
+        p['ofb_connections'] = """
+        .OFB(ofb_{site}),
+        """.format(**p)
+    else:
+        p['ofb_connections'] = ''
+
+    if random.randint(0, 1):
+        clknet = luts.get_next_output_net()
+    else:
+        clknet = random.choice((
+            'clk_BUFG1',
+            'clk_BUFG2',
+        ))
+
+    if random.randint(0, 1):
+        clkbnet = luts.get_next_output_net()
+    else:
+        clkbnet = random.choice((
+            'clk_BUFG1',
+            'clk_BUFG2',
+        ))
+
+    if random.randint(0, 1):
+        oclknet = luts.get_next_output_net()
+    else:
+        oclknet = random.choice((
+            'clk_BUFG1',
+            'clk_BUFG2',
+        ))
+
+    clkdiv = random.choice(('clk_BUFG3', 'clk_BUFG4'))
+
+    p['DISABLE_CLOCKS'] = random.randint(0, 1)
+    if p['DISABLE_CLOCKS']:
+        clknet = '0'
+        clkbnet = '0'
+        oclknet = '0'
+        clkdiv = '0'
+
+    print(
+        '''
+    (* KEEP, DONT_TOUCH, LOC = "{ilogic_loc}" *)
+    ISERDESE2 #(
+        .SERDES_MODE({SERDES_MODE}),
+        .INIT_Q1({INIT_Q1}),
+        .INIT_Q2({INIT_Q2}),
+        .INIT_Q3({INIT_Q3}),
+        .INIT_Q4({INIT_Q4}),
+        .SRVAL_Q1({SRVAL_Q1}),
+        .SRVAL_Q2({SRVAL_Q2}),
+        .SRVAL_Q3({SRVAL_Q3}),
+        .SRVAL_Q4({SRVAL_Q4}),
+        .DYN_CLKDIV_INV_EN({DYN_CLKDIV_INV_EN}),
+        .DYN_CLK_INV_EN({DYN_CLK_INV_EN}),
+        .INTERFACE_TYPE({INTERFACE_TYPE}),
+        .IS_CLK_INVERTED({IS_CLK_INVERTED}),
+        .IS_CLKB_INVERTED({IS_CLKB_INVERTED}),
+        .IS_OCLK_INVERTED({IS_OCLK_INVERTED}),
+        .IS_OCLKB_INVERTED({IS_OCLKB_INVERTED}),
+        .IS_CLKDIV_INVERTED({IS_CLKDIV_INVERTED}),
+        .IS_D_INVERTED({IS_D_INVERTED}),
+        .OFB_USED({OFB_USED}),
+        .NUM_CE({NUM_CE}),
+        .DATA_RATE({DATA_RATE}),
+        .DATA_WIDTH({DATA_WIDTH}),
+        .IOBDELAY({IOBDELAY})
+    ) iserdese2_{site} (
+        {ddly_connection}
+        {ofb_connections}
+        .D({iwire}),
+        .CLK({clknet}),
+        .CLKB({clkbnet}),
+        .OCLK({oclknet}),
+        .O({onet}),
+        .Q1({q1net}),
+        .CLKDIV({clkdiv})
+    );'''.format(
+            clkdiv=clkdiv,
+            clknet=clknet,
+            clkbnet=clkbnet,
+            oclknet=oclknet,
+            onet=luts.get_next_input_net(),
+            q1net=luts.get_next_input_net(),
+            shiftout1net=luts.get_next_input_net(),
+            shiftout2net=luts.get_next_input_net(),
+            **p),
+        file=connects)
+
+
+def use_direct_and_iddr(p, luts, connects):
+    p['mux_config'] = random.choice((
+        'direct',
+        'idelay',
+        'none',
+    ))
+
+    p['iddr_mux_config'] = random.choice((
+        'direct',
+        'idelay',
+        'none',
+    ))
+
+    if p['iddr_mux_config'] != 'none':
+        p['INIT_Q1'] = random.randint(0, 1)
+        p['INIT_Q2'] = random.randint(0, 1)
+        p['IS_C_INVERTED'] = random.randint(0, 1)
+        p['IS_D_INVERTED'] = random.randint(0, 1)
+        p['SRTYPE'] = verilog.quote(random.choice(('SYNC', 'ASYNC')))
+        p['DDR_CLK_EDGE'] = verilog.quote(
+            random.choice(
+                (
+                    'OPPOSITE_EDGE',
+                    'SAME_EDGE',
+                    'SAME_EDGE_PIPELINED',
+                )))
+
+        print(
+            '''
+    (* KEEP, DONT_TOUCH, LOC = "{ilogic_loc}" *)
+    IDDR #(
+        .IS_D_INVERTED({IS_D_INVERTED}),
+        .IS_C_INVERTED({IS_C_INVERTED}),
+        .INIT_Q1({INIT_Q1}),
+        .INIT_Q2({INIT_Q2}),
+        .SRTYPE({SRTYPE}),
+        .DDR_CLK_EDGE({DDR_CLK_EDGE})
+    ) iddr_{site} (
+        .C({cnet}),
+        .D(iddr_d_{site}),
+        .Q1({q1}),
+        .Q2({q2})
+        );
+        '''.format(
+                cnet=luts.get_next_output_net(),
+                q1=luts.get_next_input_net(),
+                q2=luts.get_next_input_net(),
+                **p),
+            file=connects)
+
+    if p['iddr_mux_config'] == 'idelay' or p['mux_config'] == 'idelay' or p[
+            'iddr_mux_config'] == 'tristate_feedback':
+        print(
+            """
+    wire idelay_{site};
+
+    (* KEEP, DONT_TOUCH, LOC = "{idelay_loc}" *)
+    IDELAYE2 #(
+    ) idelay_site_{site} (
+        .IDATAIN({iwire}),
+        .DATAOUT(idelay_{site})
+        );""".format(**p),
+            file=connects)
+
+    print(
+        """
+    assign {owire} = {onet};
+    assign {twire} = {tnet};
+        """.format(
+            onet=luts.get_next_output_net(),
+            tnet=luts.get_next_output_net(),
+            **p),
+        file=connects)
+
+    if p['iddr_mux_config'] == 'direct':
+        print(
+            '''
+    assign iddr_d_{site} = {iwire};'''.format(**p, ),
+            file=connects)
+    elif p['iddr_mux_config'] == 'idelay':
+        print(
+            '''
+    assign iddr_d_{site} = idelay_{site};'''.format(**p, ),
+            file=connects)
+    elif p['iddr_mux_config'] == 'tristate_feedback':
+        print(
+            '''
+    assign iddr_d_{site} = tfb_{site} ? ofb_{site} : idelay_{site};'''.format(
+                **p, ),
+            file=connects)
+    elif p['iddr_mux_config'] == 'none':
+        pass
+    else:
+        assert False, p['mux_config']
+
+    if p['mux_config'] == 'direct':
+        print(
+            '''
+    assign {net} = {iwire};'''.format(
+                net=luts.get_next_input_net(),
+                **p,
+            ),
+            file=connects)
+    elif p['mux_config'] == 'idelay':
+        print(
+            '''
+    assign {net} = idelay_{site};'''.format(
+                net=luts.get_next_input_net(),
+                **p,
+            ),
+            file=connects)
+    elif p['mux_config'] == 'none':
+        pass
+    else:
+        assert False, p['mux_config']
+
+
+def run():
+    # IOSTANDARD does not affect the ILOGIC config bits being measured, so pin
+    # it to LVCMOS18 (valid on every HP bank at the default drive).  LVCMOS12's
+    # default drive of 12 is illegal on HP banks (DRC BIVB-1), and mixing
+    # standards only adds bank-compatibility failure modes for no extra ILOGIC
+    # coverage.
+    iostandards = ['LVCMOS18']
+    iostandard = random.choice(iostandards)
+    drives = [2, 4, 6, 8, 12, 16]
+
+    slews = ['FAST', 'SLOW']
+    pulls = ["NONE", "KEEPER", "PULLDOWN", "PULLUP"]
+
+    luts = lut_maker.LutMaker()
+
+    connects = io.StringIO()
+
+    tile_params = []
+    params = []
+    for idx, (tile, site) in enumerate(gen_sites()):
+        if idx == 0:
+            continue
+
+        p = {}
+        p['tile'] = tile
+        p['site'] = site
+        p['ilogic_loc'] = site.replace('IOB', 'ILOGIC')
+        p['ologic_loc'] = site.replace('IOB', 'OLOGIC')
+        p['idelay_loc'] = site.replace('IOB', 'IDELAY')
+        p['IOSTANDARD'] = verilog.quote(iostandard)
+        p['PULLTYPE'] = verilog.quote(random.choice(pulls))
+        p['DRIVE'] = random.choice(drives)
+        p['SLEW'] = verilog.quote(random.choice(slews))
+
+        p['pad_wire'] = 'dio[{}]'.format(idx - 1)
+        p['owire'] = 'do_buf[{}]'.format(idx - 1)
+        p['iwire'] = 'di_buf[{}]'.format(idx - 1)
+        p['twire'] = 't[{}]'.format(idx - 1)
+
+        params.append(p)
+        tile_params.append(
+            (
+                tile, site, p['pad_wire'], iostandard, p['DRIVE'],
+                verilog.unquote(p['SLEW']) if p['SLEW'] else None,
+                verilog.unquote(p['PULLTYPE'])))
+
+    write_params(tile_params)
+
+    print(
+        '''
+`define N_DI {n_di}
+
+module top(input clk, inout wire [`N_DI-1:0] dio);
+    wire [`N_DI-1:0] di_buf;
+    wire [`N_DI-1:0] do_buf;
+    wire [`N_DI-1:0] t;
+
+    wire clk_BUFG1;
+    wire clk_BUFG2;
+    wire clk_BUFG3;
+    wire clk_BUFG4;
+
+    (* KEEP, DONT_TOUCH  *)
+    BUFG bufg1(
+        .O(clk_BUFG1)
+        );
+    (* KEEP, DONT_TOUCH  *)
+    BUFG bufg2(
+        .O(clk_BUFG2)
+        );
+    (* KEEP, DONT_TOUCH  *)
+    BUFG bufg3(
+        .O(clk_BUFG3)
+        );
+    (* KEEP, DONT_TOUCH  *)
+    BUFG bufg4(
+        .O(clk_BUFG4)
+        );
+    '''.format(n_di=idx))
+
+    # Always output a LUT6 to make placer happy.
+    print(
+        '''
+        (* KEEP, DONT_TOUCH *)
+        LUT6 dummy_lut();
+        ''')
+
+    any_idelay = False
+
+    for p in params:
+        print(
+            '''
+        wire iddr_d_{site};
+
+        (* KEEP, DONT_TOUCH, LOC = "{site}" *)
+        IOBUF #(
+            .IOSTANDARD({IOSTANDARD})
+        ) ibuf_{site} (
+            .IO({pad_wire}),
+            .I({owire}),
+            .O({iwire}),
+            .T({twire})
+            );
+            '''.format(**p),
+            file=connects)
+
+        p['use_iserdese2'] = random.randint(0, 1)
+        if p['use_iserdese2']:
+            use_iserdese2(p, luts, connects)
+        else:
+            use_direct_and_iddr(p, luts, connects)
+
+        if p['iddr_mux_config'] == 'idelay' or p['mux_config'] == 'idelay':
+            any_idelay = True
+
+    if any_idelay:
+        print("""
+    (* KEEP, DONT_TOUCH *)
+    IDELAYCTRL();""")
+
+    for l in luts.create_wires_and_luts():
+        print(l)
+
+    print(connects.getvalue())
+
+    print("endmodule")
+
+    with open('params.jl', 'w') as f:
+        json.dump(params, f, indent=2)
+
+
+if __name__ == '__main__':
+    run()

fuzzers/035a-iob18-idelay/top.py

@@ -31,7 +31,9 @@ def gen_sites():
             continue
         tile_list.append(tile_name)
 
-    get_xy = util.create_xy_fun('RIOB18_')
+    # Virtex-7 exposes both L- and R-side IOB18 tiles (kintex7's ROI only had
+    # the R side), so match either prefix when extracting the (X,Y) sort key.
+    get_xy = util.create_xy_fun('[LR]IOB18_')
     tile_list.sort(key=get_xy)
 
     for iob_tile_name in tile_list:

fuzzers/035a-iob18-odelay/generate.tcl

@@ -22,6 +22,10 @@ set_property IS_ENABLED 0 [get_drc_checks {REQP-84}]
 set_property IS_ENABLED 0 [get_drc_checks {REQP-85}]
 set_property IS_ENABLED 0 [get_drc_checks {REQP-87}]
 set_property IS_ENABLED 0 [get_drc_checks {REQP-85}]
+# ODELAY VAR_LOAD/VAR_LOAD_PIPE leaves CNTVALUEIN intentionally unconnected for
+# fuzzing; Vivado 2020.1 enforces this via REQP-135 (the IDELAY equivalents
+# REQP-79/81/.. are already disabled above, which is why the idelay fuzzer passes).
+set_property IS_ENABLED 0 [get_drc_checks {REQP-135}]
 set_property IS_ENABLED 0 [get_drc_checks {AVAL-28}]
 
 place_design

fuzzers/035a-iob18-odelay/top.py

@@ -31,7 +31,9 @@ def gen_sites():
             continue
         tile_list.append(tile_name)
 
-    get_xy = util.create_xy_fun('RIOB18_')
+    # Virtex-7 exposes both L- and R-side IOB18 tiles (kintex7's ROI only had
+    # the R side), so match either prefix when extracting the (X,Y) sort key.
+    get_xy = util.create_xy_fun('[LR]IOB18_')
     tile_list.sort(key=get_xy)
 
     for iob_tile_name in tile_list:

fuzzers/035b-iob-iserdes/Makefile

@@ -40,7 +40,7 @@ pushdb: build/segbits_rioi.db
 	${XRAY_MERGEDB} mask_rioi3 build/mask_xioi3.db
 	${XRAY_MERGEDB} mask_rioi3_tbytesrc build/mask_xioi3.db
 	${XRAY_MERGEDB} mask_rioi3_tbyteterm build/mask_xioi3.db
-ifeq ($(XRAY_DATABASE), $(filter ${XRAY_DATABASE}, kintex7 zynq7))
+ifneq (,$(filter $(XRAY_DATABASE),kintex7 zynq7 virtex7))
 	${XRAY_MERGEDB} rioi build/segbits_rioi.db
 	${XRAY_MERGEDB} rioi_tbytesrc build/segbits_rioi.db
 	${XRAY_MERGEDB} rioi_tbyteterm build/segbits_rioi.db

fuzzers/035b-iob18-iserdes/Makefile

@@ -0,0 +1,44 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+#
+# IOB18 (HP-bank) ISERDES fuzzer for Virtex-7.  The kintex7 035b-iob-iserdes
+# fuzzer targets IOB33/HR sites that do not exist on this part, so its RIOI
+# ISERDES results were transplanted.  This variant places ISERDESE2 on real
+# IOB18 sites on BOTH the L and R columns and measures the ISERDES config bits
+# directly, merging to lioi and rioi (segmaker emits the IOI. prefix, which
+# mergedb rewrites per side).
+N := 40
+include ../fuzzer.mk
+
+database: build/segbits_iob18_iserdes.db
+
+build/segbits_iob18_iserdes.rdb: $(SPECIMENS_OK)
+	${XRAY_SEGMATCH} -c 20 -m 1 -M 1 -o build/segbits_iob18_iserdes.rdb2 $$(find -name segdata_*.txt)
+	# Keep only ISERDES-related solutions (the rest belong to 035-iob18-ilogic).
+	grep -e ".ISERDES." build/segbits_iob18_iserdes.rdb2 > $@
+	grep -e ".IDDR.IN_USE." build/segbits_iob18_iserdes.rdb2 >> $@ || true
+
+build/segbits_iob18_iserdes.db: build/segbits_iob18_iserdes.rdb
+	${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --groups tag_groups.txt --seg-fn-in $^ --seg-fn-out $@
+	${XRAY_MASKMERGE} build/mask_iob18_iserdes.db $$(find -name segdata_*.txt)
+
+pushdb:
+	${XRAY_MERGEDB} lioi build/segbits_iob18_iserdes.db
+	${XRAY_MERGEDB} lioi_tbytesrc build/segbits_iob18_iserdes.db
+	${XRAY_MERGEDB} lioi_tbyteterm build/segbits_iob18_iserdes.db
+	${XRAY_MERGEDB} rioi build/segbits_iob18_iserdes.db
+	${XRAY_MERGEDB} rioi_tbytesrc build/segbits_iob18_iserdes.db
+	${XRAY_MERGEDB} rioi_tbyteterm build/segbits_iob18_iserdes.db
+	${XRAY_MERGEDB} mask_lioi build/mask_iob18_iserdes.db
+	${XRAY_MERGEDB} mask_lioi_tbytesrc build/mask_iob18_iserdes.db
+	${XRAY_MERGEDB} mask_lioi_tbyteterm build/mask_iob18_iserdes.db
+	${XRAY_MERGEDB} mask_rioi build/mask_iob18_iserdes.db
+	${XRAY_MERGEDB} mask_rioi_tbytesrc build/mask_iob18_iserdes.db
+	${XRAY_MERGEDB} mask_rioi_tbyteterm build/mask_iob18_iserdes.db
+
+.PHONY: database pushdb

fuzzers/035b-iob18-iserdes/generate.py

@@ -0,0 +1,284 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+import json
+
+from prjxray.segmaker import Segmaker
+from prjxray import util
+from prjxray import verilog
+
+iface_types = [
+    "NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"
+]
+
+data_rates = ["SDR", "DDR"]
+
+data_widths = {
+    "SDR": [2, 3, 4, 5, 6, 7, 8],
+    "DDR": [4, 6, 8, 10, 14],
+}
+
+
+def run():
+
+    segmk = Segmaker("design.bits")
+
+    # Load tags
+    with open("params.json", "r") as fp:
+        data = json.load(fp)
+
+    loc_to_tile_site_map = {}
+
+    # Output tags
+    for param_list in data:
+        for params in param_list:
+            loc = verilog.unquote(params["SITE_LOC"])
+
+            get_xy = util.create_xy_fun('IOB_')
+            x, y = get_xy(loc.replace("ILOGIC", "IOB"))
+
+            loc_to_tile_site_map[loc] = params["TILE_NAME"] + ".IOB_Y%d" % (
+                y % 2)
+
+            # Site not used at all
+            if not params["IS_USED"]:
+
+                segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", 0)
+
+                segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 0)
+                segmk.add_site_tag(loc, "ISERDES.IN_USE", 0)
+                segmk.add_site_tag(loc, "IDDR.IN_USE", 0)
+
+                segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0)
+                segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0)
+
+                for i in iface_types:
+                    if i == "NETWORKING":
+                        for j in data_rates:
+                            for k in data_widths[j]:
+                                tag = "ISERDES.%s.%s.W%s" % (i, j, k)
+                                segmk.add_site_tag(loc, tag, 0)
+                    else:
+                        segmk.add_site_tag(loc, "ISERDES.%s.DDR.W4" % i, 0)
+
+                segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 0)
+                segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 0)
+
+                for i in range(1, 4 + 1):
+                    segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0)
+
+                for i in range(1, 4 + 1):
+                    segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0)
+
+    #            segmk.add_site_tag(loc, "ISERDES.IS_CLKB_INVERTED", 0)
+    #            segmk.add_site_tag(loc, "ISERDES.IS_CLK_INVERTED", 1)
+
+                segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0)
+                segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0)
+
+                segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0)
+                segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1)
+                segmk.add_site_tag(loc, "IDELMUXE3.P0", 0)
+                segmk.add_site_tag(loc, "IDELMUXE3.P1", 1)
+
+                segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0)
+
+            # Site used as ISERDESE2
+            elif verilog.unquote(params["BEL_TYPE"]) == "ISERDESE2":
+
+                segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 1)
+                segmk.add_site_tag(loc, "ISERDES.IN_USE", 1)
+
+                if "SHIFTOUT_USED" in params:
+                    if params["CHAINED"]:
+                        value = params["SHIFTOUT_USED"]
+                        segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", value)
+
+                if "SERDES_MODE" in params:
+                    value = verilog.unquote(params["SERDES_MODE"])
+                    if value == "MASTER":
+                        segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 1)
+                        segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0)
+                    if value == "SLAVE":
+                        segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0)
+                        segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1)
+
+                iface_type = verilog.unquote(params["INTERFACE_TYPE"])
+                data_rate = verilog.unquote(params["DATA_RATE"])
+                data_width = int(params["DATA_WIDTH"])
+
+                for i in iface_types:
+                    if i == "NETWORKING":
+                        for j in data_rates:
+                            for k in data_widths[j]:
+                                tag = "ISERDES.%s.%s.W%s" % (i, j, k)
+
+                                if i == iface_type:
+                                    if j == data_rate:
+                                        if k == data_width:
+                                            segmk.add_site_tag(loc, tag, 1)
+                    else:
+                        if i == iface_type:
+                            segmk.add_site_tag(loc, "ISERDES.%s.DDR.W4" % i, 1)
+
+                if "NUM_CE" in params:
+                    value = params["NUM_CE"]
+                    if value == 1:
+                        segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 1)
+                        segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 0)
+                    if value == 2:
+                        segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 0)
+                        segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 1)
+
+                for i in range(1, 4 + 1):
+                    if ("INIT_Q%d" % i) in params:
+                        segmk.add_site_tag(
+                            loc, "IFF.ZINIT_Q%d" % i,
+                            not params["INIT_Q%d" % i])
+
+                for i in range(1, 4 + 1):
+                    if ("SRVAL_Q%d" % i) in params:
+                        segmk.add_site_tag(
+                            loc, "IFF.ZSRVAL_Q%d" % i,
+                            not params["SRVAL_Q%d" % i])
+
+                for inv in ["CLK", "CLKB", "OCLK", "OCLKB", "CLKDIV",
+                            "CLKDIVP"]:
+                    if "IS_{}_INVERTED".format(inv) in params:
+                        segmk.add_site_tag(
+                            loc, "ISERDES.INV_{}".format(inv),
+                            params["IS_{}_INVERTED".format(inv)])
+                        segmk.add_site_tag(
+                            loc, "ISERDES.ZINV_{}".format(inv),
+                            not params["IS_{}_INVERTED".format(inv)])
+
+                if "DYN_CLKDIV_INV_EN" in params:
+                    value = verilog.unquote(params["DYN_CLKDIV_INV_EN"])
+                    segmk.add_site_tag(
+                        loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE"))
+                if "DYN_CLK_INV_EN" in params:
+                    value = verilog.unquote(params["DYN_CLK_INV_EN"])
+                    segmk.add_site_tag(
+                        loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE"))
+
+                # This parameter actually controls muxes used both in ILOGIC and
+                # ISERDES mode.
+                if "IOBDELAY" in params:
+                    value = verilog.unquote(params["IOBDELAY"])
+                    if value == "NONE":
+                        segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0)
+                        segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1)
+                        segmk.add_site_tag(loc, "IDELMUXE3.P0", 0)
+                        segmk.add_site_tag(loc, "IDELMUXE3.P1", 1)
+                    if value == "IBUF":
+                        segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0)
+                        segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1)
+                        segmk.add_site_tag(loc, "IDELMUXE3.P0", 1)
+                        segmk.add_site_tag(loc, "IDELMUXE3.P1", 0)
+                    if value == "IFD":
+                        segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1)
+                        segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0)
+                        segmk.add_site_tag(loc, "IDELMUXE3.P0", 0)
+                        segmk.add_site_tag(loc, "IDELMUXE3.P1", 1)
+                    if value == "BOTH":
+                        segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1)
+                        segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0)
+                        segmk.add_site_tag(loc, "IDELMUXE3.P0", 1)
+                        segmk.add_site_tag(loc, "IDELMUXE3.P1", 0)
+
+                if "OFB_USED" in params:
+                    value = verilog.unquote(params["OFB_USED"])
+                    segmk.add_site_tag(
+                        loc, "ISERDES.OFB_USED", int(value == "TRUE"))
+
+            # Site used as IDDR
+            elif verilog.unquote(params["BEL_TYPE"]) in ["IDDR",
+                                                         "IDDR_NO_CLK"]:
+                segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 1)
+                segmk.add_site_tag(loc, "IDDR.IN_USE", 1)
+                segmk.add_site_tag(loc, "ISERDES.IN_USE", 0)
+
+                if "DDR_CLK_EDGE" in params:
+                    value = verilog.unquote(params["DDR_CLK_EDGE"])
+                    segmk.add_site_tag(
+                        loc, "IFF.DDR_CLK_EDGE.OPPOSITE_EDGE",
+                        int(value == "OPPOSITE_EDGE"))
+                    segmk.add_site_tag(
+                        loc, "IFF.DDR_CLK_EDGE.SAME_EDGE",
+                        int(value == "SAME_EDGE"))
+                    segmk.add_site_tag(
+                        loc, "IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED",
+                        int(value == "SAME_EDGE_PIPELINED"))
+
+                if "SRTYPE" in params:
+                    value = verilog.unquote(params["SRTYPE"])
+                    if value == "ASYNC":
+                        segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 1)
+                        segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 0)
+                    if value == "SYNC":
+                        segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 0)
+                        segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 1)
+
+                if "IDELMUX" in params:
+                    if params["IDELMUX"] == 1:
+                        segmk.add_site_tag(loc, "IDELMUXE3.P0", 1)
+                        segmk.add_site_tag(loc, "IDELMUXE3.P1", 0)
+                    else:
+                        segmk.add_site_tag(loc, "IDELMUXE3.P0", 0)
+                        segmk.add_site_tag(loc, "IDELMUXE3.P1", 1)
+
+                if "IFFDELMUX" in params:
+                    if params["IFFDELMUX"] == 1:
+                        segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1)
+                        segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0)
+                    else:
+                        segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0)
+                        segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1)
+
+                for inv in ["C", "D"]:
+                    if "IS_{}_INVERTED".format(inv) in params:
+                        segmk.add_site_tag(
+                            loc, "INV_{}".format(inv),
+                            params["IS_{}_INVERTED".format(inv)])
+                        segmk.add_site_tag(
+                            loc, "ZINV_{}".format(inv),
+                            not params["IS_{}_INVERTED".format(inv)])
+
+                segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 1)
+                segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 0)
+
+            # Should not happen
+            else:
+                print("Unknown BEL_TYPE '{}'".format(params["BEL_TYPE"]))
+                exit(-1)
+
+    # Write segments and tags for later check
+    def_tags = {t: 0 for d in segmk.site_tags.values() for t in d.keys()}
+
+    with open("tags.json", "w") as fp:
+        tags = {}
+        for l, d in segmk.site_tags.items():
+            d1 = dict(def_tags)
+            d1.update({k: int(v) for k, v in d.items()})
+            tags[loc_to_tile_site_map[l]] = d1
+
+        json.dump(tags, fp, sort_keys=True, indent=1)
+
+    def bitfilter(frame_idx, bit_idx):
+        if frame_idx < 26 or frame_idx > 29:
+            return False
+        return True
+
+    segmk.compile(bitfilter=bitfilter)
+    segmk.write()
+
+
+if __name__ == "__main__":
+    run()

fuzzers/035b-iob18-iserdes/generate.tcl

@@ -0,0 +1,45 @@
+# Copyright (C) 2017-2022  The Project X-Ray Authors
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+create_project -force -part $::env(XRAY_PART) design design
+read_verilog top.v
+synth_design -top top
+
+set_property CFGBVS GND [current_design]
+set_property CONFIG_VOLTAGE 1.8 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
+
+set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
+set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-79}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-81}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-84}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-85}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-87}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-85}]
+set_property IS_ENABLED 0 [get_drc_checks {AVAL-28}]
+# ISERDES/ILOGIC fuzzer deliberately builds "invalid" clocking and D-inversion
+# mux configs to observe their bits; suppress the DRCs that would block bitgen.
+set_property IS_ENABLED 0 [get_drc_checks {REQP-105}]
+set_property IS_ENABLED 0 [get_drc_checks {PDRC-26}]
+set_property IS_ENABLED 0 [get_drc_checks {PDRC-158}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-1580}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-1581}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-1582}]
+# ISERDESE2-specific DRCs (CLK/CLKDIV topology) the iserdes fuzzer must bypass.
+set_property IS_ENABLED 0 [get_drc_checks {NDRV-1}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-98}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-103}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-109}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-111}]
+
+place_design
+route_design
+
+write_checkpoint -force design.dcp
+write_bitstream -force design.bit

fuzzers/035b-iob18-iserdes/tag_groups.txt

@@ -0,0 +1,11 @@
+IOI.ILOGIC_Y0.ISERDES.MEMORY.DDR.W4 IOI.ILOGIC_Y0.ISERDES.MEMORY_DDR.W.DDR.W4 IOI.ILOGIC_Y0.ISERDES.MEMORY_QDR.DDR.W4 IOI.ILOGIC_Y0.ISERDES.NETWORKING.DDR.W10 IOI.ILOGIC_Y0.ISERDES.NETWORKING.DDR.W14 IOI.ILOGIC_Y0.ISERDES.NETWORKING.DDR.W4 IOI.ILOGIC_Y0.ISERDES.NETWORKING.DDR.W6 IOI.ILOGIC_Y0.ISERDES.NETWORKING.DDR.W8 IOI.ILOGIC_Y0.ISERDES.NETWORKING.SDR.W2 IOI.ILOGIC_Y0.ISERDES.NETWORKING.SDR.W3 IOI.ILOGIC_Y0.ISERDES.NETWORKING.SDR.W4 IOI.ILOGIC_Y0.ISERDES.NETWORKING.SDR.W5 IOI.ILOGIC_Y0.ISERDES.NETWORKING.SDR.W6 IOI.ILOGIC_Y0.ISERDES.NETWORKING.SDR.W7 IOI.ILOGIC_Y0.ISERDES.NETWORKING.SDR.W8 IOI.ILOGIC_Y0.ISERDES.OVERSAMPLE.DDR.W4
+
+IOI.ILOGIC_Y0.ISERDES.MODE.MASTER IOI.ILOGIC_Y0.ISERDES.MODE.SLAVE
+
+IOI.ILOGIC_Y0.ISERDES.NUM_CE.N1 IOI.ILOGIC_Y0.ISERDES.NUM_CE.N2
+
+IOI.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 IOI.ILOGIC_Y1.ISERDES.MEMORY_DDR.W.DDR.W4 IOI.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 IOI.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 IOI.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 IOI.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 IOI.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 IOI.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 IOI.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 IOI.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 IOI.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 IOI.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 IOI.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 IOI.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 IOI.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 IOI.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4
+
+IOI.ILOGIC_Y1.ISERDES.MODE.MASTER IOI.ILOGIC_Y1.ISERDES.MODE.SLAVE
+
+IOI.ILOGIC_Y1.ISERDES.NUM_CE.N1 IOI.ILOGIC_Y1.ISERDES.NUM_CE.N2

fuzzers/035b-iob18-iserdes/top.py

@@ -0,0 +1,496 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+import os, random
+random.seed(int(os.getenv("SEED"), 16))
+
+import json
+
+from prjxray import util
+from prjxray import verilog
+from prjxray.db import Database
+
+# =============================================================================
+
+
+def gen_sites():
+    db = Database(util.get_db_root(), util.get_part())
+    grid = db.grid()
+
+    tile_list = []
+    for tile_name in sorted(grid.tiles()):
+        if "IOB18" not in tile_name or "SING" in tile_name:
+            continue
+        tile_list.append(tile_name)
+
+    get_xy = util.create_xy_fun('[LR]IOB18_')
+    tile_list.sort(key=get_xy)
+
+    for iob_tile_name in tile_list:
+        iob_gridinfo = grid.gridinfo_at_loc(
+            grid.loc_of_tilename(iob_tile_name))
+
+        iob33s = [k for k, v in iob_gridinfo.sites.items() if v == "IOB18S"][0]
+        iob33m = [k for k, v in iob_gridinfo.sites.items() if v == "IOB18M"][0]
+
+        top_sites = {
+            "IOB": iob33m,
+            "ILOGIC": iob33m.replace("IOB", "ILOGIC"),
+            "IDELAY": iob33m.replace("IOB", "IDELAY"),
+        }
+
+        bot_sites = {
+            "IOB": iob33s,
+            "ILOGIC": iob33s.replace("IOB", "ILOGIC"),
+            "IDELAY": iob33s.replace("IOB", "IDELAY"),
+        }
+
+        yield iob_tile_name, top_sites, bot_sites
+
+
+def gen_iserdes(loc):
+
+    # Site params
+    params = {
+        "SITE_LOC": verilog.quote(loc),
+        "USE_IDELAY": random.randint(0, 1),
+        "BEL_TYPE": verilog.quote("ISERDESE2"),
+        "INIT_Q1": random.randint(0, 1),
+        "INIT_Q2": random.randint(0, 1),
+        "INIT_Q3": random.randint(0, 1),
+        "INIT_Q4": random.randint(0, 1),
+        "SRVAL_Q1": random.randint(0, 1),
+        "SRVAL_Q2": random.randint(0, 1),
+        "SRVAL_Q3": random.randint(0, 1),
+        "SRVAL_Q4": random.randint(0, 1),
+        "NUM_CE": random.randint(1, 2),
+
+        # The following one shows negative correlation (0 - not inverted)
+        "IS_D_INVERTED": random.randint(0, 1),
+
+        # No bits were found for parameters below
+        "IS_OCLKB_INVERTED": random.randint(0, 1),
+        "IS_OCLK_INVERTED": random.randint(0, 1),
+        "IS_CLKDIVP_INVERTED": random.randint(0, 1),
+        "IS_CLKDIV_INVERTED": random.randint(0, 1),
+        "IS_CLKB_INVERTED": random.randint(0, 1),
+        "IS_CLK_INVERTED": random.randint(0, 1),
+        "DYN_CLKDIV_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])),
+        "DYN_CLK_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])),
+        "IOBDELAY": verilog.quote(
+            random.choice(["NONE", "IBUF", "IFD", "BOTH"])),
+        "OFB_USED": verilog.quote(
+            random.choice(["TRUE"] + ["FALSE"] * 9)),  # Force more FALSEs
+    }
+
+    iface_type = random.choice(
+        ["NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"])
+    data_rate = random.choice(["SDR", "DDR"])
+    serdes_mode = random.choice(["MASTER", "SLAVE"])
+
+    params["INTERFACE_TYPE"] = verilog.quote(iface_type)
+    params["DATA_RATE"] = verilog.quote(data_rate)
+    params["SERDES_MODE"] = verilog.quote(serdes_mode)
+
+    # Networking mode
+    if iface_type == "NETWORKING":
+        data_widths = {
+            "SDR": [2, 3, 4, 5, 6, 7, 8],
+            "DDR": [4, 6, 8, 10, 14],
+        }
+        params["DATA_WIDTH"] = random.choice(data_widths[data_rate])
+
+    # Others
+    else:
+        params["DATA_WIDTH"] = 4
+
+    if verilog.unquote(params["OFB_USED"]) == "TRUE":
+        params["IOBDELAY"] = verilog.quote("NONE")
+
+    return params
+
+
+def gen_iddr(loc):
+
+    # Site params
+    params = {
+        "SITE_LOC":
+        verilog.quote(loc),
+        "USE_IDELAY":
+        random.randint(0, 1),
+        "BEL_TYPE":
+        verilog.quote(random.choice(["IDDR", "IDDR_NO_CLK"])),
+        "INIT_Q1":
+        random.randint(0, 1),
+        "INIT_Q2":
+        random.randint(0, 1),
+        "SRTYPE":
+        verilog.quote(random.choice(["ASYNC", "SYNC"])),
+        "DDR_CLK_EDGE":
+        verilog.quote(
+            random.choice(
+                ["OPPOSITE_EDGE", "SAME_EDGE", "SAME_EDGE_PIPELINED"])),
+        "CE1USED":
+        random.randint(0, 1),
+        "SR_MODE":
+        verilog.quote(random.choice(["NONE", "SET", "RST"])),
+        "IS_C_INVERTED":
+        random.randint(0, 1),
+        "IS_D_INVERTED":
+        random.randint(0, 1),
+    }
+
+    if params["USE_IDELAY"]:
+        params["IDELMUX"] = random.randint(0, 1)
+        params["IFFDELMUX"] = random.randint(0, 1)
+    else:
+        params["IDELMUX"] = 0
+        params["IFFDELMUX"] = 0
+
+    return params
+
+
+def run():
+
+    # Get all [LR]IOI3 tiles
+    tiles = list(gen_sites())
+
+    # Header
+    print("// Tile count: %d" % len(tiles))
+    print("// Seed: '%s'" % os.getenv("SEED"))
+    print(
+        '''
+module top (
+  (* CLOCK_BUFFER_TYPE = "NONE" *)
+  input  wire clk1,
+  (* CLOCK_BUFFER_TYPE = "NONE" *)
+  input  wire clk2,
+  input  wire ce,
+  input  wire rst,
+  input  wire [{N}:0] di,
+  output wire [{N}:0] do
+);
+
+wire [{N}:0] di_buf;
+wire [{N}:0] do_buf;
+
+// IDELAYCTRL
+(* KEEP, DONT_TOUCH *)
+IDELAYCTRL idelayctrl();
+    '''.format(**{"N": len(tiles) - 1}))
+
+    # LOCes IOBs
+    data = []
+    for i, sites in enumerate(tiles):
+        tile_name = sites[0]
+
+        # Use site
+        if random.randint(0, 19) > 0:  # Use more often
+
+            # Top sites
+            if random.randint(0, 1):
+                this_sites = sites[1]
+                other_sites = sites[2]
+            # Bottom sites
+            else:
+                this_sites = sites[2]
+                other_sites = sites[1]
+
+            # Generate cell
+            bel_types = ["IDDR", "ISERDESE2"]
+            bel_type = bel_types[int(
+                random.randint(0, 2) > 0)]  # ISERDES more often
+            if bel_type == "ISERDESE2":
+                params = gen_iserdes(this_sites["ILOGIC"])
+            if bel_type == "IDDR":
+                params = gen_iddr(this_sites["ILOGIC"])
+
+            params["IDELAY_LOC"] = verilog.quote(this_sites["IDELAY"])
+            params["IS_USED"] = 1
+
+            # Instantiate the cell
+            print('')
+            print('// This : ' + " ".join(this_sites.values()))
+            print('// Other: ' + " ".join(other_sites.values()))
+            print('(* LOC="%s", KEEP, DONT_TOUCH *)' % this_sites["IOB"])
+            print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i))
+            print('(* LOC="%s", KEEP, DONT_TOUCH *)' % other_sites["IOB"])
+            print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i))
+
+            clk1_conn = random.choice(["clk1", ""])
+
+            param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items())
+            print(
+                'ilogic_single #(%s) ilogic_%03d (.clk1(%s), .clk2(clk2), .ce(ce), .rst(rst), .I(di_buf[%3d]), .O(do_buf[%3d]));'
+                % (param_str, i, clk1_conn, i, i))
+
+            params["CHAINED"] = 0
+            params["TILE_NAME"] = tile_name
+
+            # Params for the second site
+            other_params = {
+                "TILE_NAME": tile_name,
+                "SITE_LOC": verilog.quote(other_sites["ILOGIC"]),
+                "IDELAY_LOC": verilog.quote(other_sites["IDELAY"]),
+                "IS_USED": 0,
+            }
+
+            # Append to data list
+            data.append([params, other_params])
+
+        # Don't use sites
+        else:
+
+            params_list = [
+                {
+                    "TILE_NAME": tile_name,
+                    "SITE_LOC": verilog.quote(sites[1]["ILOGIC"]),
+                    "IDELAY_LOC": verilog.quote(sites[1]["IDELAY"]),
+                    "IS_USED": 0,
+                },
+                {
+                    "TILE_NAME": tile_name,
+                    "SITE_LOC": verilog.quote(sites[2]["ILOGIC"]),
+                    "IDELAY_LOC": verilog.quote(sites[2]["IDELAY"]),
+                    "IS_USED": 0,
+                }
+            ]
+
+            data.append(params_list)
+
+    # Store params
+    with open("params.json", "w") as fp:
+        json.dump(data, fp, sort_keys=True, indent=1)
+
+    print(
+        '''
+endmodule
+
+(* KEEP, DONT_TOUCH *)
+module ilogic_single(
+  input  wire clk1,
+  input  wire clk2,
+  input  wire ce,
+  input  wire rst,
+  input  wire I,
+  output wire O,
+  input  wire [1:0] shiftin,
+  output wire [1:0] shiftout
+);
+
+parameter SITE_LOC = "";
+parameter IS_USED = 1;
+parameter BEL_TYPE = "ISERDESE2";
+parameter IDELAY_LOC = "";
+parameter USE_IDELAY = 0;
+parameter IDELMUX = 0;
+parameter IFFDELMUX = 0;
+parameter INTERFACE_TYPE = "NETWORKING";
+parameter DATA_RATE = "DDR";
+parameter DATA_WIDTH = 4;
+parameter SERDES_MODE = "MASTER";
+parameter NUM_CE = 2;
+parameter INIT_Q1 = 0;
+parameter INIT_Q2 = 0;
+parameter INIT_Q3 = 0;
+parameter INIT_Q4 = 0;
+parameter SRVAL_Q1 = 0;
+parameter SRVAL_Q2 = 0;
+parameter SRVAL_Q3 = 0;
+parameter SRVAL_Q4 = 0;
+parameter IS_D_INVERTED = 0;
+parameter IS_OCLK_INVERTED = 0;
+parameter IS_OCLKB_INVERTED = 0;
+parameter IS_CLK_INVERTED = 0;
+parameter IS_CLKB_INVERTED = 0;
+parameter IS_CLKDIV_INVERTED = 0;
+parameter IS_CLKDIVP_INVERTED = 0;
+parameter DYN_CLKDIV_INV_EN = "FALSE";
+parameter DYN_CLK_INV_EN = "FALSE";
+parameter IOBDELAY = "NONE";
+parameter OFB_USED = "FALSE";
+parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
+parameter SRTYPE = "ASYNC";
+parameter CE1USED = 0;
+parameter SR_MODE = "NONE";
+parameter IS_C_INVERTED = 0;
+
+wire [8:0] x;
+wire ddly;
+
+(* KEEP, DONT_TOUCH *)
+generate if (IS_USED && USE_IDELAY) begin
+
+  // IDELAY
+  (* LOC=IDELAY_LOC, KEEP, DONT_TOUCH *)
+  IDELAYE2 idelay
+  (
+    .C(clk),
+    .REGRST(),
+    .LD(),
+    .CE(),
+    .INC(),
+    .CINVCTRL(),
+    .CNTVALUEIN(),
+    .IDATAIN(I),
+    .DATAIN(),
+    .LDPIPEEN(),
+    .DATAOUT(ddly),
+    .CNTVALUEOUT()
+  );
+
+end else begin
+
+  assign ddly = 0;
+
+end endgenerate
+
+(* KEEP, DONT_TOUCH *)
+generate if (IS_USED && BEL_TYPE == "ISERDESE2") begin
+
+  // ISERDES
+  (* LOC=SITE_LOC, KEEP, DONT_TOUCH *)
+  ISERDESE2 #
+  (
+  .INTERFACE_TYPE(INTERFACE_TYPE),
+  .DATA_RATE(DATA_RATE),
+  .DATA_WIDTH(DATA_WIDTH),
+  .SERDES_MODE(SERDES_MODE),
+  .NUM_CE(NUM_CE),
+  .IS_D_INVERTED(IS_D_INVERTED),
+  .IS_OCLK_INVERTED(IS_OCLK_INVERTED),
+  .IS_OCLKB_INVERTED(IS_OCLKB_INVERTED),
+  .IS_CLK_INVERTED(IS_CLK_INVERTED),
+  .IS_CLKB_INVERTED(IS_CLKB_INVERTED),
+  .IS_CLKDIV_INVERTED(IS_CLKDIV_INVERTED),
+  .IS_CLKDIVP_INVERTED(IS_CLKDIVP_INVERTED),
+  .INIT_Q1(INIT_Q1),
+  .INIT_Q2(INIT_Q2),
+  .INIT_Q3(INIT_Q3),
+  .INIT_Q4(INIT_Q4),
+  .SRVAL_Q1(SRVAL_Q1),
+  .SRVAL_Q2(SRVAL_Q2),
+  .SRVAL_Q3(SRVAL_Q3),
+  .SRVAL_Q4(SRVAL_Q4),
+  .DYN_CLKDIV_INV_EN(DYN_CLKDIV_INV_EN),
+  .DYN_CLK_INV_EN(DYN_CLK_INV_EN),
+  .IOBDELAY(IOBDELAY),
+  .OFB_USED(OFB_USED)
+  )
+  isedres
+  (
+  .D(I),
+  .DDLY(),
+  .OFB(),
+  //.TFB(),
+  .CE1(),
+  .CE2(),
+  .DYNCLKSEL(),
+  .CLK(clk1),
+  .CLKB(clk2),
+  .OCLK(),
+  .OCLKB(),
+  .DYNCLKDIVSEL(),
+  .CLKDIV(),
+  .CLKDIVP(),
+  .RST(),
+  .BITSLIP(),
+  .O(x[8]),
+  .Q1(x[0]),
+  .Q2(x[1]),
+  .Q3(x[2]),
+  .Q4(x[3]),
+  .Q5(x[4]),
+  .Q6(x[5]),
+  .Q7(x[6]),
+  .Q8(x[7]),
+  .SHIFTIN1(shiftin[0]),
+  .SHIFTIN2(shiftin[1]),
+  .SHIFTOUT1(shiftout[0]),
+  .SHIFTOUT2(shiftout[1])
+  );
+
+end else if (IS_USED && BEL_TYPE == "IDDR") begin
+
+  // IDDR
+  (* LOC=SITE_LOC, KEEP, DONT_TOUCH *)
+  IDDR #
+  (
+  .IS_C_INVERTED(IS_C_INVERTED),
+  .IS_D_INVERTED(IS_D_INVERTED),
+  .DDR_CLK_EDGE(DDR_CLK_EDGE),
+  .INIT_Q1(INIT_Q1),
+  .INIT_Q2(INIT_Q2),
+  .SRTYPE(SRTYPE)
+  )
+  iddr
+  (
+  .C(clk1),
+  .CE( (CE1USED) ? ce : 1'hx ),
+  .D( (IFFDELMUX) ? ddly : I  ),
+  .S( (SR_MODE == "SET") ? rst : 1'd0 ),
+  .R( (SR_MODE == "RST") ? rst : 1'd0 ),
+  .Q1(x[0]),
+  .Q2(x[1])
+  );
+
+  assign x[8] = (IDELMUX) ? ddly : I;
+  assign x[7:2] = 0;
+
+end else if (IS_USED && BEL_TYPE == "IDDR_NO_CLK") begin
+
+  // IDDR
+  (* LOC=SITE_LOC, KEEP, DONT_TOUCH *)
+  IDDR #
+  (
+  .IS_C_INVERTED(IS_C_INVERTED),
+  .IS_D_INVERTED(IS_D_INVERTED),
+  .DDR_CLK_EDGE(DDR_CLK_EDGE),
+  .INIT_Q1(INIT_Q1),
+  .INIT_Q2(INIT_Q2),
+  .SRTYPE(SRTYPE)
+  )
+  iddr
+  (
+  .C(),
+  .CE( (CE1USED) ? ce : 1'hx ),
+  .D( (IFFDELMUX) ? ddly : I  ),
+  .S( (SR_MODE == "SET") ? rst : 1'd0 ),
+  .R( (SR_MODE == "RST") ? rst : 1'd0 ),
+  .Q1(x[0]),
+  .Q2(x[1])
+  );
+
+  assign x[8] = (IDELMUX) ? ddly : I;
+  assign x[7:2] = 0;
+
+end else begin
+
+  assign x[0] = I;
+  assign x[1] = I;
+  assign x[2] = I;
+  assign x[3] = I;
+  assign x[4] = I;
+  assign x[5] = I;
+  assign x[6] = I;
+  assign x[7] = I;
+  assign x[8] = I;
+
+end endgenerate
+
+// Output
+assign O = |x;
+
+endmodule
+
+    ''')
+
+
+run()

fuzzers/036-iob18-ologic-sing/Makefile

@@ -0,0 +1,37 @@
+# Copyright (C) 2017-2022  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+# SING-row sibling of 036-iob18-ologic.  Generates OLOGIC stimulus
+# only on IOB18 sites within *_SING tiles, then bit-diffs into
+# segbits suitable for merging as lioi_sing / rioi_sing.  Without
+# this, fasm2frames emits "invalid word address" warnings when
+# nextpnr asks for OLOGIC features on SING-row LED IOBs (VC707
+# counter25 build hits this for led[?] @ LIOI_SING_X82Y51).
+
+# N=50: the sibling 036-iob18-ologic uses N=40 to resolve the OLOGIC_Y0
+# enum features (OMUX/OQUSED/OSERDES.DATA_RATE_TQ); SING needs at least as
+# many specimens or dbfixup drops them as unresolved/duplicate.
+N := 50
+include ../fuzzer.mk
+
+database: build/segbits_rioi_sing.db
+
+build/segbits_rioi_sing.rdb: $(SPECIMENS_OK)
+	${XRAY_SEGMATCH} -c 7 -o build/segbits_rioi_sing.rdb $$(find -name segdata_*)
+
+build/segbits_rioi_sing.db: build/segbits_rioi_sing.rdb
+	${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
+	${XRAY_MASKMERGE} build/mask_rioi_sing.db $$(find -name segdata_*)
+
+pushdb:
+	${XRAY_MERGEDB} rioi_sing build/segbits_rioi_sing.db
+	${XRAY_MERGEDB} lioi_sing build/segbits_rioi_sing.db
+	${XRAY_MERGEDB} mask_rioi_sing build/mask_rioi_sing.db
+	${XRAY_MERGEDB} mask_lioi_sing build/mask_rioi_sing.db
+
+.PHONY: database pushdb

fuzzers/036-iob18-ologic-sing/bits.dbf

@@ -0,0 +1,6 @@
+33_27 33_29
+32_36 32_34
+33_61 32_58 33_57
+32_6 32_2 33_5
+30_31 30_35 30_63 31_62 31_60 30_57 31_56 30_59 31_52 31_36
+31_0 30_1 30_3 31_6 30_7 31_4 30_11 31_28 31_32 30_29 30_27

fuzzers/036-iob18-ologic-sing/generate.py

@@ -0,0 +1,189 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2022  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+from prjxray.segmaker import Segmaker
+from prjxray import verilog
+import json
+
+# Set to true to enable additional tags useful for tracing bit toggles.
+DEBUG_FUZZER = False
+
+
+def bitfilter(frame, word):
+    return 30 <= frame and frame <= 33
+
+def handle_data_width(segmk, d):
+    if 'DATA_WIDTH' not in d:
+        return
+
+    site = d['ologic_loc']
+
+    data_rate = verilog.unquote(d['DATA_RATE_OQ'])
+    segmk.add_site_tag(
+        site, 'OSERDES.DATA_WIDTH.{}.W{}'.format(data_rate, d['DATA_WIDTH']),
+        1)
+
+
+def no_oserdes(segmk, site):
+    for mode in ['SDR', 'DDR']:
+        if mode == 'SDR':
+            widths = [2, 3, 4, 5, 6, 7, 8]
+        else:
+            assert mode == 'DDR'
+            widths = [4, 6, 8]
+
+        for opt in widths:
+            segmk.add_site_tag(
+                site, 'OSERDES.DATA_WIDTH.{}.W{}'.format(mode, opt), 0)
+
+
+def main():
+    print("Loading tags")
+    segmk = Segmaker("design.bits")
+
+    with open('params.jl', 'r') as f:
+        design = json.load(f)
+
+        for d in design:
+            site = d['ologic_loc']
+
+            handle_data_width(segmk, d)
+
+            segmk.add_site_tag(site, 'OSERDES.IN_USE', d['use_oserdese2'])
+
+            if d['use_oserdese2']:
+                segmk.add_site_tag(site, 'OQUSED', 1)
+
+                for opt in ['SDR', 'DDR']:
+                    segmk.add_site_tag(
+                        site, 'OSERDES.DATA_RATE_OQ.{}'.format(opt),
+                        verilog.unquote(d['DATA_RATE_OQ']) == opt)
+
+                data_rate_tq = verilog.unquote(d['DATA_RATE_TQ'])
+                segmk.add_site_tag(
+                    site, 'OSERDES.DATA_RATE_TQ.{}'.format(data_rate_tq), 1)
+                for opt in ['BUF', 'SDR', 'DDR']:
+                    segmk.add_site_tag(
+                        site, 'OSERDES.DATA_RATE_TQ.{}'.format(opt),
+                        opt == data_rate_tq)
+
+                for opt in ['SRVAL_OQ', 'SRVAL_TQ', 'INIT_OQ', 'INIT_TQ']:
+                    segmk.add_site_tag(site, opt, d[opt])
+                    segmk.add_site_tag(site, 'Z' + opt, 1 ^ d[opt])
+
+                for opt in ['CLK', 'CLKDIV']:
+                    if d['{}_USED'.format(opt)]:
+                        k = 'IS_{}_INVERTED'.format(opt)
+                        segmk.add_site_tag(site, k, d[k])
+                        segmk.add_site_tag(
+                            site, 'ZINV_{}'.format(opt), 1 ^ d[k])
+
+                if d['io']:
+                    for idx in range(4):
+                        k = 'IS_T{}_INVERTED'.format(idx + 1)
+                        segmk.add_site_tag(site, k, d[k])
+                        segmk.add_site_tag(
+                            site, 'ZINV_T{}'.format(idx + 1), 1 ^ d[k])
+
+                for idx in range(8):
+                    k = 'IS_D{}_INVERTED'.format(idx + 1)
+                    segmk.add_site_tag(site, k, d[k])
+                    segmk.add_site_tag(
+                        site, 'ZINV_D{}'.format(idx + 1), 1 ^ d[k])
+
+                for tristate_width in [1, 4]:
+                    segmk.add_site_tag(
+                        site,
+                        'OSERDES.TRISTATE_WIDTH.W{}'.format(tristate_width),
+                        d['TRISTATE_WIDTH'] == tristate_width)
+
+                for opt in ['MASTER', 'SLAVE']:
+                    segmk.add_site_tag(
+                        site, 'OSERDES.SERDES_MODE.{}'.format(opt),
+                        opt == verilog.unquote(d['OSERDES_MODE']))
+
+            if 'o_sr_used' in d:
+                if d['o_sr_used'] in ['S', 'R']:
+                    segmk.add_site_tag(site, 'ODDR.SRUSED', 1)
+                    segmk.add_site_tag(site, 'ODDR.ZSRUSED', 0)
+                else:
+                    assert d['o_sr_used'] == 'None'
+                    segmk.add_site_tag(site, 'ODDR.SRUSED', 0)
+                    segmk.add_site_tag(site, 'ODDR.ZSRUSED', 1)
+
+            if 't_sr_used' in d:
+                if d['t_sr_used'] in ['S', 'R']:
+                    segmk.add_site_tag(site, 'TDDR.SRUSED', 1)
+                    segmk.add_site_tag(site, 'TDDR.ZSRUSED', 0)
+                else:
+                    assert d['t_sr_used'] == 'None'
+                    segmk.add_site_tag(site, 'TDDR.SRUSED', 0)
+                    segmk.add_site_tag(site, 'TDDR.ZSRUSED', 1)
+
+            if d['oddr_mux_config'] == 'direct':
+                segmk.add_site_tag(site, 'ODDR_TDDR.IN_USE', 1)
+
+            if d['tddr_mux_config'] == 'direct':
+                segmk.add_site_tag(site, 'ODDR_TDDR.IN_USE', 1)
+
+            if d['oddr_mux_config'] == 'direct' and d[
+                    'tddr_mux_config'] == 'direct':
+                segmk.add_site_tag(site, 'ZINV_CLK', 1 ^ d['IS_CLK_INVERTED'])
+
+                if d['IS_CLK_INVERTED'] == 0:
+                    for opt in ['OPPOSITE_EDGE', 'SAME_EDGE']:
+                        segmk.add_site_tag(
+                            site, 'ODDR.DDR_CLK_EDGE.{}'.format(opt),
+                            verilog.unquote(d['ODDR_CLK_EDGE']) == opt)
+
+                segmk.add_site_tag(
+                    site, 'TDDR.DDR_CLK_EDGE.INV',
+                    d['ODDR_CLK_EDGE'] != d['TDDR_CLK_EDGE'])
+                segmk.add_site_tag(
+                    site, 'TDDR.DDR_CLK_EDGE.ZINV',
+                    d['ODDR_CLK_EDGE'] == d['TDDR_CLK_EDGE'])
+
+                if 'SRTYPE' in d:
+                    for opt in ['ASYNC', 'SYNC']:
+                        segmk.add_site_tag(
+                            site, 'OSERDES.SRTYPE.{}'.format(opt),
+                            verilog.unquote(d['SRTYPE']) == opt)
+
+                for opt in ['ASYNC', 'SYNC']:
+                    segmk.add_site_tag(
+                        site, 'OSERDES.TSRTYPE.{}'.format(opt),
+                        verilog.unquote(d['TSRTYPE']) == opt)
+
+            if not d['use_oserdese2']:
+                no_oserdes(segmk, site)
+                if d['oddr_mux_config'] == 'lut':
+                    segmk.add_site_tag(site, 'ODDR_TDDR.IN_USE', 0)
+                    segmk.add_site_tag(site, 'OMUX.D1', 1)
+                    segmk.add_site_tag(site, 'OQUSED', 1)
+                elif d['oddr_mux_config'] == 'direct':
+                    segmk.add_site_tag(site, 'OMUX.D1', 0)
+                elif d['oddr_mux_config'] == 'none' and not d['io']:
+                    segmk.add_site_tag(site, 'OQUSED', 0)
+
+            segmk.add_site_tag(site, 'TQUSED', d['io'])
+
+            if DEBUG_FUZZER:
+                for k in d:
+                    segmk.add_site_tag(
+                        site, 'param_' + k + '_' + str(d[k]).replace(
+                            ' ', '').replace('\n', ''), 1)
+
+    segmk.compile(bitfilter=bitfilter)
+    segmk.write(allow_empty=True)
+
+
+if __name__ == "__main__":
+    main()

fuzzers/036-iob18-ologic-sing/generate.tcl

@@ -0,0 +1,107 @@
+# Copyright (C) 2017-2022  The Project X-Ray Authors
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+source "$::env(XRAY_DIR)/utils/utils.tcl"
+
+proc make_io_pin_sites {} {
+    # get all possible IOB pins
+    foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] {
+        set site [get_sites -of_objects $pad]
+        if {[llength $site] == 0} {
+            continue
+        }
+        if [string match IOB18* [get_property SITE_TYPE $site]] {
+            dict append io_pin_sites $site $pad
+        }
+    }
+    return $io_pin_sites
+}
+
+proc load_pin_lines {} {
+    # IOB_X0Y103 clk input
+    # IOB_X0Y129 do[0] output
+
+    set fp [open "params.csv" r]
+    gets $fp line
+
+    set pin_lines {}
+    for {gets $fp line} {$line != ""} {gets $fp line} {
+        lappend pin_lines [split $line ","]
+    }
+    close $fp
+    return $pin_lines
+}
+
+proc loc_pins {} {
+    set pin_lines [load_pin_lines]
+    set io_pin_sites [make_io_pin_sites]
+
+    puts "Looping"
+    for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} {
+        set line [lindex $pin_lines $idx]
+        puts "$line"
+
+        set site_str [lindex $line 1]
+        set pin_str [lindex $line 2]
+        set iostandard [lindex $line 3]
+        set drive [lindex $line 4]
+        set slew [lindex $line 5]
+        set pulltype [lindex $line 6]
+
+        # Have: site
+        # Want: pin for site
+
+        set site [get_sites $site_str]
+        set pad_bel [get_bels -of_objects $site -filter {TYPE =~ PAD && NAME =~ IOB_*}]
+        # set port [get_ports -of_objects $site]
+        set port [get_ports $pin_str]
+        set tile [get_tiles -of_objects $site]
+
+        set pin [dict get $io_pin_sites $site]
+
+        set props {}
+        #lappend props PACKAGE_PIN $pin
+        lappend props IOSTANDARD $iostandard
+        lappend props PULLTYPE $pulltype
+
+        if {$drive != "None"} {
+            lappend props DRIVE $drive
+        }
+
+        if {$slew != "None"} {
+            lappend props SLEW $slew
+        }
+
+        puts $props
+
+        set_property -dict "$props" $port
+    }
+}
+
+proc run {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    loc_pins
+
+    set_property CFGBVS GND [current_design]
+    set_property CONFIG_VOLTAGE 1.8 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-79}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-144}]
+
+    write_checkpoint -force design_pre_place.dcp
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+}
+
+run

fuzzers/036-iob18-ologic-sing/top.py

@@ -0,0 +1,477 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2022  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+import json
+import io
+import os
+import random
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray import lut_maker
+from prjxray import verilog
+from prjxray.db import Database
+
+
+def gen_sites():
+    '''SING-row sibling of 036-iob18-ologic.  The original fuzzer
+    walks IOB18S/IOB18M (diff-pair main/secondary), which leaves
+    the IOB18 site type in *_SING tiles uncharacterised — OLOGIC
+    features at those tiles assemble against the regular tile's
+    bit-addresses and fasm2frames raises "invalid word address"
+    warnings.  This fuzzer's filter is the complement: only the
+    IOB18 site type in *_SING tiles.  Produces segbits that merge
+    into lioi_sing / rioi_sing.'''
+    db = Database(util.get_db_root(), util.get_part())
+    grid = db.grid()
+    for tile_name in sorted(grid.tiles()):
+        loc = grid.loc_of_tilename(tile_name)
+        gridinfo = grid.gridinfo_at_loc(loc)
+        if not gridinfo.tile_type.endswith("_SING"):
+            continue
+        for site_name, site_type in gridinfo.sites.items():
+            if site_type == 'IOB18':
+                yield tile_name, site_name
+
+
+def write_params(params):
+    pinstr = 'tile,site,pin,iostandard,drive,slew\n'
+    for vals in params:
+        pinstr += ','.join(map(str, vals)) + '\n'
+
+    open('params.csv', 'w').write(pinstr)
+
+
+def use_oserdese2(p, luts, connects):
+
+    p['oddr_mux_config'] = 'none'
+    p['tddr_mux_config'] = 'none'
+
+    p['DATA_RATE_OQ'] = verilog.quote(random.choice((
+        'SDR',
+        'DDR',
+    )))
+
+    p['DATA_RATE_TQ'] = verilog.quote(random.choice((
+        'BUF',
+        'SDR',
+        'DDR',
+    )))
+
+    if verilog.unquote(p['DATA_RATE_OQ']) == 'SDR':
+        data_widths = [2, 3, 4, 5, 6, 7, 8]
+    else:
+        data_widths = [4, 6, 8]
+
+    p['DATA_WIDTH'] = random.choice(data_widths)
+
+    if p['DATA_WIDTH'] == 4 and verilog.unquote(
+            p['DATA_RATE_OQ']) == 'DDR' and verilog.unquote(
+                p['DATA_RATE_TQ']) == 'DDR':
+        tristate_width = 4
+    else:
+        tristate_width = 1
+    p['SERDES_MODE'] = verilog.quote(random.choice(('MASTER', 'SLAVE')))
+
+    p['TRISTATE_WIDTH'] = tristate_width
+    p['OSERDES_MODE'] = verilog.quote(random.choice(('MASTER', 'SLAVE')))
+
+    if p['io']:
+        p['TFB'] = '.TFB(tfb_{site}),'.format(**p)
+        p['TQ'] = '.TQ({twire}),'.format(**p)
+        p['t1net'] = luts.get_next_output_net()
+        p['t2net'] = luts.get_next_output_net()
+        p['t3net'] = luts.get_next_output_net()
+        p['t4net'] = luts.get_next_output_net()
+        p['tcenet'] = luts.get_next_output_net()
+
+        for idx in range(4):
+            p['IS_T{}_INVERTED'.format(idx + 1)] = random.randint(0, 1)
+    else:
+        p['TFB'] = '.TFB(),'
+        p['TQ'] = '.TQ(),'
+        p['t1net'] = ''
+        p['t2net'] = ''
+        p['t3net'] = ''
+        p['t4net'] = ''
+        p['tcenet'] = ''
+
+        for idx in range(4):
+            p['IS_T{}_INVERTED'.format(idx + 1)] = 0
+
+    p['SRVAL_OQ'] = random.randint(0, 1)
+    p['SRVAL_TQ'] = random.randint(0, 1)
+    p['INIT_OQ'] = random.randint(0, 1)
+    p['INIT_TQ'] = random.randint(0, 1)
+
+    for idx in range(8):
+        p['IS_D{}_INVERTED'.format(idx + 1)] = random.randint(0, 1)
+
+    p['IS_CLK_INVERTED'] = random.randint(0, 1)
+    p['IS_CLKDIV_INVERTED'] = random.randint(0, 1)
+
+    clk_connections = ''
+    p['CLK_USED'] = random.randint(0, 1)
+    p['CLKDIV_USED'] = random.randint(0, 1)
+    if p['CLK_USED']:
+        clk_connections += '''
+        .CLK({}),'''.format(luts.get_next_output_net())
+    if p['CLKDIV_USED']:
+        clk_connections += '''
+        .CLKDIV({}),'''.format(luts.get_next_output_net())
+
+    print(
+        '''
+    (* KEEP, DONT_TOUCH, LOC = "{ologic_loc}" *)
+    OSERDESE2 #(
+        .SERDES_MODE({OSERDES_MODE}),
+        .DATA_RATE_TQ({DATA_RATE_TQ}),
+        .DATA_RATE_OQ({DATA_RATE_OQ}),
+        .DATA_WIDTH({DATA_WIDTH}),
+        .TRISTATE_WIDTH({TRISTATE_WIDTH}),
+        .SRVAL_OQ({SRVAL_OQ}),
+        .SRVAL_TQ({SRVAL_TQ}),
+        .INIT_OQ({INIT_OQ}),
+        .INIT_TQ({INIT_TQ}),
+        .IS_T1_INVERTED({IS_T1_INVERTED}),
+        .IS_T2_INVERTED({IS_T2_INVERTED}),
+        .IS_T3_INVERTED({IS_T3_INVERTED}),
+        .IS_T4_INVERTED({IS_T4_INVERTED}),
+        .IS_D1_INVERTED({IS_D1_INVERTED}),
+        .IS_D2_INVERTED({IS_D2_INVERTED}),
+        .IS_D3_INVERTED({IS_D3_INVERTED}),
+        .IS_D4_INVERTED({IS_D4_INVERTED}),
+        .IS_D5_INVERTED({IS_D5_INVERTED}),
+        .IS_D6_INVERTED({IS_D6_INVERTED}),
+        .IS_D7_INVERTED({IS_D7_INVERTED}),
+        .IS_D8_INVERTED({IS_D8_INVERTED}),
+        .IS_CLK_INVERTED({IS_CLK_INVERTED}),
+        .IS_CLKDIV_INVERTED({IS_CLKDIV_INVERTED})
+    ) oserdese2_{site} (
+        .OQ({owire}),
+        {TFB}
+        {TQ}
+        {clk_connections}
+        .D1({d1net}),
+        .D2({d2net}),
+        .D3({d3net}),
+        .D4({d4net}),
+        .D5({d5net}),
+        .D6({d6net}),
+        .D7({d7net}),
+        .D8({d8net}),
+        .OCE({ocenet}),
+        .RST({rstnet}),
+        .T1({t1net}),
+        .T2({t2net}),
+        .T3({t3net}),
+        .T4({t4net}),
+        .TCE({tcenet})
+        );'''.format(
+            clk_connections=clk_connections,
+            rstnet=luts.get_next_output_net(),
+            d1net=luts.get_next_output_net(),
+            d2net=luts.get_next_output_net(),
+            d3net=luts.get_next_output_net(),
+            d4net=luts.get_next_output_net(),
+            d5net=luts.get_next_output_net(),
+            d6net=luts.get_next_output_net(),
+            d7net=luts.get_next_output_net(),
+            d8net=luts.get_next_output_net(),
+            ocenet=luts.get_next_output_net(),
+            ofb_wire=luts.get_next_input_net(),
+            **p),
+        file=connects)
+
+
+def use_direct_and_oddr(p, luts, connects):
+    p['oddr_mux_config'] = random.choice((
+        'direct',
+        'lut',
+        'none',
+    ))
+
+    if p['io']:
+        if p['oddr_mux_config'] != 'lut':
+            p['tddr_mux_config'] = random.choice((
+                'direct',
+                'lut',
+                'none',
+            ))
+        else:
+            p['tddr_mux_config'] = random.choice((
+                'lut',
+                'none',
+            ))
+    else:
+        p['tddr_mux_config'] = 'none'
+
+    # toddr and oddr share the same clk
+    if random.randint(0, 1):
+        clknet = luts.get_next_output_net()
+        p['IS_CLK_INVERTED'] = 0
+    else:
+        clknet = 'bufg_o'
+        p['IS_CLK_INVERTED'] = random.randint(0, 1)
+
+    if p['tddr_mux_config'] == 'direct':
+        p['TINIT'] = random.randint(0, 1)
+        p['TSRTYPE'] = verilog.quote(random.choice(('SYNC', 'ASYNC')))
+        p['TDDR_CLK_EDGE'] = verilog.quote('OPPOSITE_EDGE')
+
+        # Note: it seems that CLK_EDGE setting is ignored for TDDR
+        p['TDDR_CLK_EDGE'] = verilog.quote(
+            random.choice(('OPPOSITE_EDGE', 'SAME_EDGE')))
+
+        p['t_sr_used'] = random.choice(('None', 'S', 'R'))
+        if p['t_sr_used'] == 'None':
+            p['t_srnet'] = ''
+        elif p['t_sr_used'] == 'S':
+            p['srnet'] = luts.get_next_output_net()
+            p['t_srnet'] = '.S({}),\n'.format(p['srnet'])
+        elif p['t_sr_used'] == 'R':
+            p['srnet'] = luts.get_next_output_net()
+            p['t_srnet'] = '.R({}),\n'.format(p['srnet'])
+
+        print(
+            '''
+    (* KEEP, DONT_TOUCH, LOC = "{ologic_loc}" *)
+    ODDR #(
+        .INIT({TINIT}),
+        .SRTYPE({TSRTYPE}),
+        .DDR_CLK_EDGE({TDDR_CLK_EDGE}),
+        .IS_C_INVERTED({IS_CLK_INVERTED})
+    ) toddr_{site} (
+        .C({cnet}),
+        .D1({d1net}),
+        .D2({d2net}),
+        .CE({cenet}),
+        {t_srnet}
+        .Q(tddr_d_{site})
+        );
+        '''.format(
+                cnet=clknet,
+                d1net=luts.get_next_output_net(),
+                d2net=luts.get_next_output_net(),
+                cenet=luts.get_next_output_net(),
+                **p),
+            file=connects)
+
+    if p['tddr_mux_config'] == 'direct':
+        print(
+            '''
+    assign {twire} = tddr_d_{site};'''.format(**p, ),
+            file=connects)
+    elif p['tddr_mux_config'] == 'lut':
+        print(
+            '''
+    assign {twire} = {lut};'''.format(lut=luts.get_next_output_net(), **p),
+            file=connects)
+        pass
+    elif p['tddr_mux_config'] == 'none':
+        pass
+    else:
+        assert False, p['tddr_mux_config']
+
+    if p['oddr_mux_config'] == 'direct':
+        p['QINIT'] = random.randint(0, 1)
+        p['SRTYPE'] = verilog.quote(random.choice(('SYNC', 'ASYNC')))
+        p['ODDR_CLK_EDGE'] = verilog.quote(
+            random.choice((
+                'OPPOSITE_EDGE',
+                'SAME_EDGE',
+            )))
+
+        p['o_sr_used'] = random.choice(('None', 'S', 'R'))
+        if p['o_sr_used'] == 'None':
+            p['o_srnet'] = ''
+        elif p['o_sr_used'] == 'S':
+            if 'srnet' not in p:
+                p['srnet'] = luts.get_next_output_net()
+            p['o_srnet'] = '.S({}),\n'.format(p['srnet'])
+        elif p['o_sr_used'] == 'R':
+            if 'srnet' not in p:
+                p['srnet'] = luts.get_next_output_net()
+            p['o_srnet'] = '.R({}),\n'.format(p['srnet'])
+
+        print(
+            '''
+    (* KEEP, DONT_TOUCH, LOC = "{ologic_loc}" *)
+    ODDR #(
+        .INIT({QINIT}),
+        .SRTYPE({SRTYPE}),
+        .DDR_CLK_EDGE({ODDR_CLK_EDGE}),
+        .IS_C_INVERTED({IS_CLK_INVERTED})
+    ) oddr_{site} (
+        .C({cnet}),
+        .D1({d1net}),
+        .D2({d2net}),
+        .CE({cenet}),
+        {o_srnet}
+        .Q(oddr_d_{site})
+        );
+        '''.format(
+                cnet=clknet,
+                d1net=luts.get_next_output_net(),
+                d2net=luts.get_next_output_net(),
+                cenet=luts.get_next_output_net(),
+                **p),
+            file=connects)
+
+    if p['oddr_mux_config'] == 'direct':
+        print(
+            '''
+    assign {owire} = oddr_d_{site};'''.format(**p, ),
+            file=connects)
+    elif p['oddr_mux_config'] == 'lut':
+        print(
+            '''
+    assign {owire} = {lut};'''.format(lut=luts.get_next_output_net(), **p),
+            file=connects)
+        pass
+    elif p['oddr_mux_config'] == 'none':
+        pass
+    else:
+        assert False, p['oddr_mux_config']
+
+
+def run():
+    iostandards = [
+        'LVCMOS12', 'LVCMOS15', 'LVCMOS18'
+    ]
+    iostandard = random.choice(iostandards)
+
+    if iostandard in ['LVCMOS12']:
+        drives = [2, 4, 6, 8]
+    elif iostandard in ['LVCMOS15', 'LVCMOS18']:
+        drives = [2, 4, 6, 8, 12, 16]
+    else:
+        assert False, "This should be unreachable"
+
+    slews = ['FAST', 'SLOW']
+    pulls = ["NONE", "KEEPER", "PULLDOWN", "PULLUP"]
+
+    luts = lut_maker.LutMaker()
+
+    connects = io.StringIO()
+
+    tile_params = []
+    params = []
+
+    ndio = 0
+    ndo = 0
+    for idx, (tile, site) in enumerate(gen_sites()):
+        if idx == 0:
+            continue
+
+        p = {}
+        p['tile'] = tile
+        p['site'] = site
+        p['ilogic_loc'] = site.replace('IOB', 'ILOGIC')
+        p['ologic_loc'] = site.replace('IOB', 'OLOGIC')
+        p['IOSTANDARD'] = verilog.quote(iostandard)
+        p['PULLTYPE'] = verilog.quote(random.choice(pulls))
+        p['DRIVE'] = random.choice(drives)
+        p['SLEW'] = verilog.quote(random.choice(slews))
+
+        p['io'] = random.randint(0, 1)
+        p['owire'] = 'do_buf[{}]'.format(idx - 1)
+
+        if p['io']:
+            p['pad_wire'] = 'dio[{}]'.format(ndio)
+            ndio += 1
+
+            p['iwire'] = 'di_buf[{}]'.format(idx - 1)
+            p['twire'] = 't[{}]'.format(idx - 1)
+        else:
+            p['pad_wire'] = 'do[{}]'.format(ndo)
+            ndo += 1
+
+        params.append(p)
+        tile_params.append(
+            (
+                tile, site, p['pad_wire'], iostandard, p['DRIVE'],
+                verilog.unquote(p['SLEW']) if p['SLEW'] else None,
+                verilog.unquote(p['PULLTYPE'])))
+
+    write_params(tile_params)
+
+    print(
+        '''
+`define N_DO {n_do}
+`define N_DIO {n_dio}
+
+module top(input clk, output wire [`N_DO-1:0] do, inout wire [`N_DIO-1:0] dio);
+    wire [(`N_DIO+`N_DO)-1:0] di_buf;
+    wire [(`N_DIO+`N_DO)-1:0] do_buf;
+    wire [(`N_DIO+`N_DO)-1:0] t;
+    '''.format(n_dio=ndio, n_do=ndo))
+
+    # Always output a LUT6 to make placer happy.
+    print(
+        '''
+        (* KEEP, DONT_TOUCH *)
+        LUT6 dummy_lut();
+
+        wire bufg_o;
+        (* KEEP, DONT_TOUCH *)
+        BUFG (.O(bufg_o));
+        ''')
+
+    for p in params:
+        if p['io']:
+            print(
+                '''
+        wire oddr_d_{site};
+
+        (* KEEP, DONT_TOUCH, LOC = "{site}" *)
+        IOBUF #(
+            .IOSTANDARD({IOSTANDARD})
+        ) obuf_{site} (
+            .IO({pad_wire}),
+            .I({owire}),
+            .O({iwire}),
+            .T({twire})
+            );
+            '''.format(**p),
+                file=connects)
+        else:
+            print(
+                '''
+        wire oddr_d_{site};
+
+        (* KEEP, DONT_TOUCH, LOC = "{site}" *)
+        OBUF #(
+            .IOSTANDARD({IOSTANDARD})
+        ) obuf_{site} (
+            .O({pad_wire}),
+            .I({owire})
+            );
+            '''.format(**p),
+                file=connects)
+
+        p['use_oserdese2'] = random.randint(0, 1)
+        if p['use_oserdese2']:
+            use_oserdese2(p, luts, connects)
+        else:
+            use_direct_and_oddr(p, luts, connects)
+
+    for l in luts.create_wires_and_luts():
+        print(l)
+
+    print(connects.getvalue())
+
+    print("endmodule")
+
+    with open('params.jl', 'w') as f:
+        json.dump(params, f, indent=2)
+
+
+if __name__ == '__main__':
+    run()

fuzzers/037-iob18-pips/Makefile

@@ -10,10 +10,16 @@ PIP_TYPE?=ioi
 PIPLIST_TCL=$(FUZDIR)/ioi_pip_list.tcl
 
 TODO_RE=".*"
-EXCLUDE_RE=".*((PHASER)|(CLKDIVF)|(CLKDIVP)|(CLKDIVB)|(IOI_ILOGIC[01]_O)|(IOI_OLOGIC[01]_CLKB?\.)|(IOI_IMUX_RC)|(IOI_OLOGIC[01]_[OT]FB)|(OCLKM.*IMUX31)|IOI_ODELAY[01]_CLKIN.IOI_OCLK_[01]|RIOI_O[01].RIOI_ODELAY[01]_DATAOUT|RIOI_O[01].RIOI_OLOGIC[01]_OQ).*"
+# Per-side exclusions cover the R-side patterns from upstream kintex7 plus the
+# mirrored L-side patterns needed when the part has HP-bank IOB18 on both sides
+# (e.g. virtex7 xc7vx485tffg1761-2). The L-side rules are exact mirrors with
+# the RIOI_ prefix replaced by LIOI_.
+EXCLUDE_RE=".*((PHASER)|(CLKDIVF)|(CLKDIVP)|(CLKDIVB)|(IOI_ILOGIC[01]_O)|(IOI_OLOGIC[01]_CLKB?\.)|(IOI_IMUX_RC)|(IOI_OLOGIC[01]_[OT]FB)|(OCLKM.*IMUX31)|IOI_ODELAY[01]_CLKIN.IOI_OCLK_[01]|RIOI_O[01].RIOI_ODELAY[01]_DATAOUT|RIOI_O[01].RIOI_OLOGIC[01]_OQ|LIOI_O[01].LIOI_ODELAY[01]_DATAOUT|LIOI_O[01].LIOI_OLOGIC[01]_OQ).*"
 
-MAKETODO_FLAGS=--pip-type ${PIP_TYPE} --seg-type $(PIP_TYPE) --re $(TODO_RE) --sides "xr" --exclude-re $(EXCLUDE_RE)
+MAKETODO_FLAGS=--pip-type ${PIP_TYPE} --seg-type $(PIP_TYPE) --re $(TODO_RE) --sides "xl,xr" --exclude-re $(EXCLUDE_RE)
-N = 120
+# N=120 is excessive on a large device like xc7vx485t; 20 (matches other pip
+# fuzzers) is plenty for segmatch convergence and roughly 6x faster per iter.
+N = 20
 
 SPECIMENS_DEPS=build/cmt_regions.csv
 
@@ -22,12 +28,15 @@ include ../pip_loop.mk
 SIX_BIT_PIPS="OLOGIC[01]_CLKDIV"
 
 build/segbits_ioi_x.rdb: $(SPECIMENS_OK)
-	# Most pips are 3 bits, force a 3 bit solution
+	# Most pips are 3 bits, force a 3 bit solution.
+	# Match segdata for BOTH lioi*.txt and rioi*.txt so left- and right-side
+	# pip bits feed segmatch in a single pass (the per-side data is solved
+	# against side-specific pip names that live in the same tile architecture).
 	${XRAY_SEGMATCH} -c 3 -m 20 -M 50 -o build/segbits_ioi_x_match_3.rdb \
-		$(shell find build -name segdata_rioi*.txt)
+		$(shell find build -name 'segdata_[rl]ioi*.txt')
 	# Some are 6 bit solutions, solve for 6 bits and merge respectively
 	${XRAY_SEGMATCH} -c 6 -m 20 -M 50 -o build/segbits_ioi_x_match_6.rdb \
-		$(shell find build -name segdata_rioi*.txt)
+		$(shell find build -name 'segdata_[rl]ioi*.txt')
 	grep -v ${SIX_BIT_PIPS} build/segbits_ioi_x_match_3.rdb  > build/segbits_ioi_x.rdb
 	grep    ${SIX_BIT_PIPS} build/segbits_ioi_x_match_6.rdb >> build/segbits_ioi_x.rdb
 
@@ -45,6 +54,7 @@ database: ${RDBS}
 	# Clobber existing .db to eliminate potential conflicts
 	cp ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/segbits*.db build/database/${XRAY_DATABASE}
 	XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} rioi build/segbits_ioi_x.db
+	XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} lioi build/segbits_ioi_x.db
 
 build/cmt_regions.csv: output_cmt.tcl
 	mkdir -p build
@@ -54,5 +64,11 @@ pushdb: database
 	${XRAY_MERGEDB} rioi build/segbits_ioi_x.db
 	${XRAY_MERGEDB} rioi_tbytesrc build/segbits_ioi_x.db
 	${XRAY_MERGEDB} rioi_tbyteterm build/segbits_ioi_x.db
+	# L-side counterparts for parts with HP-bank IOB18 on both sides
+	# (e.g. virtex7 xc7vx485tffg1761-2). Harmless on R-side-only parts:
+	# segbits_lioi*.db just ends up empty or unchanged.
+	${XRAY_MERGEDB} lioi build/segbits_ioi_x.db
+	${XRAY_MERGEDB} lioi_tbytesrc build/segbits_ioi_x.db
+	${XRAY_MERGEDB} lioi_tbyteterm build/segbits_ioi_x.db
 
 .PHONY: database pushdb

fuzzers/037-iob18-pips/generate.py

@@ -72,8 +72,12 @@ def main():
     for tile, pips_srcs_dsts in tiledata.items():
         tile_type = pips_srcs_dsts["type"]
 
+        # Normalise per-instance tile types (e.g. RIOI_TBYTESRC, LIOI_SING) to
+        # the base type used as pipdata key by ioi_pip_list.tcl.
         if tile_type.startswith('RIOI'):
             tile_type = 'RIOI'
+        elif tile_type.startswith('LIOI'):
+            tile_type = 'LIOI'
 
         for src, dst in pipdata[tile_type]:
             if (src, dst) in ignpip:

fuzzers/037-iob18-pips/generate.tcl

@@ -7,28 +7,14 @@
 # SPDX-License-Identifier: ISC
 source "$::env(XRAY_DIR)/utils/utils.tcl"
 
-proc write_pip_txtdata {filename} {
+# NOTE: this fuzzer previously defined its own slow Tcl write_pip_txtdata proc
-    puts "FUZ([pwd]): Writing $filename."
+# that iterated foreach net foreach pip and queried the routing graph per-pip
-    set fp [open $filename w]
+# (set num_pips [llength [get_nodes -uphill ...]] ...). On a large device like
-    set nets [get_nets -hierarchical]
+# xc7vx485t this took hours per specimen (1296 nets * O(nodes) Tcl queries).
-    set nnets [llength $nets]
+# Vivado's built-in `write_pip_txtdata $filename` produces the same 6-column
-    set neti 0
+# output (tile pip src_wire dst_wire pnum pdir) that the prjxray segmakers
-    foreach net $nets {
+# parse, but in seconds. Drop the override; the call at the end of this file
-        incr neti
+# now resolves to the built-in.
-        if {($neti % 100) == 0 } {
-            puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)"
-        }
-        foreach pip [get_pips -of_objects $net] {
-            set tile [get_tiles -of_objects $pip]
-            set src_wire [get_wires -uphill -of_objects $pip]
-            set dst_wire [get_wires -downhill -of_objects $pip]
-            set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
-            set dir_prop [get_property IS_DIRECTIONAL $pip]
-            puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
-        }
-    }
-    close $fp
-}
 
 proc make_manual_routes {filename} {
     puts "MANROUTE: Loading routes from $filename"