Merge pull request #357 from mcmasterg/pll_poc

MMCME2_ADV, PLLE2_ADV: very basic fuzzer

fuzzers/005-tilegrid/add_tdb.py

@@ -97,9 +97,9 @@ def run(fn_in, fn_out, verbose=False):
     tdb_fns = [
         ("iob/build/segbits_tilegrid.tdb", 42, 4),
         # FIXME: height
-        ("mmcm/build/segbits_tilegrid.tdb", 30, 4),
+        ("mmcm/build/segbits_tilegrid.tdb", 30, 101),
         # FIXME: height
-        ("pll/build/segbits_tilegrid.tdb", 30, 4),
+        ("pll/build/segbits_tilegrid.tdb", 30, 101),
     ]
     for (tdb_fn, frames, words) in tdb_fns:
         for (tile, frame, wordidx) in load_db(tdb_fn):

fuzzers/005-tilegrid/mmcm/Makefile

@@ -1,5 +1,6 @@
 N ?= 2
 # Was expecting oneval 3, but bits might be inverted
 # FIXME: dword
-GENERATE_ARGS?="--oneval 2 --design params.csv --dframe 1D --dword 0 --dbit 15"
+# Ex: 0002009D_029_15
+GENERATE_ARGS?="--oneval 2 --design params.csv --dframe 1D --dword 29 --dbit 15"
 include ../fuzzaddr/common.mk

fuzzers/005-tilegrid/pll/Makefile

@@ -1,5 +1,6 @@
 N ?= 2
 # Was expecting oneval 3, but bits might be inverted
 # FIXME: dword
-GENERATE_ARGS?="--oneval 2 --design params.csv --dframe 1C --dword 0 --dbit 16"
+# Ex: 0002009C_077_16
+GENERATE_ARGS?="--oneval 2 --design params.csv --dframe 1C --dword 77 --dbit 16"
 include ../fuzzaddr/common.mk

fuzzers/025-bram-config/generate.py

@@ -6,7 +6,7 @@ from prjxray.segmaker import Segmaker
 from prjxray import verilog
 
 
-def isenv_tags(segmk, ps, site):
+def isinv_tags(segmk, ps, site):
     # all of these bits are inverted
     ks = [
         ('IS_CLKARDCLK_INVERTED', 'ZINV_CLKARDCLK'),
@@ -109,7 +109,7 @@ def run():
         site = verilog.unquote(ps['LOC'])
         #print('site', site)
 
-        isenv_tags(segmk, ps, site)
+        isinv_tags(segmk, ps, site)
         bus_tags(segmk, ps, site)
         rw_width_tags(segmk, ps, site)
         write_mode_tags(segmk, ps, site)

fuzzers/025-bram-config/top.py

@@ -126,50 +126,6 @@ for loci, (site_type, site) in enumerate(brams):
     j = {'module': modname, 'i': loci, 'params': params}
     f.write('%s\n' % (json.dumps(j)))
     print('')
-'''
-
-
-
-def randbits(n):
-    return ''.join([random.choice(('0', '1')) for _x in range(n)])
-
-
-loci = 0
-
-
-def make(module, gen_locs, pdatan, datan):
-    global loci
-
-    for loci, loc in enumerate(gen_locs()):
-        if loci >= DUTN:
-            break
-
-        pdata = randbits(pdatan * 0x100)
-        data = randbits(datan * 0x100)
-
-        print('    %s #(' % module)
-        for i in range(pdatan):
-            print(
-                "        .INITP_%02X(256'b%s)," %
-                (i, pdata[i * 256:(i + 1) * 256]))
-        for i in range(datan):
-            print(
-                "        .INIT_%02X(256'b%s)," %
-                (i, data[i * 256:(i + 1) * 256]))
-        print('        .LOC("%s"))' % (loc, ))
-        print(
-            '            inst_%d (.clk(clk), .din(din[  %d +: 8]), .dout(dout[  %d +: 8]));'
-            % (loci, 8 * loci, 8 * loci))
-
-        f.write('%s,%s,%s,%s\n' % (module, loc, pdata, data))
-        print('')
-        loci += 1
-    assert loci == DUTN
-
-
-#make('my_RAMB18E1', gen_bram18, 0x08, 0x40)
-make('my_RAMB36E1', gen_bram36, 0x10, 0x80)
-'''
 
 f.close()
 print(

fuzzers/030-iob/README.md

@@ -1,4 +1,2 @@
-# NDI1MUX Fuzzer
+# IOB Fuzzer
-
-See minitest for DI notes
 

fuzzers/031-mmcm/.gitignore

@@ -0,0 +1 @@
+build

fuzzers/031-mmcm/Makefile

@@ -0,0 +1,19 @@
+# read/write width is relatively slow to resolve
+# Even slower with multi bit masks...
+N := 8
+include ../fuzzer.mk
+
+database: build/segbits_bramx.db
+
+build/segbits_bramx.rdb: $(SPECIMENS_OK)
+	${XRAY_SEGMATCH} -o build/segbits_bramx.rdb $(addsuffix /segdata_bram_[lr].txt,$(SPECIMENS))
+
+build/segbits_bramx.db: build/segbits_bramx.rdb
+	${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
+
+pushdb:
+	${XRAY_MERGEDB} bram_l build/segbits_bramx.db
+	${XRAY_MERGEDB} bram_r build/segbits_bramx.db
+
+.PHONY: database pushdb
+

fuzzers/031-mmcm/generate.py

@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+
+import json
+
+from prjxray.segmaker import Segmaker
+from prjxray import verilog
+
+
+def bus_tags(segmk, ps, site):
+    for param, tagname in [('CLKOUT1_DIVIDE', 'ZCLKOUT1_DIVIDE')]:
+        # 1-128 => 0-127 for actual 7 bit value
+        paramadj = int(ps[param]) - 1
+        bitstr = [int(x) for x in "{0:07b}".format(paramadj)[::-1]]
+        # FIXME: only bits 0 and 1 resolving
+        # for i in range(7):
+        for i in range(2):
+            segmk.add_site_tag(site, '%s[%u]' % (param, i), 1 ^ bitstr[i])
+
+
+def run():
+
+    segmk = Segmaker("design.bits")
+
+    print("Loading tags")
+    f = open('params.jl', 'r')
+    f.readline()
+    for l in f:
+        j = json.loads(l)
+        ps = j['params']
+        assert j['module'] == 'my_MMCME2_ADV'
+        site = verilog.unquote(ps['LOC'])
+
+        bus_tags(segmk, ps, site)
+
+    segmk.compile()
+    segmk.write()
+
+
+run()

fuzzers/031-mmcm/generate.sh

@@ -0,0 +1,5 @@
+#!/bin/bash
+
+set -ex
+source ${XRAY_DIR}/utils/top_generate.sh
+

fuzzers/031-mmcm/generate.tcl

@@ -0,0 +1,33 @@
+create_project -force -part $::env(XRAY_PART) design design
+read_verilog top.v
+synth_design -top top
+
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+
+create_pblock roi
+
+add_cells_to_pblock [get_pblocks roi] [get_cells roi]
+resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+# Disable MMCM frequency etc sanity checks
+set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}]
+set_property IS_ENABLED 0 [get_drc_checks {PDRC-30}]
+set_property IS_ENABLED 0 [get_drc_checks {AVAL-50}]
+set_property IS_ENABLED 0 [get_drc_checks {AVAL-53}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-126}]
+# PLL
+set_property IS_ENABLED 0 [get_drc_checks {REQP-161}]
+
+place_design
+route_design
+
+write_checkpoint -force design.dcp
+write_bitstream -force design.bit

fuzzers/031-mmcm/top.py

@@ -0,0 +1,114 @@
+import os
+import random
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray import verilog
+from prjxray.verilog import vrandbit, vrandbits
+import sys
+import json
+
+
+def gen_sites():
+    for _tile_name, site_name, _site_type in sorted(util.get_roi().gen_sites(
+        ["PLLE2_ADV"])):
+        yield site_name
+
+
+sites = list(gen_sites())
+DUTN = len(sites)
+DIN_N = DUTN * 8
+DOUT_N = DUTN * 8
+
+verilog.top_harness(DIN_N, DOUT_N)
+
+f = open('params.jl', 'w')
+f.write('module,loc,params\n')
+print(
+    'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
+    (DIN_N - 1, DOUT_N - 1))
+
+for loci, site in enumerate(sites):
+
+    ports = {
+        'clk': 'clk',
+        'din': 'din[  %d +: 8]' % (8 * loci, ),
+        'dout': 'dout[  %d +: 8]' % (8 * loci, ),
+    }
+
+    params = {
+        "CLKOUT1_DIVIDE": random.randint(1, 128),
+    }
+
+    modname = "my_MMCME2_ADV"
+    verilog.instance(modname, "inst_%u" % loci, ports, params=params)
+    # LOC isn't support
+    params["LOC"] = verilog.quote(site)
+
+    j = {'module': modname, 'i': loci, 'params': params}
+    f.write('%s\n' % (json.dumps(j)))
+    print('')
+
+f.close()
+print(
+    '''endmodule
+
+// ---------------------------------------------------------------------
+
+''')
+
+print(
+    '''
+module my_MMCME2_ADV (input clk, input [7:0] din, output [7:0] dout);
+    parameter CLKOUT1_DIVIDE = 1;
+    parameter CLKOUT2_DIVIDE = 1;
+    parameter CLKOUT3_DIVIDE = 1;
+    parameter CLKOUT4_DIVIDE = 1;
+    parameter CLKOUT5_DIVIDE = 1;
+    parameter CLKOUT6_DIVIDE = 1;
+    parameter DIVCLK_DIVIDE = 1;
+    parameter CLKFBOUT_MULT = 5;
+
+    (* KEEP, DONT_TOUCH *)
+    MMCME2_ADV #(
+            .CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
+            .CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
+            .CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
+            .CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
+            .CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
+            .CLKOUT6_DIVIDE(CLKOUT6_DIVIDE)
+    ) dut(
+            .CLKFBOUT(),
+            .CLKFBOUTB(),
+            .CLKFBSTOPPED(),
+            .CLKINSTOPPED(),
+            .CLKOUT0(dout[0]),
+            .CLKOUT0B(),
+            .CLKOUT1(),
+            .CLKOUT1B(),
+            .CLKOUT2(),
+            .CLKOUT2B(),
+            .CLKOUT3(),
+            .CLKOUT3B(),
+            .CLKOUT4(),
+            .CLKOUT5(),
+            .CLKOUT6(),
+            .DO(),
+            .DRDY(),
+            .LOCKED(),
+            .PSDONE(),
+            .CLKFBIN(clk),
+            .CLKIN1(clk),
+            .CLKIN2(clk),
+            .CLKINSEL(clk),
+            .DADDR(),
+            .DCLK(clk),
+            .DEN(),
+            .DI(),
+            .DWE(),
+            .PSCLK(clk),
+            .PSEN(),
+            .PSINCDEC(),
+            .PWRDWN(),
+            .RST(din[0]));
+endmodule
+''')

fuzzers/032-pll/.gitignore

@@ -0,0 +1 @@
+build

fuzzers/032-pll/Makefile

@@ -0,0 +1,19 @@
+# read/write width is relatively slow to resolve
+# Even slower with multi bit masks...
+N := 8
+include ../fuzzer.mk
+
+database: build/segbits_bramx.db
+
+build/segbits_bramx.rdb: $(SPECIMENS_OK)
+	${XRAY_SEGMATCH} -o build/segbits_bramx.rdb $(addsuffix /segdata_bram_[lr].txt,$(SPECIMENS))
+
+build/segbits_bramx.db: build/segbits_bramx.rdb
+	${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
+
+pushdb:
+	${XRAY_MERGEDB} bram_l build/segbits_bramx.db
+	${XRAY_MERGEDB} bram_r build/segbits_bramx.db
+
+.PHONY: database pushdb
+

fuzzers/032-pll/generate.py

@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+
+import json
+
+from prjxray.segmaker import Segmaker
+from prjxray import verilog
+
+
+def bus_tags(segmk, ps, site):
+    for param, tagname in [('CLKOUT0_DIVIDE', 'ZCLKOUT0_DIVIDE')]:
+        # 1-128 => 0-127 for actual 7 bit value
+        paramadj = int(ps[param]) - 1
+        bitstr = [int(x) for x in "{0:07b}".format(paramadj)[::-1]]
+        # FIXME: only bits 0 and 1 resolving
+        # for i in range(7):
+        for i in range(2):
+            segmk.add_site_tag(site, '%s[%u]' % (param, i), 1 ^ bitstr[i])
+
+
+def run():
+
+    segmk = Segmaker("design.bits")
+
+    print("Loading tags")
+    f = open('params.jl', 'r')
+    f.readline()
+    for l in f:
+        j = json.loads(l)
+        ps = j['params']
+        assert j['module'] == 'my_PLLE2_ADV'
+        site = verilog.unquote(ps['LOC'])
+
+        bus_tags(segmk, ps, site)
+
+    segmk.compile()
+    segmk.write()
+
+
+run()

fuzzers/032-pll/generate.sh

@@ -0,0 +1,5 @@
+#!/bin/bash
+
+set -ex
+source ${XRAY_DIR}/utils/top_generate.sh
+

fuzzers/032-pll/generate.tcl

@@ -0,0 +1,33 @@
+create_project -force -part $::env(XRAY_PART) design design
+read_verilog top.v
+synth_design -top top
+
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+
+create_pblock roi
+
+add_cells_to_pblock [get_pblocks roi] [get_cells roi]
+resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+# Disable MMCM frequency etc sanity checks
+set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}]
+set_property IS_ENABLED 0 [get_drc_checks {PDRC-30}]
+set_property IS_ENABLED 0 [get_drc_checks {AVAL-50}]
+set_property IS_ENABLED 0 [get_drc_checks {AVAL-53}]
+set_property IS_ENABLED 0 [get_drc_checks {REQP-126}]
+# PLL
+set_property IS_ENABLED 0 [get_drc_checks {REQP-161}]
+
+place_design
+route_design
+
+write_checkpoint -force design.dcp
+write_bitstream -force design.bit

fuzzers/032-pll/top.py

@@ -0,0 +1,104 @@
+import os
+import random
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray import verilog
+from prjxray.verilog import vrandbit, vrandbits
+import sys
+import json
+
+
+def gen_sites():
+    for _tile_name, site_name, _site_type in sorted(util.get_roi().gen_sites(
+        ["PLLE2_ADV"])):
+        yield site_name
+
+
+sites = list(gen_sites())
+DUTN = len(sites)
+DIN_N = DUTN * 8
+DOUT_N = DUTN * 8
+
+verilog.top_harness(DIN_N, DOUT_N)
+
+f = open('params.jl', 'w')
+f.write('module,loc,params\n')
+print(
+    'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
+    (DIN_N - 1, DOUT_N - 1))
+
+for loci, site in enumerate(sites):
+
+    ports = {
+        'clk': 'clk',
+        'din': 'din[  %d +: 8]' % (8 * loci, ),
+        'dout': 'dout[  %d +: 8]' % (8 * loci, ),
+    }
+
+    params = {
+        "CLKOUT0_DIVIDE": random.randint(1, 128),
+    }
+
+    modname = "my_PLLE2_ADV"
+    verilog.instance(modname, "inst_%u" % loci, ports, params=params)
+    # LOC isn't support
+    params["LOC"] = verilog.quote(site)
+
+    j = {'module': modname, 'i': loci, 'params': params}
+    f.write('%s\n' % (json.dumps(j)))
+    print('')
+
+f.close()
+print(
+    '''endmodule
+
+// ---------------------------------------------------------------------
+
+''')
+
+print(
+    '''
+module my_PLLE2_ADV (input clk, input [7:0] din, output [7:0] dout);
+    parameter CLKOUT0_DIVIDE = 1;
+    parameter CLKOUT1_DIVIDE = 1;
+    parameter CLKOUT2_DIVIDE = 1;
+    parameter CLKOUT3_DIVIDE = 1;
+    parameter CLKOUT4_DIVIDE = 1;
+    parameter CLKOUT5_DIVIDE = 1;
+    parameter DIVCLK_DIVIDE = 1;
+    parameter CLKFBOUT_MULT = 5;
+
+    (* KEEP, DONT_TOUCH *)
+    PLLE2_ADV #(
+            .CLKOUT0_DIVIDE(CLKOUT0_DIVIDE),
+            .CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
+            .CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
+            .CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
+            .CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
+            .CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
+            .DIVCLK_DIVIDE(DIVCLK_DIVIDE),
+            .CLKFBOUT_MULT(CLKFBOUT_MULT)
+    ) dut(
+            .CLKFBOUT(),
+            .CLKOUT0(dout[0]),
+            .CLKOUT1(),
+            .CLKOUT2(),
+            .CLKOUT3(),
+            .CLKOUT4(),
+            .CLKOUT5(),
+            .DRDY(),
+            .LOCKED(),
+            .DO(),
+            .CLKFBIN(),
+            .CLKIN1(),
+            .CLKIN2(),
+            .CLKINSEL(),
+            .DCLK(),
+            .DEN(),
+            .DWE(),
+            .PWRDWN(),
+            .RST(din[0]),
+            .DI(),
+            .DADDR());
+endmodule
+''')