mirror of https://github.com/openXC7/prjxray.git
Merge pull request #357 from mcmasterg/pll_poc
MMCME2_ADV, PLLE2_ADV: very basic fuzzer
This commit is contained in:
John McMaster
GitHub
commit
759e9b64ba
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@ -97,9 +97,9 @@ def run(fn_in, fn_out, verbose=False):
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tdb_fns = [
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("iob/build/segbits_tilegrid.tdb", 42, 4),
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# FIXME: height
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("mmcm/build/segbits_tilegrid.tdb", 30, 4),
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("mmcm/build/segbits_tilegrid.tdb", 30, 101),
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# FIXME: height
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("pll/build/segbits_tilegrid.tdb", 30, 4),
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("pll/build/segbits_tilegrid.tdb", 30, 101),
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]
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for (tdb_fn, frames, words) in tdb_fns:
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for (tile, frame, wordidx) in load_db(tdb_fn):
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@ -1,5 +1,6 @@
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N ?= 2
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# Was expecting oneval 3, but bits might be inverted
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# FIXME: dword
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GENERATE_ARGS?="--oneval 2 --design params.csv --dframe 1D --dword 0 --dbit 15"
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# Ex: 0002009D_029_15
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GENERATE_ARGS?="--oneval 2 --design params.csv --dframe 1D --dword 29 --dbit 15"
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include ../fuzzaddr/common.mk
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@ -1,5 +1,6 @@
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N ?= 2
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# Was expecting oneval 3, but bits might be inverted
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# FIXME: dword
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GENERATE_ARGS?="--oneval 2 --design params.csv --dframe 1C --dword 0 --dbit 16"
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# Ex: 0002009C_077_16
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GENERATE_ARGS?="--oneval 2 --design params.csv --dframe 1C --dword 77 --dbit 16"
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include ../fuzzaddr/common.mk
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@ -6,7 +6,7 @@ from prjxray.segmaker import Segmaker
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from prjxray import verilog
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def isenv_tags(segmk, ps, site):
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def isinv_tags(segmk, ps, site):
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# all of these bits are inverted
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ks = [
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('IS_CLKARDCLK_INVERTED', 'ZINV_CLKARDCLK'),
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@ -109,7 +109,7 @@ def run():
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site = verilog.unquote(ps['LOC'])
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#print('site', site)
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isenv_tags(segmk, ps, site)
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isinv_tags(segmk, ps, site)
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bus_tags(segmk, ps, site)
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rw_width_tags(segmk, ps, site)
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write_mode_tags(segmk, ps, site)
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@ -126,50 +126,6 @@ for loci, (site_type, site) in enumerate(brams):
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j = {'module': modname, 'i': loci, 'params': params}
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f.write('%s\n' % (json.dumps(j)))
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print('')
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'''
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def randbits(n):
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return ''.join([random.choice(('0', '1')) for _x in range(n)])
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loci = 0
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def make(module, gen_locs, pdatan, datan):
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global loci
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for loci, loc in enumerate(gen_locs()):
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if loci >= DUTN:
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break
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pdata = randbits(pdatan * 0x100)
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data = randbits(datan * 0x100)
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print(' %s #(' % module)
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for i in range(pdatan):
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print(
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" .INITP_%02X(256'b%s)," %
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(i, pdata[i * 256:(i + 1) * 256]))
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for i in range(datan):
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print(
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" .INIT_%02X(256'b%s)," %
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(i, data[i * 256:(i + 1) * 256]))
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print(' .LOC("%s"))' % (loc, ))
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print(
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' inst_%d (.clk(clk), .din(din[ %d +: 8]), .dout(dout[ %d +: 8]));'
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% (loci, 8 * loci, 8 * loci))
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f.write('%s,%s,%s,%s\n' % (module, loc, pdata, data))
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print('')
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loci += 1
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assert loci == DUTN
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#make('my_RAMB18E1', gen_bram18, 0x08, 0x40)
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make('my_RAMB36E1', gen_bram36, 0x10, 0x80)
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'''
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f.close()
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print(
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@ -1,4 +1,2 @@
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# NDI1MUX Fuzzer
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See minitest for DI notes
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# IOB Fuzzer
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@ -0,0 +1 @@
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build
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@ -0,0 +1,19 @@
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# read/write width is relatively slow to resolve
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# Even slower with multi bit masks...
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N := 8
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include ../fuzzer.mk
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database: build/segbits_bramx.db
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build/segbits_bramx.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o build/segbits_bramx.rdb $(addsuffix /segdata_bram_[lr].txt,$(SPECIMENS))
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build/segbits_bramx.db: build/segbits_bramx.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
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pushdb:
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${XRAY_MERGEDB} bram_l build/segbits_bramx.db
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${XRAY_MERGEDB} bram_r build/segbits_bramx.db
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.PHONY: database pushdb
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@ -0,0 +1,39 @@
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#!/usr/bin/env python3
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import json
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from prjxray.segmaker import Segmaker
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from prjxray import verilog
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def bus_tags(segmk, ps, site):
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for param, tagname in [('CLKOUT1_DIVIDE', 'ZCLKOUT1_DIVIDE')]:
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# 1-128 => 0-127 for actual 7 bit value
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paramadj = int(ps[param]) - 1
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bitstr = [int(x) for x in "{0:07b}".format(paramadj)[::-1]]
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# FIXME: only bits 0 and 1 resolving
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# for i in range(7):
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for i in range(2):
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segmk.add_site_tag(site, '%s[%u]' % (param, i), 1 ^ bitstr[i])
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def run():
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segmk = Segmaker("design.bits")
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print("Loading tags")
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f = open('params.jl', 'r')
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f.readline()
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for l in f:
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j = json.loads(l)
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ps = j['params']
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assert j['module'] == 'my_MMCME2_ADV'
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site = verilog.unquote(ps['LOC'])
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bus_tags(segmk, ps, site)
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segmk.compile()
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segmk.write()
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run()
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@ -0,0 +1,5 @@
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#!/bin/bash
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set -ex
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source ${XRAY_DIR}/utils/top_generate.sh
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@ -0,0 +1,33 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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# Disable MMCM frequency etc sanity checks
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}]
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-30}]
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set_property IS_ENABLED 0 [get_drc_checks {AVAL-50}]
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set_property IS_ENABLED 0 [get_drc_checks {AVAL-53}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-126}]
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# PLL
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set_property IS_ENABLED 0 [get_drc_checks {REQP-161}]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -0,0 +1,114 @@
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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from prjxray.verilog import vrandbit, vrandbits
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import sys
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import json
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def gen_sites():
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for _tile_name, site_name, _site_type in sorted(util.get_roi().gen_sites(
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["PLLE2_ADV"])):
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yield site_name
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sites = list(gen_sites())
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DUTN = len(sites)
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DIN_N = DUTN * 8
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DOUT_N = DUTN * 8
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verilog.top_harness(DIN_N, DOUT_N)
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f = open('params.jl', 'w')
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f.write('module,loc,params\n')
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print(
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'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
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(DIN_N - 1, DOUT_N - 1))
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for loci, site in enumerate(sites):
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ports = {
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'clk': 'clk',
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'din': 'din[ %d +: 8]' % (8 * loci, ),
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'dout': 'dout[ %d +: 8]' % (8 * loci, ),
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}
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params = {
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"CLKOUT1_DIVIDE": random.randint(1, 128),
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}
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modname = "my_MMCME2_ADV"
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verilog.instance(modname, "inst_%u" % loci, ports, params=params)
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# LOC isn't support
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params["LOC"] = verilog.quote(site)
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j = {'module': modname, 'i': loci, 'params': params}
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f.write('%s\n' % (json.dumps(j)))
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print('')
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f.close()
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print(
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'''endmodule
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// ---------------------------------------------------------------------
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''')
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print(
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'''
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module my_MMCME2_ADV (input clk, input [7:0] din, output [7:0] dout);
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parameter CLKOUT1_DIVIDE = 1;
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parameter CLKOUT2_DIVIDE = 1;
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parameter CLKOUT3_DIVIDE = 1;
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parameter CLKOUT4_DIVIDE = 1;
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parameter CLKOUT5_DIVIDE = 1;
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parameter CLKOUT6_DIVIDE = 1;
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parameter DIVCLK_DIVIDE = 1;
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parameter CLKFBOUT_MULT = 5;
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(* KEEP, DONT_TOUCH *)
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MMCME2_ADV #(
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.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
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.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
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.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
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.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
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.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
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.CLKOUT6_DIVIDE(CLKOUT6_DIVIDE)
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) dut(
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.CLKFBOUT(),
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.CLKFBOUTB(),
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.CLKFBSTOPPED(),
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.CLKINSTOPPED(),
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.CLKOUT0(dout[0]),
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.CLKOUT0B(),
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.CLKOUT1(),
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.CLKOUT1B(),
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.CLKOUT2(),
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.CLKOUT2B(),
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.CLKOUT3(),
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.CLKOUT3B(),
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKOUT6(),
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.DO(),
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.DRDY(),
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.LOCKED(),
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.PSDONE(),
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.CLKFBIN(clk),
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.CLKIN1(clk),
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.CLKIN2(clk),
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.CLKINSEL(clk),
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.DADDR(),
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.DCLK(clk),
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.DEN(),
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.DI(),
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.DWE(),
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.PSCLK(clk),
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.PSEN(),
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.PSINCDEC(),
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.PWRDWN(),
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.RST(din[0]));
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endmodule
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''')
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@ -0,0 +1 @@
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build
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@ -0,0 +1,19 @@
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# read/write width is relatively slow to resolve
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# Even slower with multi bit masks...
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N := 8
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include ../fuzzer.mk
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database: build/segbits_bramx.db
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build/segbits_bramx.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o build/segbits_bramx.rdb $(addsuffix /segdata_bram_[lr].txt,$(SPECIMENS))
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build/segbits_bramx.db: build/segbits_bramx.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
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pushdb:
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${XRAY_MERGEDB} bram_l build/segbits_bramx.db
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${XRAY_MERGEDB} bram_r build/segbits_bramx.db
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.PHONY: database pushdb
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@ -0,0 +1,39 @@
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#!/usr/bin/env python3
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import json
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from prjxray.segmaker import Segmaker
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from prjxray import verilog
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def bus_tags(segmk, ps, site):
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for param, tagname in [('CLKOUT0_DIVIDE', 'ZCLKOUT0_DIVIDE')]:
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# 1-128 => 0-127 for actual 7 bit value
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paramadj = int(ps[param]) - 1
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bitstr = [int(x) for x in "{0:07b}".format(paramadj)[::-1]]
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# FIXME: only bits 0 and 1 resolving
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# for i in range(7):
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for i in range(2):
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segmk.add_site_tag(site, '%s[%u]' % (param, i), 1 ^ bitstr[i])
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def run():
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segmk = Segmaker("design.bits")
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print("Loading tags")
|
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f = open('params.jl', 'r')
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f.readline()
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for l in f:
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j = json.loads(l)
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ps = j['params']
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assert j['module'] == 'my_PLLE2_ADV'
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site = verilog.unquote(ps['LOC'])
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bus_tags(segmk, ps, site)
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segmk.compile()
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segmk.write()
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run()
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@ -0,0 +1,5 @@
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#!/bin/bash
|
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|
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set -ex
|
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source ${XRAY_DIR}/utils/top_generate.sh
|
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|
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|
|
@ -0,0 +1,33 @@
|
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create_project -force -part $::env(XRAY_PART) design design
|
||||
read_verilog top.v
|
||||
synth_design -top top
|
||||
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
|
||||
|
||||
create_pblock roi
|
||||
|
||||
add_cells_to_pblock [get_pblocks roi] [get_cells roi]
|
||||
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
|
||||
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
|
||||
|
||||
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
|
||||
# Disable MMCM frequency etc sanity checks
|
||||
set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {PDRC-30}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {AVAL-50}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {AVAL-53}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-126}]
|
||||
# PLL
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-161}]
|
||||
|
||||
place_design
|
||||
route_design
|
||||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
import os
|
||||
import random
|
||||
random.seed(int(os.getenv("SEED"), 16))
|
||||
from prjxray import util
|
||||
from prjxray import verilog
|
||||
from prjxray.verilog import vrandbit, vrandbits
|
||||
import sys
|
||||
import json
|
||||
|
||||
|
||||
def gen_sites():
|
||||
for _tile_name, site_name, _site_type in sorted(util.get_roi().gen_sites(
|
||||
["PLLE2_ADV"])):
|
||||
yield site_name
|
||||
|
||||
|
||||
sites = list(gen_sites())
|
||||
DUTN = len(sites)
|
||||
DIN_N = DUTN * 8
|
||||
DOUT_N = DUTN * 8
|
||||
|
||||
verilog.top_harness(DIN_N, DOUT_N)
|
||||
|
||||
f = open('params.jl', 'w')
|
||||
f.write('module,loc,params\n')
|
||||
print(
|
||||
'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
|
||||
(DIN_N - 1, DOUT_N - 1))
|
||||
|
||||
for loci, site in enumerate(sites):
|
||||
|
||||
ports = {
|
||||
'clk': 'clk',
|
||||
'din': 'din[ %d +: 8]' % (8 * loci, ),
|
||||
'dout': 'dout[ %d +: 8]' % (8 * loci, ),
|
||||
}
|
||||
|
||||
params = {
|
||||
"CLKOUT0_DIVIDE": random.randint(1, 128),
|
||||
}
|
||||
|
||||
modname = "my_PLLE2_ADV"
|
||||
verilog.instance(modname, "inst_%u" % loci, ports, params=params)
|
||||
# LOC isn't support
|
||||
params["LOC"] = verilog.quote(site)
|
||||
|
||||
j = {'module': modname, 'i': loci, 'params': params}
|
||||
f.write('%s\n' % (json.dumps(j)))
|
||||
print('')
|
||||
|
||||
f.close()
|
||||
print(
|
||||
'''endmodule
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
''')
|
||||
|
||||
print(
|
||||
'''
|
||||
module my_PLLE2_ADV (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter CLKOUT0_DIVIDE = 1;
|
||||
parameter CLKOUT1_DIVIDE = 1;
|
||||
parameter CLKOUT2_DIVIDE = 1;
|
||||
parameter CLKOUT3_DIVIDE = 1;
|
||||
parameter CLKOUT4_DIVIDE = 1;
|
||||
parameter CLKOUT5_DIVIDE = 1;
|
||||
parameter DIVCLK_DIVIDE = 1;
|
||||
parameter CLKFBOUT_MULT = 5;
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
PLLE2_ADV #(
|
||||
.CLKOUT0_DIVIDE(CLKOUT0_DIVIDE),
|
||||
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
|
||||
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
|
||||
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
|
||||
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
|
||||
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
|
||||
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
|
||||
.CLKFBOUT_MULT(CLKFBOUT_MULT)
|
||||
) dut(
|
||||
.CLKFBOUT(),
|
||||
.CLKOUT0(dout[0]),
|
||||
.CLKOUT1(),
|
||||
.CLKOUT2(),
|
||||
.CLKOUT3(),
|
||||
.CLKOUT4(),
|
||||
.CLKOUT5(),
|
||||
.DRDY(),
|
||||
.LOCKED(),
|
||||
.DO(),
|
||||
.CLKFBIN(),
|
||||
.CLKIN1(),
|
||||
.CLKIN2(),
|
||||
.CLKINSEL(),
|
||||
.DCLK(),
|
||||
.DEN(),
|
||||
.DWE(),
|
||||
.PWRDWN(),
|
||||
.RST(din[0]),
|
||||
.DI(),
|
||||
.DADDR());
|
||||
endmodule
|
||||
''')
|
||||
Loading…
Reference in New Issue