mirror of https://github.com/openXC7/prjxray.git
ffprim test
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
b4b392ed54
commit
7238939c7b
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@ -0,0 +1,22 @@
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N := 1
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: $(SPECIMENS_OK)
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../../tools/segmatch -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
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pushdb:
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bash ../../utils/mergedb.sh clbll_l seg_clblx.segbits
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bash ../../utils/mergedb.sh clbll_r seg_clblx.segbits
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bash ../../utils/mergedb.sh clblm_l seg_clblx.segbits
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bash ../../utils/mergedb.sh clblm_r seg_clblx.segbits
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
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.PHONY: database pushdb clean
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@ -0,0 +1,40 @@
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Clock inversion is per slice (as BEL CLKINV)
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Vivado GUI is misleading as it often shows it per FF, which is not actually true
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CLB.SLICE_X0.AFF.FF_INV_CLK 00_51
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CLB.SLICE_X1.AFF.FF_INV_CLK <0 candidates>
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Clifford suggests X1 may be in adjacent tile
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as he found with X1 INIT values
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More research needed
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CLB.SLICE_X0.AFF.FF_INV_CLK 00_51
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CLB.SLICE_X0.FF_FDCE 00_21 00_24 00_25 00_26 00_29 00_35 29_01 29_12 30_01 30_03
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CLB.SLICE_X0.FF_FDPE 00_21 00_24 00_25 00_26 00_29 00_35 29_01 30_01
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CLB.SLICE_X0.FF_FDRE 00_21 00_24 00_25 00_26 00_29 29_01 29_12 30_01 30_03
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CLB.SLICE_X0.FF_FDSE 00_21 00_24 00_25 00_26 00_29 00_35 29_01 30_01
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CLB.SLICE_X0.FF_USED 00_21 00_24 00_25 00_26 00_29 29_01 30_01
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CLB.SLICE_X1.AFF.FF_INV_CLK <0 candidates>
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CLB.SLICE_X1.FF_FDCE 00_21 00_24 00_25 00_26 00_29 29_01 30_01 30_04 30_15
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CLB.SLICE_X1.FF_FDPE 00_21 00_24 00_25 00_26 00_29 29_01 30_01
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CLB.SLICE_X1.FF_FDRE 00_21 00_24 00_25 00_26 00_29 00_31 29_01 30_01 30_04 30_15
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CLB.SLICE_X1.FF_FDSE 00_21 00_24 00_25 00_26 00_29 00_31 29_01 30_01
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CLB.SLICE_X1.FF_USED 00_21 00_24 00_25 00_26 00_29 29_01 30_01
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Following bits are always present with a FF
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00_21
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00_24
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00_25
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00_26
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00_29
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29_01
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30_01
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Interesting bits are then
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CLB.SLICE_X0.FF_FDCE 00_35 29_12 30_03
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CLB.SLICE_X0.FF_FDPE 00_35
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CLB.SLICE_X0.FF_FDSE 00_35
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CLB.SLICE_X0.FF_FDRE 29_12 30_03
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@ -0,0 +1,116 @@
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#!/usr/bin/env python3
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import sys, re
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sys.path.append("../../../utils/")
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from segmaker import segmaker
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segmk = segmaker("design.bits")
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ffprims = (
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'FD',
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'FD_1',
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'FDC',
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'FDC_1',
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'FDCE',
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'FDCE_1',
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'FDE',
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'FDE_1',
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'FDP',
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'FDP_1',
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'FDPE',
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'FDPE_1',
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'FDR',
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'FDR_1',
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'FDRE',
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'FDRE_1',
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'FDS',
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'FDS_1',
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'FDSE',
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'FDSE_1',
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)
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ffprims = (
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'FDRE',
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'FDSE',
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'FDCE',
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'FDPE',
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)
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print("Loading tags from design.txt")
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with open("design.txt", "r") as f:
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for line in f:
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'''
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puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
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CLBLM_L CLBLM_L_X10Y137 30 13 SLICE_X13Y137/AFF REG_INIT 1 FDRE
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CLBLM_L CLBLM_L_X10Y137 30 13 SLICE_X12Y137/D5FF FF_INIT 0
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'''
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line = line.split()
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tile_type = line[0]
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tile_name = line[1]
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grid_x = line[2]
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grid_y = line[3]
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# Other code uses BEL name
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site_ff_name = line[4]
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site, ff_name = site_ff_name.split('/')
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ff_type = line[5]
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used = int(line[6])
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ref_name = None
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cel_name = None
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if used:
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cel_name = line[7]
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ref_name = line[8]
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# 1'b1
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# cinv = int(line[9][-1])
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cinv = int(line[9])
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which = ff_name[0]
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# Reduced test for now
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if ff_name != 'AFF':
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continue
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segmk.addtag(site, "FF_USED", used)
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if 1:
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# If unused mark all primitives as not present
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# Otherwise mark the primitive we are using
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for ffprim in ffprims:
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if not used:
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segmk.addtag(site, "FF_%s" % ffprim, 0)
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elif ref_name == ffprim:
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segmk.addtag(site, "FF_%s" % ffprim, 1)
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'''
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Experiment diffing against one of the lower bit set candidates
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can probably isolate a few bits this way
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really though I want to diff against USED but not sure how to do that
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CLB.SLICE_X0.FF_USED <7 candidates>
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CLB.SLICE_X0.FF_FDSE <8 candidates>
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CLB.SLICE_X0.FF_FDPE <8 candidates>
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CLB.SLICE_X0.FF_FDRE <9 candidates>
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CLB.SLICE_X0.FF_FDCE <10 candidates>
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'''
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if 1:
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# If unused mark all primitives as not present
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# Otherwise mark the primitive we are using
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if used:
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base = 'FDSE'
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if ref_name == base:
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for ffprim in ffprims:
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segmk.addtag(site, "FF_DIFF_%s_%s" % (base, fprim, 0)
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for ffprim in ffprims:
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segmk.addtag(site, "FF_%s" % ffprim, 0)
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elif
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segmk.addtag(site, "FF_%s" % ffprim, 1)
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# Compare '_1' negative edge clock to positive edge
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if used:
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#inv_clk = ref_name.endswith("_1")
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inv_clk = cinv
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segmk.addtag(site, "%s.FF_INV_CLK" % ff_name, inv_clk)
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segmk.compile()
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segmk.write()
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@ -0,0 +1,17 @@
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#!/bin/bash
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set -ex
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. ../../utils/genheader.sh
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#echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh
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python3 ../top.py >top.v
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vivado -mode batch -source ../generate.tcl
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for x in design*.bit; do
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../../../tools/bitread -F $XRAY_ROI_FRAMES -o ${x}s -zy $x
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done
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python3 ../generate.py
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@ -0,0 +1,58 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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# Get all FF's in pblock
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set ffs [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ *} */*FF]
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set fp [open "design.txt" w]
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# set ff [lindex $ffs 0]
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# set ff [get_bels SLICE_X23Y100/AFF]
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# proc putl {lst} { foreach line $lst {puts $line} }
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foreach ff $ffs {
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set tile [get_tile -of_objects $ff]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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set type [get_property TYPE $tile]
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set bel_type [get_property TYPE $ff]
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set used [get_property IS_USED $ff]
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set usedstr ""
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if $used {
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set ffc [get_cells -of_objects $ff]
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set cell_bel [get_property BEL $ffc]
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# ex: FDRE
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set ref_name [get_property REF_NAME $ffc]
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#set cinv [get_property IS_C_INVERTED $ffc]
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set cpin [get_pins -of_objects $ffc -filter {REF_PIN_NAME == C}]
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set cinv [get_property IS_INVERTED $cpin]
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set usedstr "$cell_bel $ref_name $cinv"
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}
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puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
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}
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close $fp
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@ -0,0 +1,350 @@
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import random
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CLBN = 600
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# SLICE_X12Y100
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# SLICE_X27Y149
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SLICEX = (12, 28)
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SLICEY = (100, 150)
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# 800
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SLICEN = (SLICEY[1] - SLICEY[0]) * (SLICEX[1] - SLICEX[0])
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print('//SLICEX: %s' % str(SLICEX))
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print('//SLICEY: %s' % str(SLICEY))
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print('//SLICEN: %s' % str(SLICEN))
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print('//Requested CLBs: %s' % str(CLBN))
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def gen_slices():
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for slicey in range(*SLICEY):
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for slicex in range(*SLICEX):
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yield "SLICE_X%dY%d" % (slicex, slicey)
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DIN_N = CLBN * 4
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DOUT_N = CLBN * 1
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clbs = (
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'FD',
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'FD_1',
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'FDC',
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'FDC_1',
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'FDCE',
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'FDCE_1',
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'FDE',
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'FDE_1',
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'FDP',
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'FDP_1',
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'FDPE',
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'FDPE_1',
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'FDR',
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'FDR_1',
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'FDRE',
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'FDRE_1',
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'FDS',
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'FDS_1',
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'FDSE',
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'FDSE_1',
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)
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ff_bels = (
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'AFF',
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'A5FF',
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'BFF',
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'B5FF',
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'CFF',
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'C5FF',
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'DFF',
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'D5FF',
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)
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print('''
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = %d;
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localparam integer DOUT_N = %d;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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''' % (DIN_N, DOUT_N))
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slices = gen_slices()
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print('module roi(input clk, input [%d:0] din, output [%d:0] dout);' % (DIN_N - 1, DOUT_N - 1))
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for i in range(CLBN):
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clb = random.choice(clbs)
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# clb_FD clb_FD (.clk(clk), .din(din[ 0 +: 4]), .dout(dout[ 0]));
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# clb_FD_1 clb_FD_1 (.clk(clk), .din(din[ 4 +: 4]), .dout(dout[ 1]));
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loc = next(slices)
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#bel = random.choice(ff_bels)
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bel = "AFF"
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print(' clb_%s' % clb)
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print(' #(.LOC("%s"), .BEL("%s"))' % (loc, bel))
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print(' clb_%d (.clk(clk), .din(din[ %d +: 4]), .dout(dout[ %d]));' % (i, 4 * i, 1 * i))
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print('''endmodule
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// ---------------------------------------------------------------------
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''')
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print('''
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module clb_FD (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y100";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FD ff (
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.C(clk),
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.Q(dout),
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.D(din[0])
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);
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endmodule
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module clb_FD_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y101";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FD_1 ff (
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.C(clk),
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.Q(dout),
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.D(din[0])
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);
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endmodule
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module clb_FDC (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y102";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDC ff (
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.C(clk),
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.Q(dout),
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.CLR(din[0]),
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.D(din[1])
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);
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endmodule
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module clb_FDC_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y103";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDC_1 ff (
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.C(clk),
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.Q(dout),
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.CLR(din[0]),
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.D(din[1])
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);
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endmodule
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module clb_FDCE (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y104";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDCE ff (
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.C(clk),
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.Q(dout),
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.CE(din[0]),
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.CLR(din[1]),
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.D(din[2])
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);
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endmodule
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module clb_FDCE_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y105";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDCE_1 ff (
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.C(clk),
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.Q(dout),
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.CE(din[0]),
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.CLR(din[1]),
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.D(din[2])
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);
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endmodule
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module clb_FDE (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y106";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDE ff (
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.C(clk),
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.Q(dout),
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.D(din[0]),
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.CE(din[1])
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);
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endmodule
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module clb_FDE_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y107";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDE_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.D(din[0]),
|
||||
.CE(din[1])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDP (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y108";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDP ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.D(din[0]),
|
||||
.PRE(din[1])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDP_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y109";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDP_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.D(din[0]),
|
||||
.PRE(din[1])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDPE (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y110";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDPE ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.CE(din[0]),
|
||||
.PRE(din[1]),
|
||||
.D(din[2])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDPE_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y111";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDPE_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.CE(din[0]),
|
||||
.PRE(din[1]),
|
||||
.D(din[2])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDR (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y112";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDR ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.D(din[0]),
|
||||
.R(din[1])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDR_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y113";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDR_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.D(din[0]),
|
||||
.R(din[1])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDRE (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y114";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDRE ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.CE(din[0]),
|
||||
.R(din[1]),
|
||||
.D(din[2])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDRE_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y115";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDRE_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.CE(din[0]),
|
||||
.R(din[1]),
|
||||
.D(din[2])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDS (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y116";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDS ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.S(din[0]),
|
||||
.D(din[1])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDS_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y117";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDS_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.S(din[0]),
|
||||
.D(din[1])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDSE (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y118";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDSE ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.CE(din[0]),
|
||||
.S(din[1]),
|
||||
.D(din[2])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDSE_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y119";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDSE_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.CE(din[0]),
|
||||
.S(din[1]),
|
||||
.D(din[2])
|
||||
);
|
||||
endmodule
|
||||
''')
|
||||
|
||||
Loading…
Reference in New Issue