mirror of https://github.com/openXC7/prjxray.git
Merge pull request #1503 from antmicro/bits2rbt_and_aux
Add bits2rbt and aux data support to bitread
This commit is contained in:
litghost
GitHub
commit
714f4d9e66
11
Makefile
11
Makefile
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@ -48,7 +48,7 @@ install:
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# ------------------------
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TEST_EXCLUDE = $(foreach x,$(ALL_EXCLUDE) docs fuzzers minitests experiments,--ignore $(x))
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test: test-py test-cpp
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test: test-py test-cpp test-tools
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@true
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test-py:
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@ -61,7 +61,10 @@ test-cpp:
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cd build && ctest --no-compress-output -T Test -C RelWithDebInfo --output-on-failure
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xsltproc .github/kokoro/ctest2junit.xsl build/Testing/*/Test.xml > build/cpp_test_results.xml
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.PHONY: test test-py test-cpp
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test-tools:
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$(MAKE) -f Makefile.tools_tests
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.PHONY: test test-py test-cpp test-tools
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# Run HTML test
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# ------------------------
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@ -73,7 +76,7 @@ test-htmlgen:
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# Auto formatting of code.
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# ------------------------
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FORMAT_EXCLUDE = $(foreach x,$(ALL_EXCLUDE),-and -not -path './$(x)/*') -and -not -name *.bit
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FORMAT_EXCLUDE = $(foreach x,$(ALL_EXCLUDE),-and -not -path './$(x)/*') -and -not -name *.bit -and -not -name *.tar.gz
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CLANG_FORMAT ?= clang-format-5.0
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format-cpp:
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@ -100,7 +103,7 @@ WS_CMD = sed -i '\''s@\s\+$$@@g'\''
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# xargs later) is a file, and not a directory or link. Also filters out .bit
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# files as these are the only binary files currently tracked by Git and we don't
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# want to inadvertently change these at all.
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WS_FILTER = [ -f {} -a ! -L {} ] && [[ {} != *.bit ]]
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WS_FILTER = [ -f {} -a ! -L {} ] && [[ {} != *.bit ]] && [[ {} != *.tar.gz ]]
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# For every file piped to $(WS_FORMAT) apply the filter and perform the command,
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# if a file does not match the filter, just returns true.
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@ -0,0 +1,45 @@
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SHELL=/bin/bash
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BITREAD = build/tools/bitread
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BITS2RBT = build/tools/bits2rbt/bits2rbt
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TEST_DATA_PATH = lib/test_data
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#FIXME Uncomment bits2rbt_bram_xc7 once https://github.com/SymbiFlow/prjxray/issues/1285 is fixed
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BITS2RBT_TESTS = bits2rbt_xc7 #bits2rbt_bram_xc7
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TESTS = $(BITS2RBT_TESTS)
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bits2rbt_xc7_ARGS_1 = -part_file build/Series7/part.yaml -architecture Series7 -y -o build/xc7.bits -aux build/xc7.aux build/Series7/design.bit
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bits2rbt_xc7_ARGS_2 = -arch Series7 -aux build/xc7.aux -o build/xc7.rbt build/xc7.bits
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bits2rbt_xc7_TEST = diff <(tail -n +8 build/Series7/design.rbt) <(tail -n +8 build/xc7.rbt)
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bits2rbt_bram_xc7_ARGS_1 = -part_file build/Series7/part.yaml -architecture Series7 -y -o build/bram_xc7.bits -aux build/bram_xc7.aux build/Series7/bram.bit
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bits2rbt_bram_xc7_ARGS_2 = -arch Series7 -aux build/bram_xc7.aux -o build/bram_xc7.rbt build/bram_xc7.bits
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bits2rbt_bram_xc7_TEST = diff <(tail -n +8 build/Series7/bram.rbt) <(tail -n +8 build/bram_xc7.rbt)
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all: $(TESTS)
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test_data: $(TEST_DATA_PATH)/ToolsTestData.tar.gz
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@echo "Unpacking test data"
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tar -zxf $< -C build
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define bitread_test_tpl =
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$(1): $(2) $(3) test_data
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@echo "Started test $(1)"
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$(2) $$($(1)_ARGS_1) > /dev/null && $(3) $$($(1)_ARGS_2) > /dev/null && $$($(1)_TEST); \
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RETVAL=$$$$? ; \
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if [ $$$$RETVAL -eq 0 ]; then \
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echo "$(1) PASS"; \
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true; \
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else \
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echo "$(1) FAIL"; \
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false; \
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fi
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$(1)_clean:
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rm -rf build/*.frm build/*.aux build/*.bits build/*.rbt
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endef
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$(foreach test,$(BITS2RBT_TESTS),$(eval $(call bitread_test_tpl,$(test),$(BITREAD),$(BITS2RBT))))
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clean: $(foreach test,$(TESTS),$(test)_clean)
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@true
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@ -68,6 +68,14 @@ class BitstreamReader {
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static absl::optional<BitstreamReader<ArchType>> InitWithBytes(
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T bitstream);
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// Extract information from bitstream necessary to reconstruct RBT
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// header and add it to the AUX data
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template <typename T>
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static void PrintHeader(T bitstream, FILE* aux_fp);
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// Extract configuration logic data and add to the AUX data
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void PrintFpgaConfigurationLogicData(FILE* aux_fp);
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const std::vector<uint32_t>& words() { return words_; };
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// Returns an iterator that yields `ConfigurationPackets`
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@ -76,11 +84,59 @@ class BitstreamReader {
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iterator end();
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private:
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static std::array<uint8_t, 4> kSyncWord;
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static const std::array<uint8_t, 4> kSyncWord;
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static const std::array<uint32_t, 2> kWcfgCmd;
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static const std::array<uint32_t, 2> kNullCmd;
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std::vector<uint32_t> words_;
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};
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// Extract FPGA configuration logic information
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template <typename ArchType>
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void BitstreamReader<ArchType>::PrintFpgaConfigurationLogicData(
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FILE* aux_fp) {
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// Get the data before the first FDRI_WRITE command packet
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const auto fpga_conf_end = std::search(
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words_.cbegin(), words_.cend(), kWcfgCmd.cbegin(), kWcfgCmd.cend());
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fprintf(aux_fp, "FPGA configuration logic prefix:");
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for (auto it = words_.cbegin(); it != fpga_conf_end; ++it) {
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fprintf(aux_fp, " %08X", *it);
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}
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fprintf(aux_fp, "\n");
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// Get the data after the last Null Command packet
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const auto last_null_cmd = std::find_end(
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words_.cbegin(), words_.cend(), kNullCmd.cbegin(), kNullCmd.cend());
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fprintf(aux_fp, "FPGA configuration logic suffix:");
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for (auto it = last_null_cmd; it != words_.cend(); ++it) {
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fprintf(aux_fp, " %08X", *it);
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}
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fprintf(aux_fp, "\n");
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}
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template <typename ArchType>
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template <typename T>
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void BitstreamReader<ArchType>::PrintHeader(T bitstream, FILE* aux_fp) {
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// If this is really a Xilinx bitstream, there will be a sync
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// word somewhere toward the beginning.
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auto sync_pos = std::search(bitstream.begin(), bitstream.end(),
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kSyncWord.begin(), kSyncWord.end());
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if (sync_pos == bitstream.end()) {
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return;
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}
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sync_pos += kSyncWord.size();
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// Wrap the provided container in a span that strips off the preamble.
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absl::Span<typename T::value_type> bitstream_span(bitstream);
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auto header_packets =
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bitstream_span.subspan(0, sync_pos - bitstream.begin());
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fprintf(aux_fp, "Header bytes:");
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for (auto& word : header_packets) {
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fprintf(aux_fp, " %02X", word);
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}
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fprintf(aux_fp, "\n");
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}
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template <typename ArchType>
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template <typename T>
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absl::optional<BitstreamReader<ArchType>>
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@ -111,9 +167,19 @@ BitstreamReader<ArchType>::InitWithBytes(T bitstream) {
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// Sync word as specified in UG470 page 81
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template <typename ArchType>
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std::array<uint8_t, 4> BitstreamReader<ArchType>::kSyncWord{0xAA, 0x99, 0x55,
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const std::array<uint8_t, 4> BitstreamReader<ArchType>::kSyncWord{0xAA, 0x99, 0x55,
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0x66};
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// Writing the WCFG(0x1) command in type 1 packet with 1 word to the CMD register (0x30008001)
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// Refer to UG470 page 110
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template <typename ArchType>
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const std::array<uint32_t, 2> BitstreamReader<ArchType>::kWcfgCmd = {0x30008001, 0x1};
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// Writing the NULL(0x0) command in type 1 packet with 1 word to the CMD register (0x30008001)
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// Refer to UG470 page 110
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template <typename ArchType>
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const std::array<uint32_t, 2> BitstreamReader<ArchType>::kNullCmd = {0x30008001, 0x0};
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template <typename ArchType>
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typename BitstreamReader<ArchType>::iterator
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BitstreamReader<ArchType>::begin() {
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@ -68,6 +68,7 @@ class Configuration {
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const typename ArchType::Part& part() const { return part_; }
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const FrameMap& frames() const { return frames_; }
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void PrintFrameAddresses(FILE* fp);
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private:
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typename ArchType::Part part_;
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@ -358,6 +359,19 @@ Configuration<ArchType>::InitWithPackets(const typename ArchType::Part& part,
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return Configuration(part, frames);
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}
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template <typename ArchType>
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void Configuration<ArchType>::PrintFrameAddresses(FILE* fp) {
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fprintf(fp, "Frame addresses in bitstream: ");
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for (auto frame = frames_.begin(); frame != frames_.end(); ++frame) {
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fprintf(fp, "%08X", (int)frame->first);
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if (std::next(frame) != frames_.end()) {
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fprintf(fp, " ");
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} else {
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fprintf(fp, "\n");
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}
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}
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}
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} // namespace xilinx
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} // namespace prjxray
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Binary file not shown.
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@ -34,4 +34,6 @@ target_link_libraries(xc7frames2bit
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libprjxray
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)
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add_subdirectory(bits2rbt)
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install(TARGETS xc7frames2bit xc7patch gen_part_base_yaml frame_address_decoder bittool segmatch bitread DESTINATION bin)
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@ -54,6 +54,10 @@ DEFINE_string(part_file, "", "YAML file describing a Xilinx part");
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DEFINE_string(architecture,
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"Series7",
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"Architecture of the provided bitstream");
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DEFINE_string(
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aux,
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"",
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"write machine-readable output file with auxiliary bitstream data");
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namespace xilinx = prjxray::xilinx;
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@ -115,6 +119,25 @@ struct BitReader {
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fprintf(f, "\n");
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}
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if (!FLAGS_aux.empty()) {
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FILE* aux_file = fopen(FLAGS_aux.c_str(), "w");
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if (aux_file == nullptr) {
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printf(
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"Can't open aux output file '%s' for "
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"writing!\n",
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FLAGS_aux.c_str());
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return 1;
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}
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// Extract and decode header information as in RBT file
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xilinx::BitstreamReader<ArchType>::PrintHeader(
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bytes_, aux_file);
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// Extract FPGA configuration logic information
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reader->PrintFpgaConfigurationLogicData(aux_file);
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// Extract configuration frames' addresses
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config->PrintFrameAddresses(aux_file);
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fclose(aux_file);
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}
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std::vector<std::vector<bool>> pgmdata;
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std::vector<int> pgmsep;
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@ -0,0 +1,5 @@
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add_executable(bits2rbt bits2rbt.cc
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configuration_packets.cc
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header.cc
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ecc.cc)
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target_link_libraries(bits2rbt absl::strings gflags)
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@ -0,0 +1,44 @@
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#include <gflags/gflags.h>
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#include <fstream>
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#include <iostream>
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#include "configuration_packets.h"
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DEFINE_string(o, "", "Output RBT file");
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DEFINE_string(aux, "", "Input auxiliary data file");
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DEFINE_string(arch, "Series7", "FPGA architecture");
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int main(int argc, char** argv) {
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gflags::ParseCommandLineFlags(&argc, &argv, true);
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if (argc != 2) {
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std::cerr << "Error: Input bits file not specified"
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<< std::endl;
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return 1;
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}
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std::ofstream out_file;
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if (!FLAGS_o.empty()) {
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out_file.open(FLAGS_o.c_str(), std::ofstream::out);
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if (!out_file.good()) {
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std::cerr << "Error: Can't open output file\n";
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return 1;
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}
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}
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std::ostream& out = (FLAGS_o.empty()) ? std::cout : out_file;
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try {
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std::shared_ptr<ConfigurationPackets> packets =
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ConfigurationPackets::InitFromFile(argv[1], FLAGS_arch);
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packets->AddAuxData(FLAGS_aux);
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packets->WriteBits(out);
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} catch (std::runtime_error& e) {
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std::cerr << "Error: " << e.what();
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return 1;
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}
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if (!FLAGS_o.empty()) {
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out_file.close();
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}
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return 0;
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}
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@ -0,0 +1,241 @@
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#include <absl/strings/str_split.h>
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#include <algorithm>
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#include <bitset>
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#include <fstream>
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#include <iomanip>
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#include <iostream>
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#include <stdexcept>
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#include <string>
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#include "configuration_packets.h"
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#include "crc.h"
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#include "ecc.h"
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#include "header.h"
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ConfigurationPackets::ConfigurationPackets(const std::string& arch)
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: words_per_frame_(words_in_architecture.at(arch)),
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architecture_(arch),
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ecc_(arch, words_per_frame_) {}
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const std::unordered_map<std::string, size_t>
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ConfigurationPackets::words_in_architecture = {{"Series7", 101},
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{"UltraScale", 123},
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{"UltraScalePlus", 93}};
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std::shared_ptr<ConfigurationPackets> ConfigurationPackets::InitFromFile(
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const std::string& file,
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const std::string& arch) {
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std::ifstream ifs(file, std::ifstream::in);
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if (!ifs.good()) {
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throw std::runtime_error("Couldn't open bits file\n");
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}
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if (words_in_architecture.find(arch) == words_in_architecture.end()) {
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throw std::runtime_error("Error: Unrecognized architecture " +
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arch + "\n");
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}
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std::shared_ptr<ConfigurationPackets> packets =
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std::make_shared<ConfigurationPackets>(arch);
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packets->SetBits(ifs);
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packets->UpdateECCs();
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return packets;
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}
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void ConfigurationPackets::SetBits(std::ifstream& ifs) {
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while (!ifs.eof()) {
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std::string line;
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getline(ifs, line);
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SetBit(line);
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}
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}
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void ConfigurationPackets::WriteBits(std::ostream& out) {
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header_->Write(out);
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WriteFpgaConfiguration(out, fpga_configuration_head_);
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WriteConfiguration(out);
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WriteFpgaConfiguration(out, fpga_configuration_tail_);
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}
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void ConfigurationPackets::WriteFpgaConfiguration(
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std::ostream& out,
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const std::vector<uint32_t>& vect) {
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for (auto& word : vect) {
|
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out << std::bitset<32>(word) << std::endl;
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}
|
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}
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|
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void ConfigurationPackets::WriteConfiguration(std::ostream& out) {
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for (auto packet = configuration_data_packets_.cbegin();
|
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packet != configuration_data_packets_.cend(); ++packet) {
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WritePacket(out, packet);
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if (IsDifferentRow(packet, std::next(packet))) {
|
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// Write the zero frame at the end of each row
|
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WritePacket(out, packet);
|
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}
|
||||
}
|
||||
}
|
||||
|
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void ConfigurationPackets::WritePacket(
|
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std::ostream& out,
|
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ConfigurationFrames::const_iterator frame_citr) const {
|
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bool is_new_row(false);
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if ((frame_citr == configuration_data_packets_.cbegin()) ||
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IsDifferentRow(frame_citr, std::prev(frame_citr))) {
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// Write the WCFG command followed by a FAR write with address
|
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// of the next frame WCFG command write
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out << std::bitset<32>(kCmdWrite | 0x1) << std::endl;
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out << std::bitset<32>(0x1) << std::endl;
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out << std::bitset<32>(kNop) << std::endl;
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// FAR Write of the next frame followed by frame address
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out << std::bitset<32>(kFarWrite | 0x1) << std::endl;
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out << std::bitset<32>(frame_citr->first) << std::endl;
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if (architecture_ == "Series7") {
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out << std::bitset<32>(kNop) << std::endl;
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}
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is_new_row = true;
|
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}
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uint32_t crc(GetCRC(frame_citr, is_new_row));
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// FDRI Write
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out << std::bitset<32>(kFdriWrite | words_per_frame_) << std::endl;
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||||
// Declared number of configuration words
|
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for (auto& word : frame_citr->second) {
|
||||
out << std::bitset<32>(word) << std::endl;
|
||||
}
|
||||
// FAR Write followed by frame address
|
||||
out << std::bitset<32>(kFarWrite | 0x1) << std::endl;
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||||
out << std::bitset<32>(frame_citr->first) << std::endl;
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// CRC Write followed by packet CRC
|
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out << std::bitset<32>(kCrcWrite | 0x1) << std::endl;
|
||||
out << std::bitset<32>(crc) << std::endl;
|
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}
|
||||
|
||||
void ConfigurationPackets::SetBit(const std::string& line) {
|
||||
if (line.empty()) {
|
||||
return;
|
||||
}
|
||||
uint32_t frame_address, word, bit;
|
||||
sscanf(line.c_str(), "bit_%08x_%03u_%02u", &frame_address, &word, &bit);
|
||||
if (configuration_data_packets_.find(frame_address) ==
|
||||
configuration_data_packets_.end()) {
|
||||
configuration_data_packets_[frame_address] =
|
||||
std::vector<uint32_t>(words_per_frame_, 0x0);
|
||||
}
|
||||
configuration_data_packets_[frame_address].at(word) |= (1 << bit);
|
||||
}
|
||||
|
||||
void ConfigurationPackets::Line2Vector(const std::string& line,
|
||||
std::vector<uint32_t>& vect) {
|
||||
static std::function<uint32_t(const std::string& str)> str_to_uint =
|
||||
[](const std::string& str) -> uint32_t {
|
||||
assert(!str.empty());
|
||||
return std::stoul(str, nullptr, 16);
|
||||
};
|
||||
// Skip the line content description before the conversion
|
||||
std::vector<std::string> str_vector =
|
||||
absl::StrSplit(line.substr(line.find(":") + 2), " ");
|
||||
std::transform(str_vector.begin(), str_vector.end(),
|
||||
std::back_inserter(vect), str_to_uint);
|
||||
}
|
||||
|
||||
void ConfigurationPackets::AddAuxData(const std::string& file) {
|
||||
std::ifstream ifs(file, std::ifstream::in);
|
||||
if (!ifs.good()) {
|
||||
throw std::runtime_error("Couldn't open auxiliary data file\n");
|
||||
}
|
||||
|
||||
std::string line;
|
||||
getline(ifs, line);
|
||||
InitializeHeader(line);
|
||||
getline(ifs, line);
|
||||
InitializeFpgaConfigurationHead(line);
|
||||
getline(ifs, line);
|
||||
InitializeFpgaConfigurationTail(line);
|
||||
getline(ifs, line);
|
||||
InitializeConfigurationData(line);
|
||||
}
|
||||
|
||||
uint32_t ConfigurationPackets::GetFpgaConfigurationCRC() const {
|
||||
uint32_t crc(0);
|
||||
auto far = std::search(fpga_configuration_head_.begin(),
|
||||
fpga_configuration_head_.end(), kRCrcCmd.begin(),
|
||||
kRCrcCmd.end());
|
||||
for (auto itr = far + kRCrcCmd.size();
|
||||
itr != fpga_configuration_head_.end(); ++itr) {
|
||||
if (*itr == kNop)
|
||||
continue;
|
||||
// Check if it is a write packet
|
||||
assert(*itr & 0x30000000);
|
||||
// Get the packet address
|
||||
uint32_t addr = (*itr >> 13) & 0x1F;
|
||||
std::advance(itr, 1);
|
||||
assert(itr != fpga_configuration_head_.end());
|
||||
crc = icap_crc(addr, *itr, crc);
|
||||
}
|
||||
return crc;
|
||||
}
|
||||
|
||||
uint32_t ConfigurationPackets::GetCRC(
|
||||
ConfigurationFrames::const_iterator frame_citr,
|
||||
bool is_new_row) const {
|
||||
uint32_t crc = 0;
|
||||
if (is_new_row) {
|
||||
if (frame_citr == configuration_data_packets_.begin()) {
|
||||
crc = GetFpgaConfigurationCRC();
|
||||
}
|
||||
crc = icap_crc(kCmdReg, kWcfgCmd, crc);
|
||||
crc = icap_crc(kFarReg, frame_citr->first, crc);
|
||||
}
|
||||
for (const auto& word : frame_citr->second) {
|
||||
crc = icap_crc(kFdriReg, word, crc);
|
||||
}
|
||||
crc = icap_crc(kFarReg, frame_citr->first, crc);
|
||||
return crc;
|
||||
}
|
||||
|
||||
void ConfigurationPackets::UpdateECCs() {
|
||||
for (auto& packet : configuration_data_packets_) {
|
||||
auto& data = packet.second;
|
||||
ecc_.UpdateFrameECC(data);
|
||||
}
|
||||
}
|
||||
|
||||
void ConfigurationPackets::InitializeConfigurationData(
|
||||
const std::string& line) {
|
||||
std::function<void(const uint32_t&)> update_packets =
|
||||
[this](const uint32_t& addr) {
|
||||
if (configuration_data_packets_.find(addr) ==
|
||||
configuration_data_packets_.end()) {
|
||||
configuration_data_packets_[addr] =
|
||||
std::vector<uint32_t>(words_per_frame_, 0x0);
|
||||
}
|
||||
};
|
||||
std::vector<uint32_t> frames_addr;
|
||||
Line2Vector(line, frames_addr);
|
||||
std::for_each(frames_addr.begin(), frames_addr.end(), update_packets);
|
||||
}
|
||||
|
||||
void ConfigurationPackets::InitializeFpgaConfigurationHead(
|
||||
const std::string& line) {
|
||||
Line2Vector(line, fpga_configuration_head_);
|
||||
}
|
||||
|
||||
void ConfigurationPackets::InitializeFpgaConfigurationTail(
|
||||
const std::string& line) {
|
||||
Line2Vector(line, fpga_configuration_tail_);
|
||||
}
|
||||
|
||||
void ConfigurationPackets::InitializeHeader(const std::string& line) {
|
||||
// FIXME Remove the configuration data head part once the aux data is
|
||||
// fixed
|
||||
header_ = std::make_unique<Header>(line, fpga_configuration_head_);
|
||||
}
|
||||
|
||||
bool ConfigurationPackets::IsDifferentRow(
|
||||
ConfigurationFrames::const_iterator frame_citr1,
|
||||
ConfigurationFrames::const_iterator frame_citr2) const {
|
||||
auto get_row = [this](const uint32_t& address) {
|
||||
size_t row_shift =
|
||||
(architecture_ == "UltraScalePlus") ? 18 : 17;
|
||||
return (address >> row_shift) & 0x3FF;
|
||||
};
|
||||
return (get_row(frame_citr1->first) != get_row(frame_citr2->first));
|
||||
}
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
#ifndef CONFIGURATION_PACKETS_H_
|
||||
#define CONFIGURATION_PACKETS_H_
|
||||
#include <array>
|
||||
#include <map>
|
||||
#include <memory>
|
||||
#include <unordered_map>
|
||||
|
||||
#include "ecc.h"
|
||||
#include "header.h"
|
||||
|
||||
class ConfigurationPackets {
|
||||
public:
|
||||
ConfigurationPackets(const std::string& arch);
|
||||
static const std::unordered_map<std::string, size_t>
|
||||
words_in_architecture;
|
||||
static std::shared_ptr<ConfigurationPackets> InitFromFile(
|
||||
const std::string& file,
|
||||
const std::string& arch);
|
||||
void AddAuxData(const std::string& file);
|
||||
void WriteBits(std::ostream& out);
|
||||
void SetBits(std::ifstream& ifs);
|
||||
|
||||
private:
|
||||
using ConfigurationFrame = std::pair<uint32_t, std::vector<uint32_t>>;
|
||||
using ConfigurationFrames = std::map<uint32_t, std::vector<uint32_t>>;
|
||||
// Refer to UG470 page 109 for address of configuration registers and commands
|
||||
const uint32_t kCmdWrite = 0x30008000;
|
||||
const uint32_t kFdriWrite = 0x30004000;
|
||||
const uint32_t kFarWrite = 0x30002000;
|
||||
const uint32_t kCrcWrite = 0x30000000;
|
||||
const uint32_t kNop = 0x20000000;
|
||||
const uint32_t kFarReg = 0x1;
|
||||
const uint32_t kFdriReg = 0x2;
|
||||
const uint32_t kCmdReg = 0x4;
|
||||
const uint32_t kWcfgCmd = 0x1;
|
||||
// Writing the RCRC(0x7) command in type 1 packet with 1 word to the CMD register (0x30008001)
|
||||
const std::array<uint32_t, 2> kRCrcCmd = {{0x30008001, 0x7}};
|
||||
size_t words_per_frame_;
|
||||
std::string architecture_;
|
||||
ConfigurationFrames configuration_data_packets_;
|
||||
std::vector<uint32_t> fpga_configuration_head_;
|
||||
std::vector<uint32_t> fpga_configuration_tail_;
|
||||
std::unique_ptr<Header> header_;
|
||||
ECC ecc_;
|
||||
|
||||
void InitializeConfigurationData(const std::string& line);
|
||||
void InitializeFpgaConfigurationHead(const std::string& line);
|
||||
void InitializeFpgaConfigurationTail(const std::string& line);
|
||||
void InitializeHeader(const std::string& line);
|
||||
uint32_t GetCRC(ConfigurationFrames::const_iterator frame_citr,
|
||||
bool is_new_row = false) const;
|
||||
uint32_t GetFpgaConfigurationCRC() const;
|
||||
void UpdateECCs();
|
||||
void SetBit(const std::string& line);
|
||||
void WriteConfiguration(std::ostream& out);
|
||||
void WriteFpgaConfiguration(std::ostream& out,
|
||||
const std::vector<uint32_t>& vect);
|
||||
void WritePacket(std::ostream& out,
|
||||
ConfigurationFrames::const_iterator frame_citr) const;
|
||||
bool IsDifferentRow(
|
||||
ConfigurationFrames::const_iterator frame_citr1,
|
||||
ConfigurationFrames::const_iterator frame_citr2) const;
|
||||
void Line2Vector(const std::string& line, std::vector<uint32_t>& vect);
|
||||
};
|
||||
#endif // CONFIGURATION_PACKETS_H_
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
uint32_t icap_crc(uint32_t addr, uint32_t data, uint32_t prev) {
|
||||
int kAddressBitWidth = 5;
|
||||
constexpr int kDataBitWidth = 32;
|
||||
constexpr uint32_t kCrc32CastagnoliPolynomial = 0x82F63B78;
|
||||
|
||||
uint64_t poly = static_cast<uint64_t>(kCrc32CastagnoliPolynomial) << 1;
|
||||
uint64_t val = (static_cast<uint64_t>(addr) << 32) | data;
|
||||
uint64_t crc = prev;
|
||||
|
||||
for (int i = 0; i < kAddressBitWidth + kDataBitWidth; i++) {
|
||||
if ((val & 1) != (crc & 1))
|
||||
crc ^= poly;
|
||||
|
||||
val >>= 1;
|
||||
crc >>= 1;
|
||||
}
|
||||
return crc;
|
||||
}
|
||||
|
|
@ -0,0 +1,107 @@
|
|||
#include "ecc.h"
|
||||
#include <cassert>
|
||||
#include <iostream>
|
||||
|
||||
const std::unordered_map<std::string, size_t> ECC::ecc_word_per_architecture = {
|
||||
{"Series7", 50},
|
||||
{"UltraScale", 60},
|
||||
{"UltraScalePlus", 45}};
|
||||
|
||||
uint32_t ECC::GetSeries7WordEcc(uint32_t idx,
|
||||
uint32_t data,
|
||||
uint32_t ecc) const {
|
||||
uint32_t val = idx * 32; // bit offset
|
||||
|
||||
if (idx > 0x25) // avoid 0x800
|
||||
val += 0x1360;
|
||||
else if (idx > 0x6) // avoid 0x400
|
||||
val += 0x1340;
|
||||
else // avoid lower
|
||||
val += 0x1320;
|
||||
|
||||
if (idx == 0x32) // mask ECC
|
||||
data &= 0xFFFFE000;
|
||||
|
||||
for (int i = 0; i < 32; i++) {
|
||||
if (data & 1)
|
||||
ecc ^= val + i;
|
||||
|
||||
data >>= 1;
|
||||
}
|
||||
|
||||
if (idx == 0x64) { // last index
|
||||
uint32_t v = ecc & 0xFFF;
|
||||
v ^= v >> 8;
|
||||
v ^= v >> 4;
|
||||
v ^= v >> 2;
|
||||
v ^= v >> 1;
|
||||
ecc ^= (v & 1) << 12; // parity
|
||||
}
|
||||
|
||||
return ecc;
|
||||
}
|
||||
|
||||
uint64_t ECC::GetUSEccFrameOffset(int word, int bit) const {
|
||||
int nib = bit / 4;
|
||||
int nibbit = bit % 4;
|
||||
// ECC offset is expanded to 1 bit per nibble,
|
||||
// and then shifted based on the bit index in nibble
|
||||
// e.g. word 3, bit 9
|
||||
// offset: 0b10100110010 - concatenate (3 + (255 - last_frame_index(e.g.
|
||||
// 92 for US+)) [frame offset] and 9/4 [nibble offset] becomes:
|
||||
// 0x10100110010 shifted by bit in nibble (9%4): 0x20200220020
|
||||
uint32_t offset = (word + (255 - (frame_words_ - 1))) << 3 | nib;
|
||||
uint64_t exp_offset = 0;
|
||||
// Odd parity
|
||||
offset ^= (1 << 11);
|
||||
for (int i = 0; i < 11; i++)
|
||||
if (offset & (1 << i))
|
||||
offset ^= (1 << 11);
|
||||
// Expansion
|
||||
for (int i = 0; i < 12; i++)
|
||||
if (offset & (1 << i))
|
||||
exp_offset |= (1ULL << (4 * i));
|
||||
return exp_offset << nibbit;
|
||||
};
|
||||
|
||||
uint64_t ECC::GetUSWordEcc(uint32_t idx, uint32_t data, uint64_t ecc) const {
|
||||
if (idx == ecc_word_) {
|
||||
data = 0x0;
|
||||
}
|
||||
if (idx == ecc_word_ + 1) {
|
||||
data &= 0xffff0000;
|
||||
}
|
||||
for (int i = 0; i < 32; i++) {
|
||||
if (data & 1) {
|
||||
ecc ^= GetUSEccFrameOffset(idx, i);
|
||||
}
|
||||
data >>= 1;
|
||||
}
|
||||
return ecc;
|
||||
}
|
||||
|
||||
uint64_t ECC::CalculateECC(const std::vector<uint32_t>& data) const {
|
||||
uint64_t ecc = 0;
|
||||
for (size_t w = 0; w < data.size(); ++w) {
|
||||
const uint32_t& word = data.at(w);
|
||||
if (architecture_ == "Series7") {
|
||||
ecc = GetSeries7WordEcc(w, word, ecc);
|
||||
} else {
|
||||
ecc = GetUSWordEcc(w, word, ecc);
|
||||
}
|
||||
}
|
||||
return ecc;
|
||||
}
|
||||
|
||||
void ECC::UpdateFrameECC(std::vector<uint32_t>& data) const {
|
||||
assert(data.size() >= ecc_word_);
|
||||
uint64_t ecc(CalculateECC(data));
|
||||
if (architecture_ == "Series7") {
|
||||
data[ecc_word_] &= 0xffffe000;
|
||||
data[ecc_word_] |= ecc & 0x1fff;
|
||||
} else {
|
||||
data[ecc_word_] = ecc;
|
||||
data[ecc_word_ + 1] &= 0xffff0000;
|
||||
data[ecc_word_ + 1] |= (ecc >> 32) & 0xffff;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
#ifndef ECC_H_
|
||||
#define ECC_H_
|
||||
|
||||
#include <cstdint>
|
||||
#include <string>
|
||||
#include <unordered_map>
|
||||
#include <vector>
|
||||
|
||||
class ECC {
|
||||
public:
|
||||
ECC(const std::string& architecture, size_t words_per_frame)
|
||||
: architecture_(architecture),
|
||||
frame_words_(words_per_frame),
|
||||
ecc_word_(ecc_word_per_architecture.at(architecture)) {}
|
||||
|
||||
void UpdateFrameECC(std::vector<uint32_t>& data) const;
|
||||
|
||||
private:
|
||||
const std::string architecture_;
|
||||
const size_t frame_words_;
|
||||
const size_t ecc_word_;
|
||||
static const std::unordered_map<std::string, size_t>
|
||||
ecc_word_per_architecture;
|
||||
|
||||
uint64_t CalculateECC(const std::vector<uint32_t>& words) const;
|
||||
uint64_t GetUSEccFrameOffset(int word, int bit) const;
|
||||
uint32_t GetSeries7WordEcc(uint32_t idx,
|
||||
uint32_t data,
|
||||
uint32_t ecc) const;
|
||||
uint64_t GetUSWordEcc(uint32_t idx, uint32_t data, uint64_t ecc) const;
|
||||
};
|
||||
|
||||
#endif // ECC_H_
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
#include "header.h"
|
||||
#include <algorithm>
|
||||
#include <ctime>
|
||||
#include <sstream>
|
||||
|
||||
Header::Header(const std::string& line,
|
||||
std::vector<uint32_t>& fpga_config_packets) {
|
||||
absl::string_view header_str(line);
|
||||
// Go to tag 'a' of the TLV formatted header
|
||||
header_str.remove_prefix(header_str.find("61"));
|
||||
bool tlv_header_end = false;
|
||||
while (!tlv_header_end) {
|
||||
char tag = char(GetByteAndAdvance(header_str));
|
||||
switch (tag) {
|
||||
case 'a':
|
||||
design_name_ = GetTLVHeaderValue(header_str);
|
||||
break;
|
||||
case 'b':
|
||||
part_ = GetTLVHeaderValue(header_str);
|
||||
break;
|
||||
case 'c':
|
||||
date_ = GetTLVHeaderValue(header_str);
|
||||
break;
|
||||
case 'd':
|
||||
date_ += " " + GetTLVHeaderValue(header_str);
|
||||
break;
|
||||
case 'e':
|
||||
// Get number of bytes in bitstream and multiply
|
||||
// by 8 to obtain number of bits
|
||||
no_bits_ = GetWord(header_str) * 8;
|
||||
tlv_header_end = true;
|
||||
break;
|
||||
default:
|
||||
assert(false);
|
||||
}
|
||||
}
|
||||
while (!header_str.empty()) {
|
||||
fpga_config_packets.emplace_back(GetWord(header_str));
|
||||
}
|
||||
}
|
||||
|
||||
std::string Header::GetDate() {
|
||||
int year, month, day, hour, min, sec;
|
||||
std::replace_if(date_.begin(), date_.end(),
|
||||
[](char c) { return c == '/' or c == ':'; }, ' ');
|
||||
std::istringstream(date_) >> year >> month >> day >> hour >> min >> sec;
|
||||
std::tm time_raw = {sec, min, hour, day, month - 1, year - 1900};
|
||||
time_t time = mktime(&time_raw);
|
||||
const std::tm* time_out = std::localtime(&time);
|
||||
return std::string(std::asctime(time_out));
|
||||
}
|
||||
|
||||
std::string Header::GetArchitecture() {
|
||||
if (part_.find("xczu") != std::string::npos) {
|
||||
return "zynquplus";
|
||||
}
|
||||
if (part_.find("7a") != std::string::npos) {
|
||||
return "artix7";
|
||||
}
|
||||
if (part_.find("xcku") != std::string::npos) {
|
||||
return "kintexu";
|
||||
}
|
||||
return "Unknown architecture";
|
||||
}
|
||||
|
||||
void Header::Write(std::ostream& out) {
|
||||
out << "Xilinx ASCII Bitstream" << std::endl;
|
||||
out << "Created by" << std::endl;
|
||||
out << "Design name: " << design_name_ << std::endl;
|
||||
out << "Architecture: " << GetArchitecture() << std::endl;
|
||||
out << "Part: " << part_ << std::endl;
|
||||
out << "Date: " << GetDate();
|
||||
out << "Bits: " << no_bits_ << std::endl;
|
||||
}
|
||||
|
||||
size_t Header::GetByteAndAdvance(absl::string_view& str_view) {
|
||||
size_t space_pos(str_view.find(" "));
|
||||
size_t byte =
|
||||
std::stoul(std::string(str_view.substr(0, space_pos)), nullptr, 16);
|
||||
str_view.remove_prefix((space_pos != absl::string_view::npos)
|
||||
? space_pos + 1
|
||||
: str_view.size());
|
||||
return byte;
|
||||
}
|
||||
|
||||
size_t Header::GetTLVHeaderLength(absl::string_view& str_view) {
|
||||
return (GetByteAndAdvance(str_view) << 8) | GetByteAndAdvance(str_view);
|
||||
}
|
||||
|
||||
std::string Header::GetTLVHeaderValue(absl::string_view& str_view) {
|
||||
size_t length(GetTLVHeaderLength(str_view));
|
||||
std::string value;
|
||||
for (size_t i = 0; i < length; i++) {
|
||||
value += char(GetByteAndAdvance(str_view));
|
||||
}
|
||||
// Lose trailing 0x00
|
||||
value.pop_back();
|
||||
return value;
|
||||
}
|
||||
|
||||
uint32_t Header::GetWord(absl::string_view& str_view) {
|
||||
return (GetByteAndAdvance(str_view) << 24) |
|
||||
(GetByteAndAdvance(str_view) << 16) |
|
||||
(GetByteAndAdvance(str_view) << 8) | GetByteAndAdvance(str_view);
|
||||
}
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
#ifndef HEADER_H_
|
||||
#define HEADER_H_
|
||||
#include <absl/strings/string_view.h>
|
||||
#include <iostream>
|
||||
#include <string>
|
||||
#include <vector>
|
||||
|
||||
class Header {
|
||||
public:
|
||||
Header(const std::string& line,
|
||||
std::vector<uint32_t>& fpga_config_packets);
|
||||
void Write(std::ostream& out);
|
||||
|
||||
private:
|
||||
std::string design_name_;
|
||||
std::string part_;
|
||||
std::string date_;
|
||||
uint32_t no_bits_;
|
||||
|
||||
std::string GetTLVHeaderValue(absl::string_view& str_view);
|
||||
uint32_t GetWord(absl::string_view& str_view);
|
||||
size_t GetTLVHeaderLength(absl::string_view& str_view);
|
||||
size_t GetByteAndAdvance(absl::string_view& str_view);
|
||||
std::string GetDate();
|
||||
std::string GetArchitecture();
|
||||
};
|
||||
#endif // HEADER_H_
|
||||
Loading…
Reference in New Issue