Merge pull request #60 from mcmasterg/slice_x01

fasm: slice site name as 0/1 instead of global coordinate. Test cleanup
This commit is contained in:
John McMaster 2018-01-23 15:27:21 -08:00 committed by GitHub
commit 7110a67c55
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15 changed files with 39 additions and 84 deletions

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@ -144,34 +144,7 @@ def run(f_in, f_out, sparse=False, debug=False):
segdb = get_database(segj['type'])
def clb2dbkey(tile, tilej, site, suffix, value):
def slice_global2x01(tile_name, tile_type, site):
# SLICE_X12Y102 => SLICEL_X0
m = re.match(r'SLICE_X([0-9]+)Y[0-9]+', site)
xg = int(m.group(1))
prefix = {
'CLBLL_L': {
0: 'SLICEL',
1: 'SLICEL'
},
'CLBLM_L': {
0: 'SLICEM',
1: 'SLICEL'
},
'CLBLL_R': {
0: 'SLICEL',
1: 'SLICEL'
},
'CLBLM_R': {
0: 'SLICEM',
1: 'SLICEL'
},
}
x01 = xg % 2
return '%s_X%d' % (prefix[tile_type][x01], x01)
db_site = slice_global2x01(tile, tilej['type'], site)
db_k = '%s.%s.%s' % (tilej['type'], db_site, suffix)
db_k = '%s.%s.%s' % (tilej['type'], site, suffix)
return db_k
def int2dbkey(tile, tilej, site, suffix, value):

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@ -11,25 +11,7 @@ def tag2fasm(grid, seg, tag):
segj = grid['segments'][seg]
def clbf(seg, tile, tag_post):
# seg: SEG_CLBLM_L_X10Y102
# tile_type: CLBLM_L
# tag_post: SLICEM_X0.ALUT.INIT[43]
# To: CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[43] 1
m = re.match(r'(SLICE[LM])_X([01])[.](.*)', tag_post)
slicelm = m.group(1)
off01 = int(m.group(2))
post = m.group(3)
# xxx: actually this might not work on decimal overflow (9 => 10)
for site in grid['tiles'][tile]['sites'].keys():
m = re.match(r'SLICE_X(.*)Y.*', site)
sitex = int(m.group(1))
if sitex % 2 == off01:
break
else:
raise Exception("Failed to match site")
return '%s.%s.%s 1' % (tile, site, post)
return '%s.%s 1' % (tile, tag_post)
def intf(seg, tile, tag_post):
# Make the selection an argument of the configruation

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@ -2,13 +2,13 @@
# segprint -zd test_data/clb_ff/design.bits
# FF as LDCE
CLBLM_L_X10Y102.SLICE_X12Y102.AFF.DMUX.AX 1
CLBLM_L_X10Y102.SLICE_X12Y102.AFF.ZINI 1
CLBLM_L_X10Y102.SLICE_X12Y102.AFF.ZRST 1
CLBLM_L_X10Y102.SLICE_X12Y102.CEUSEDMUX 1
CLBLM_L_X10Y102.SLICE_X12Y102.SRUSEDMUX 1
# CLBLM_L_X10Y102.SLICE_X12Y102.FFSYNC 0
# CLBLM_L_X10Y102.SLICE_X12Y102.LATCH 0
CLBLM_L_X10Y102.SLICEM_X0.AFF.DMUX.AX 1
CLBLM_L_X10Y102.SLICEM_X0.AFF.ZINI 1
CLBLM_L_X10Y102.SLICEM_X0.AFF.ZRST 1
CLBLM_L_X10Y102.SLICEM_X0.CEUSEDMUX 1
CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX 1
# CLBLM_L_X10Y102.SLICEM_X0.FFSYNC 0
# CLBLM_L_X10Y102.SLICEM_X0.LATCH 0
# Note: a number of pseudo pips here
# Omitted

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@ -1,15 +1,15 @@
# LUT
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[00] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[08] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[10] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[11] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[13] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[14] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[15] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[41] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[43] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[44] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[46] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[47] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[63] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[00] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[08] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[10] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[11] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[13] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[14] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[15] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[41] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[43] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[44] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[46] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[47] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[63] 1

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@ -2,19 +2,19 @@
# segprint -zd test_data/clb_lut/design.bits
# LUT
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[00] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[08] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[10] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[11] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[13] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[14] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[15] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[41] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[43] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[44] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[46] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[47] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[63] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[00] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[08] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[10] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[11] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[13] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[14] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[15] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[41] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[43] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[44] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[46] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[47] 1
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[63] 1
# din bus
# din[0]

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@ -68,11 +68,11 @@ class TestStringMethods(unittest.TestCase):
def test_lut_int(self):
self.bitread_frm_equals(
'test_data/lut_int.fasm', 'test_data/clb_lut/design.bits')
'test_data/lut_int.fasm', 'test_data/lut_int/design.bits')
def test_ff_int(self):
self.bitread_frm_equals(
'test_data/ff_int.fasm', 'test_data/clb_ff/design.bits')
'test_data/ff_int.fasm', 'test_data/ff_int/design.bits')
def test_sparse(self):
'''Verify sparse equivilent to normal encoding'''

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@ -33,11 +33,11 @@ class TestStringMethods(unittest.TestCase):
def test_lut_int(self):
self.check_segprint_fasm_equiv(
'test_data/clb_lut/design.segp', 'test_data/lut_int.fasm')
'test_data/lut_int/design.segp', 'test_data/lut_int.fasm')
def test_ff_int(self):
self.check_segprint_fasm_equiv(
'test_data/clb_ff/design.segp', 'test_data/ff_int.fasm')
'test_data/ff_int/design.segp', 'test_data/ff_int.fasm')
if __name__ == '__main__':