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Merge pull request #76 from mithro/master 

Rename flip-flop muxes to make Vivado GUI names.
This commit is contained in:
Tim Ansell 2018-02-13 10:49:33 -08:00 committed by GitHub
parent 284953c044 21a33e50a1
commit 6fe77dedae
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GPG Key ID: 4AEE18F83AFDEB23
6 changed files with 77 additions and 75 deletions
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4
fuzzers/012-clbn5ffmux/generate.py
View File

@ -26,7 +26,7 @@ for l in f:
# Theory: there is one bit for each mux positon
# In each config 3 muxes are in one position, other 3 are in another
inv = int(i == n)
segmk.addtag(loc, "%c5FF.MUX.A" % which, def_a ^ inv)
segmk.addtag(loc, "%c5FF.MUX.B" % which, 1 ^ def_a ^ inv)
segmk.addtag(loc, "%c5FFMUX.IN_A" % which, def_a ^ inv)
segmk.addtag(loc, "%c5FFMUX.IN_B" % which, 1 ^ def_a ^ inv)
segmk.compile()
segmk.write()

66
fuzzers/015-clbnffmux/README.md
View File

@ -1,42 +1,42 @@
Purpose:
Document AFFMUX family of CLB muxes
Document nFFMUX family of CLB muxes
Algorithm:
Outcome:
CLB.SLICE_X0.AFF.DMUX.B0 30_00
CLB.SLICE_X0.AFF.DMUX.B1 30_01
CLB.SLICE_X0.AFF.DMUX.B2 30_02
CLB.SLICE_X0.AFF.DMUX.B3 30_03
CLB.SLICE_X0.BFF.DMUX.B0 30_27
CLB.SLICE_X0.BFF.DMUX.B1 30_26
CLB.SLICE_X0.BFF.DMUX.B2 30_25
CLB.SLICE_X0.BFF.DMUX.B3 30_24
CLB.SLICE_X0.CFF.DMUX.B0 30_35
CLB.SLICE_X0.CFF.DMUX.B1 30_36
CLB.SLICE_X0.CFF.DMUX.B2 30_37
CLB.SLICE_X0.CFF.DMUX.B3 30_38
CLB.SLICE_X0.DFF.DMUX.B0 30_62
CLB.SLICE_X0.DFF.DMUX.B1 30_61
CLB.SLICE_X0.DFF.DMUX.B2 30_60
CLB.SLICE_X0.DFF.DMUX.B3 30_59
CLB.SLICE_X1.AFF.DMUX.B0 31_00
CLB.SLICE_X1.AFF.DMUX.B1 31_01
CLB.SLICE_X1.AFF.DMUX.B2 31_02
CLB.SLICE_X1.AFF.DMUX.B3 30_04
CLB.SLICE_X1.BFF.DMUX.B0 31_25
CLB.SLICE_X1.BFF.DMUX.B1 31_27
CLB.SLICE_X1.BFF.DMUX.B2 31_26
CLB.SLICE_X1.BFF.DMUX.B3 31_24
CLB.SLICE_X1.CFF.DMUX.B0 31_35
CLB.SLICE_X1.CFF.DMUX.B1 31_38
CLB.SLICE_X1.CFF.DMUX.B2 31_37
CLB.SLICE_X1.CFF.DMUX.B3 31_36
CLB.SLICE_X1.DFF.DMUX.B0 30_58
CLB.SLICE_X1.DFF.DMUX.B1 31_61
CLB.SLICE_X1.DFF.DMUX.B2 31_62
CLB.SLICE_X1.DFF.DMUX.B3 31_60
CLB.SLICE_X0.AFFMUX.B0 30_00
CLB.SLICE_X0.AFFMUX.B1 30_01
CLB.SLICE_X0.AFFMUX.B2 30_02
CLB.SLICE_X0.AFFMUX.B3 30_03
CLB.SLICE_X0.BFFMUX.B0 30_27
CLB.SLICE_X0.BFFMUX.B1 30_26
CLB.SLICE_X0.BFFMUX.B2 30_25
CLB.SLICE_X0.BFFMUX.B3 30_24
CLB.SLICE_X0.CFFMUX.B0 30_35
CLB.SLICE_X0.CFFMUX.B1 30_36
CLB.SLICE_X0.CFFMUX.B2 30_37
CLB.SLICE_X0.CFFMUX.B3 30_38
CLB.SLICE_X0.DFFMUX.B0 30_62
CLB.SLICE_X0.DFFMUX.B1 30_61
CLB.SLICE_X0.DFFMUX.B2 30_60
CLB.SLICE_X0.DFFMUX.B3 30_59
CLB.SLICE_X1.AFFMUX.B0 31_00
CLB.SLICE_X1.AFFMUX.B1 31_01
CLB.SLICE_X1.AFFMUX.B2 31_02
CLB.SLICE_X1.AFFMUX.B3 30_04
CLB.SLICE_X1.BFFMUX.B0 31_25
CLB.SLICE_X1.BFFMUX.B1 31_27
CLB.SLICE_X1.BFFMUX.B2 31_26
CLB.SLICE_X1.BFFMUX.B3 31_24
CLB.SLICE_X1.CFFMUX.B0 31_35
CLB.SLICE_X1.CFFMUX.B1 31_38
CLB.SLICE_X1.CFFMUX.B2 31_37
CLB.SLICE_X1.CFFMUX.B3 31_36
CLB.SLICE_X1.DFFMUX.B0 30_58
CLB.SLICE_X1.DFFMUX.B1 31_61
CLB.SLICE_X1.DFFMUX.B2 31_62
CLB.SLICE_X1.DFFMUX.B3 31_60

4
fuzzers/015-clbnffmux/generate.py
View File

@ -52,7 +52,7 @@ for l in f:
src = which + "X"
# add the 1-tag for this connection
tag = "%sFF.DMUX.%s" % (which, src)
tag = "%sFFMUX.%s" % (which, src)
segmk.addtag(loc, tag, 1)
# remove this MUX from the cache, preventing generation of 0-tags for this MUX
@ -65,7 +65,7 @@ for loc, muxes in cache.items():
if src == "F7" and which not in "AC": continue
if src == "F8" and which not in "B": continue
if src == "AX": src = which + "X"
tag = "%sFF.DMUX.%s" % (which, src)
tag = "%sFFMUX.%s" % (which, src)
segmk.addtag(loc, tag, 0)

66
fuzzers/016-clbnoutmux/README.md
View File

@ -1,43 +1,43 @@
Purpose:
Document AOUTMUX family of CLB muxes
Document nOUTMUX family of CLB muxes
TODO: document O6
Algorithm:
Outcome:
CLB.SLICE_X0.AMUX.B0 30_11
CLB.SLICE_X0.AMUX.B1 30_08
CLB.SLICE_X0.AMUX.B2 30_06
CLB.SLICE_X0.AMUX.B3 30_07
CLB.SLICE_X0.BMUX.B0 30_20
CLB.SLICE_X0.BMUX.B1 30_21
CLB.SLICE_X0.BMUX.B2 30_22
CLB.SLICE_X0.BMUX.B3 30_23
CLB.SLICE_X0.CMUX.B0 30_45
CLB.SLICE_X0.CMUX.B1 30_44
CLB.SLICE_X0.CMUX.B2 30_40
CLB.SLICE_X0.CMUX.B3 30_43
CLB.SLICE_X0.DMUX.B0 30_56
CLB.SLICE_X0.DMUX.B1 30_51
CLB.SLICE_X0.DMUX.B2 30_52
CLB.SLICE_X0.DMUX.B3 30_57
CLB.SLICE_X1.AMUX.B0 31_09
CLB.SLICE_X1.AMUX.B1 31_07
CLB.SLICE_X1.AMUX.B2 31_10
CLB.SLICE_X1.AMUX.B3 30_05
CLB.SLICE_X1.BMUX.B0 31_20
CLB.SLICE_X1.BMUX.B1 30_28
CLB.SLICE_X1.BMUX.B2 31_21
CLB.SLICE_X1.BMUX.B3 30_29
CLB.SLICE_X1.CMUX.B0 31_43
CLB.SLICE_X1.CMUX.B1 30_42
CLB.SLICE_X1.CMUX.B2 31_40
CLB.SLICE_X1.CMUX.B3 30_41
CLB.SLICE_X1.DMUX.B0 31_56
CLB.SLICE_X1.DMUX.B1 30_53
CLB.SLICE_X1.DMUX.B2 31_57
CLB.SLICE_X1.DMUX.B3 31_53
CLB.SLICE_X0.AOUTMUX.B0 30_11
CLB.SLICE_X0.AOUTMUX.B1 30_08
CLB.SLICE_X0.AOUTMUX.B2 30_06
CLB.SLICE_X0.AOUTMUX.B3 30_07
CLB.SLICE_X0.BOUTMUX.B0 30_20
CLB.SLICE_X0.BOUTMUX.B1 30_21
CLB.SLICE_X0.BOUTMUX.B2 30_22
CLB.SLICE_X0.BOUTMUX.B3 30_23
CLB.SLICE_X0.COUTMUX.B0 30_45
CLB.SLICE_X0.COUTMUX.B1 30_44
CLB.SLICE_X0.COUTMUX.B2 30_40
CLB.SLICE_X0.COUTMUX.B3 30_43
CLB.SLICE_X0.DOUTMUX.B0 30_56
CLB.SLICE_X0.DOUTMUX.B1 30_51
CLB.SLICE_X0.DOUTMUX.B2 30_52
CLB.SLICE_X0.DOUTMUX.B3 30_57
CLB.SLICE_X1.AOUTMUX.B0 31_09
CLB.SLICE_X1.AOUTMUX.B1 31_07
CLB.SLICE_X1.AOUTMUX.B2 31_10
CLB.SLICE_X1.AOUTMUX.B3 30_05
CLB.SLICE_X1.BOUTMUX.B0 31_20
CLB.SLICE_X1.BOUTMUX.B1 30_28
CLB.SLICE_X1.BOUTMUX.B2 31_21
CLB.SLICE_X1.BOUTMUX.B3 30_29
CLB.SLICE_X1.COUTMUX.B0 31_43
CLB.SLICE_X1.COUTMUX.B1 30_42
CLB.SLICE_X1.COUTMUX.B2 31_40
CLB.SLICE_X1.COUTMUX.B3 30_41
CLB.SLICE_X1.DOUTMUX.B0 31_56
CLB.SLICE_X1.DOUTMUX.B1 30_53
CLB.SLICE_X1.DOUTMUX.B2 31_57
CLB.SLICE_X1.DOUTMUX.B3 31_53
From manual O6 testing

4
fuzzers/016-clbnoutmux/generate.py
View File

@ -52,7 +52,7 @@ for l in f:
src = which + "5Q"
# add the 1-tag for this connection
tag = "%sMUX.%s" % (which, src)
tag = "%sOUTMUX.%s" % (which, src)
segmk.addtag(loc, tag, 1)
# remove this MUX from the cache, preventing generation of 0-tags for this MUX
@ -65,7 +65,7 @@ for loc, muxes in cache.items():
if src == "F7" and which not in "AC": continue
if src == "F8" and which not in "B": continue
if src == "5Q": src = which + "5Q"
tag = "%sMUX.%s" % (which, src)
tag = "%sOUTMUX.%s" % (which, src)
segmk.addtag(loc, tag, 0)

8
htmlgen/htmlgen.py
View File

@ -202,6 +202,7 @@ for segname, segdata in grid["segments"].items():
routebits[segtype][bit].add(bit_name)
def add_single_bit(line):
print(line)
bit_name, bit_pos = line.split()
assert bit_pos[0] != "!"
segbits[segtype][bit_name] = bit_pos
@ -211,7 +212,8 @@ for segname, segdata in grid["segments"].items():
print(" loading %s segbits." % segtype)
with db_open("segbits_%s.db" % segtype) as f:
for line in f:
if re.search(r"(\.[ABCD]MUX\.)|(\.PRECYINIT\.)", line):
if re.search(r"(\.[ABCD](5?FF|OUT)MUX\.)|(\.PRECYINIT\.)",
line):
add_pip_bits(line)
else:
add_single_bit(line)
@ -578,12 +580,12 @@ function oml() {
bgcolor = "#4466bb"
label = "LH"
elif re.match(
"^CLBL[LM]_[LR].SLICE[LM]_X[01].[ABCD]FF.DMUX",
"^CLBL[LM]_[LR].SLICE[LM]_X[01].[ABCD]FFMUX",
bn):
bgcolor = "#88aaff"
label = "DMX"
elif re.match(
"^CLBL[LM]_[LR].SLICE[LM]_X[01].[ABCD]MUX",
"^CLBL[LM]_[LR].SLICE[LM]_X[01].[ABCD]OUTMUX",
bn):
bgcolor = "#aa88ff"
label = "OMX"