mirror of https://github.com/openXC7/prjxray.git
Initial working GCLK to HROW_CLK PIP fuzzer.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
3b10ceed54
commit
6fd2cb4eec
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@ -0,0 +1,26 @@
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N ?= 50
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include ../fuzzer.mk
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database: build/segbits_clk_hrow.db
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build/segbits_clk_hrow.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o build/segbits_clk_hrow.rdb \
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$(addsuffix /segdata_clk_hrow_top_r.txt,$(SPECIMENS)) \
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$(addsuffix /segdata_clk_hrow_bot_r.txt,$(SPECIMENS))
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build/segbits_clk_hrow.db: build/segbits_clk_hrow.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_clk_hrow.rdb \
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--seg-fn-out build/segbits_clk_hrow.db
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${XRAY_MASKMERGE} build/mask_clk_hrow.db \
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$(addsuffix /segdata_clk_hrow_top_r.txt,$(SPECIMENS)) \
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$(addsuffix /segdata_clk_hrow_bot_r.txt,$(SPECIMENS))
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pushdb: database
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${XRAY_MERGEDB} clk_hrow_bot_r build/segbits_clk_hrow.db
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${XRAY_MERGEDB} clk_hrow_top_r build/segbits_clk_hrow.db
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${XRAY_MERGEDB} mask_clk_hrow_bot_r build/mask_clk_hrow.db
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${XRAY_MERGEDB} mask_clk_hrow_top_r build/mask_clk_hrow.db
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.PHONY: database pushdb
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@ -0,0 +1,21 @@
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proc print_tile_pips {tile_type filename} {
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set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
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puts "Dumping PIPs for tile $tile ($tile_type) to $filename."
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set fp [open $filename w]
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foreach pip [lsort [get_pips -of_objects [get_tiles $tile]]] {
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set src [get_wires -uphill -of_objects $pip]
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set dst [get_wires -downhill -of_objects $pip]
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if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
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puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
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}
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}
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close $fp
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}
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create_project -force -part $::env(XRAY_PART) design design
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set_property design_mode PinPlanning [current_fileset]
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open_io_design -name io_1
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print_tile_pips CLK_HROW_TOP_R clk_hrow_top_r.txt
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print_tile_pips CLK_HROW_BOT_R clk_hrow_bot_r.txt
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print_tile_pips CLK_BUFG_REBUF clk_bufg_rebuf.txt
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@ -0,0 +1,51 @@
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#!/usr/bin/env python3
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from prjxray.segmaker import Segmaker
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import re
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def main():
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segmk = Segmaker("design.bits")
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print("Loading tags from design.txt.")
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with open("design.txt", "r") as f:
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for line in f:
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tile, pip, src, dst, pnum, pdir = line.split()
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if not tile.startswith('CLK_HROW'):
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continue
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pip_prefix, pip = pip.split(".")
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tile_from_pip, tile_type = pip_prefix.split('/')
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assert tile == tile_from_pip
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_, src = src.split("/")
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_, dst = dst.split("/")
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rows = set(range(8))
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columns = set(range(4))
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m = re.match('^CLK_HROW_R_CK_GCLK([0-9]+)$', src)
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if m:
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gclk = int(m.group(1))
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row = gclk % 8
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column = int(gclk / 8)
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segmk.add_tile_tag(tile, '{}.GCLK_ENABLE_ROW{}'.format(dst, row), 1)
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segmk.add_tile_tag(tile, '{}.GCLK_ENABLE_COLUMN{}'.format(dst, column), 1)
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rows.remove(row)
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columns.remove(column)
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for row in rows:
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segmk.add_tile_tag(tile, '{}.GCLK_ENABLE_ROW{}'.format(dst, row), 0)
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for column in columns:
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segmk.add_tile_tag(tile, '{}.GCLK_ENABLE_COLUMN{}'.format(dst, column), 0)
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segmk.compile()
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segmk.write()
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if __name__ == '__main__':
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main()
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@ -0,0 +1,43 @@
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proc write_pip_txtdata {filename} {
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puts "FUZ([pwd]): Writing $filename."
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set fp [open $filename w]
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set nets [get_nets -hierarchical]
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set nnets [llength $nets]
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set neti 0
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foreach net $nets {
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incr neti
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if {($neti % 100) == 0 } {
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puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)"
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}
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foreach pip [get_pips -of_objects $net] {
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set tile [get_tiles -of_objects $pip]
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set src_wire [get_wires -uphill -of_objects $pip]
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set dst_wire [get_wires -downhill -of_objects $pip]
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set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
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set dir_prop [get_property IS_DIRECTIONAL $pip]
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puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
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}
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}
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close $fp
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}
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-161}]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_pip_txtdata design.txt
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}
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run
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@ -0,0 +1,11 @@
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create_project -force -part $::env(XRAY_PART) design design
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set_property design_mode PinPlanning [current_fileset]
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open_io_design -name io_1
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set fp [open "cmt_regions.csv" "w"]
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foreach site_type {MMCME2_ADV PLLE2_ADV BUFHCE} {
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foreach site [get_sites -filter "SITE_TYPE == $site_type"] {
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puts $fp "$site,[get_property CLOCK_REGION $site]"
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}
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}
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close $fp
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@ -0,0 +1,190 @@
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import os
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import re
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray.db import Database
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XY_RE = re.compile('^BUFHCE_X([0-9]+)Y([0-9]+)$')
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BUFGCTRL_XY_RE = re.compile('^BUFGCTRL_X([0-9]+)Y([0-9]+)$')
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"""
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BUFHCE's can be driven from:
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MMCME2_ADV
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BUFHCE
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PLLE2_ADV
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BUFGCTRL
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"""
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def get_xy(s):
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m = BUFGCTRL_XY_RE.match(s)
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x = int(m.group(1))
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y = int(m.group(2))
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return x, y
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def gen_sites(desired_site_type):
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db = Database(util.get_db_root())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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for site, site_type in gridinfo.sites.items():
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if site_type == desired_site_type:
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yield site
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def gen_bufhce_sites():
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db = Database(util.get_db_root())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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sites = []
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for site, site_type in gridinfo.sites.items():
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if site_type == 'BUFHCE':
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sites.append(site)
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if sites:
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yield tile_name, sorted(sites)
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def read_site_to_cmt():
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with open(os.path.join(os.getenv('FUZDIR'), 'build', 'cmt_regions.csv')) as f:
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for l in f:
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site, cmt = l.strip().split(',')
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yield (site, cmt)
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CMT_RE = re.compile('X([0-9]+)Y([0-9]+)')
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class ClockSources(object):
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def __init__(self):
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self.sources = {}
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self.merged_sources = {}
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def add_clock_source(self, source, cmt):
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if cmt not in self.sources:
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self.sources[cmt] = []
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self.sources[cmt].append(source)
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def get_random_source(self, cmt):
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if cmt not in self.merged_sources:
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choices = []
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choices.extend(self.sources['ANY'])
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if cmt in self.sources:
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choices.extend(self.sources[cmt])
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m = CMT_RE.match(cmt)
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x = int(m.group(1))
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y = int(m.group(2))
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if x % 2 == 0:
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x += 1
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else:
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x -= 1
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paired_cmt = 'X{}Y{}'.format(x, y)
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if paired_cmt in self.sources:
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choices.extend(self.sources[paired_cmt])
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self.merged_sources[cmt] = choices
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return random.choice(self.merged_sources[cmt])
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def other_sources():
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site_to_cmt = dict(read_site_to_cmt())
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clock_sources = ClockSources()
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clock_sources.add_clock_source('one', 'ANY')
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clock_sources.add_clock_source('zero', 'ANY')
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print("""
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wire zero = 0;
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wire one = 1;""")
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for idx in range(1):
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wire_name = "lut_wire_{}".format(idx)
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clock_sources.add_clock_source(wire_name, 'ANY')
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print("""
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(* KEEP, DONT_TOUCH *)
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wire {wire_name};
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LUT6 lut{idx} (
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.O({wire_name})
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);""".format(
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idx=idx,
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wire_name=wire_name,
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))
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for site in gen_sites('PLLE2_ADV'):
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pll_clocks = ['pll_clock_{site}_{idx}'.format(site=site, idx=idx) for
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idx in range(6)]
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for clk in pll_clocks[:2]:
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clock_sources.add_clock_source(clk, site_to_cmt[site])
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print("""
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wire {c0}, {c1}, {c2}, {c3}, {c4}, {c5};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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PLLE2_ADV pll_{site} (
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.CLKOUT0({c0}),
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.CLKOUT1({c1}),
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.CLKOUT2({c2}),
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.CLKOUT3({c3}),
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.CLKOUT4({c4}),
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.CLKOUT5({c5})
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);
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""".format(
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site=site,
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c0=pll_clocks[0],
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c1=pll_clocks[1],
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c2=pll_clocks[2],
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c3=pll_clocks[3],
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c4=pll_clocks[4],
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c5=pll_clocks[5],
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))
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def main():
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print('''
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module top();
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''')
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gclks = []
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for site in sorted(gen_sites("BUFGCTRL"), key=get_xy):
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wire_name = 'clk_{}'.format(site)
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gclks.append(wire_name)
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print("""
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wire {wire_name};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFG bufg_{site} (
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.O({wire_name})
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);
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""".format(
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site=site,
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wire_name=wire_name,
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))
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bufhce_sites = list(gen_bufhce_sites())
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for tile_name, sites in bufhce_sites:
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for site in sites:
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print("""
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFHCE buf_{site} (
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.I({wire_name})
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);
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""".format(
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site=site,
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wire_name=random.choice(gclks),
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))
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print("endmodule")
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if __name__ == '__main__':
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main()
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