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bram: TDP minitest 

Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster 2018-10-30 10:51:23 -07:00
parent 8171030058
commit 6c2b04a7bf
3 changed files with 31 additions and 1 deletions
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2
minitests/bram_basic/Makefile
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@ -44,4 +44,6 @@ build/roi_bram18_width.diff:
build/roi_bram18_write_mode.diff:
$(MAKE) -f diff.mk OUT_DIFF=build/roi_bram18_write_mode.diff PRJL=roi_bram18_write_mode_a PRJR=roi_bram18_write_mode_b
build/roi_bram18_ram_mode.diff:
$(MAKE) -f diff.mk OUT_DIFF=build/roi_bram18_ram_mode.diff PRJL=roi_bram18_ram_mode_tdp PRJR=roi_bram18_ram_mode_sdp

2
minitests/bram_basic/runme.tcl
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@ -25,5 +25,7 @@ route_design
write_checkpoint -force design.dcp
# set_property BITSTREAM.GENERAL.DEBUGBITSTREAM Yes [current_design]
# BRAM SDP WEA check, to make test slightly easier to write
set_property IS_ENABLED 0 [get_drc_checks {REQP-1931}]
write_bitstream -force design.bit

28
minitests/bram_basic/top.v
View File

@ -266,7 +266,7 @@ module roi_hck(input clk, input [255:0] din, output [255:0] dout);
endmodule
/******************************************************************************
Misc ROI
READ_WIDTH
******************************************************************************/
module roi_bram18_width_a(input clk, input [255:0] din, output [255:0] dout);
@ -281,6 +281,9 @@ module roi_bram18_width_b(input clk, input [255:0] din, output [255:0] dout);
endmodule
/******************************************************************************
WRITE_MODE
******************************************************************************/
module roi_bram18_write_mode_a(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .WRITE_MODE_A("WRITE_FIRST"))
@ -293,6 +296,29 @@ module roi_bram18_write_mode_b(input clk, input [255:0] din, output [255:0] dout
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
/******************************************************************************
RAM_MODE
******************************************************************************/
module roi_bram18_ram_mode_tdp(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .RAM_MODE("TDP"))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
/*
ERROR: [DRC REQP-1931] RAMB18E1_WEA_NO_CONNECT_OR_TIED_GND:
roi/r0/ram programming per UG473 requires that for SDP mode the WEA bus must be unconnected
or tied to GND.
Are these routing bits are real bits we need to look at?
> bit_0002031b_002_00
> bit_0002031b_002_04
*/
module roi_bram18_ram_mode_sdp(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .RAM_MODE("SDP"))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
/******************************************************************************
Library
******************************************************************************/