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065-gtp-common-pips: add comments 

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi 2021-02-02 19:34:52 +01:00
parent f48608dd1c
commit 6ad64bc4fa
2 changed files with 25 additions and 9 deletions
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4
fuzzers/065-gtp-common-pips/generate.py
View File

@ -17,9 +17,13 @@ import os.path
def bitfilter(frame, word):
word = int(word / 32)
# Clock-related PIPs in the GTP_COMMON_MID_[LEFT|RIGHT] have bits
# from frame 0 to 7, hence, all the other frames are skipped.
if frame not in [0, 1, 2, 3, 4, 5, 6, 7]:
return False
# All the Clock-related PIPs have bits at word 50 in the GTP_COMMON tile.
# Filter out all bits not belonging to word 50.
if word != 50:
return False

30
fuzzers/065-gtp-common-pips/generate.tcl
View File

@ -131,10 +131,14 @@ proc get_nets_with_todo_pip_wires {direction net_regexp wire_regexp used_destina
}
proc route_todo {} {
set verbose false
set used_destinations [dict create]
# Re-route GTP-related nets, which are originated from the GTPE2_CHANNEL and/or IBUFDS_GTE2 primitives.
set todo_map [load_todo "dsts"]
set gtp_channel_nets [get_nets_with_todo_pip_wires "dsts" "gtp_channel_clock" "GTPE2_COMMON_\[TR\]XOUTCLK_MUX_\[0123\]" $used_destinations true]
set ibufds_nets [get_nets_with_todo_pip_wires "dsts" "ibufds_clock" "IBUFDS_GTPE2_\[01\]_MGTCLKOUT_MUX" $used_destinations true]
set gtp_channel_nets [get_nets_with_todo_pip_wires "dsts" "gtp_channel_clock" "GTPE2_COMMON_\[TR\]XOUTCLK_MUX_\[0123\]" $used_destinations $verbose]
set ibufds_nets [get_nets_with_todo_pip_wires "dsts" "ibufds_clock" "IBUFDS_GTPE2_\[01\]_MGTCLKOUT_MUX" $used_destinations $verbose]
set gtp_nets [dict merge $gtp_channel_nets $ibufds_nets]
puts "GTP nets: $gtp_nets"
dict for {net tile_wire} $gtp_nets {
@ -213,9 +217,10 @@ proc route_todo {} {
}
}
# Re-route CMT-related nets, which are originated from the fabric's PLL/MMCM primitives
set todo_map [load_todo "srcs"]
set pll_nets [get_nets_with_todo_pip_wires "srcs" "pll_clock" "HCLK_GTP_CK_IN" $used_destinations true true]
set mmcm_nets [get_nets_with_todo_pip_wires "srcs" "mmcm_clock" "HCLK_GTP_CK_IN" $used_destinations true true]
set pll_nets [get_nets_with_todo_pip_wires "srcs" "pll_clock" "HCLK_GTP_CK_IN" $used_destinations $verbose true]
set mmcm_nets [get_nets_with_todo_pip_wires "srcs" "mmcm_clock" "HCLK_GTP_CK_IN" $used_destinations $verbose true]
set cmt_nets [dict merge $pll_nets $mmcm_nets]
puts "CMT nets: $cmt_nets"
dict for {net tile_wire} $cmt_nets {
@ -230,19 +235,25 @@ proc route_todo {} {
continue
}
# All clock nets which have a source belonging to a PLL/MMCM tile can be routed to any
# HCLK_GTP_CK_MUX --> HCLK_GTP_CK_IN wire pair, hence we build a list of all the remaining
# PIPs to choose from.
puts "Rerouting net $net at $tile / $wire (type $tile_type)"
puts "Previous target wire: $old_origin_dst_wire"
set old_origin_node [get_nodes -of_objects $old_origin_dst_wire]
if [regexp "HCLK_GTP_CK_IN.*" $old_origin_dst_wire match group] {
set old_target_side $group
}
foreach dst $dsts {
set srcs [dict get $todo_map $dst]
foreach src $srcs {
# For each HCLK_GTP_CK_IN wire, get the source node (HCLK_GTP_CK_MUX) from the todo_map
# that still needs to be documented.
#
# Each HCLK_GTP_CK_IN has two possible HCLK_GTP_CK_MUX sources to be paired with.
set src_wire [lindex $src 1]
# There are PIPs that do connect HCLK_GTP_CK_IN wires to GTP_CHANNEL- and IBUFDS-related wires.
#
# These kinds of PIPs are solved at a previous stage of this process, hence, the todo PIP list should
# not contain these src/dst pairs at this stage, but only PIPs to the fabric (PLL/MMCM nets).
set is_gtp_net 1
if [regexp "HCLK_GTP_CK_MUX.*" $src_wire match group] {
set is_gtp_net 0
@ -282,6 +293,7 @@ proc route_todo {} {
set used_dst_wire [dict exists $used_destinations "$tile/$dst_wire"]
set used_src_wire [dict exists $used_destinations "$tile/$src_wire"]
# If one between MUX or IN wire pairs is already used, skip this todo
if { $used_dst_wire || $used_src_wire } {
puts "Not routing to $tile / $src_wire or $dst_wire, in use."
continue