Add fuzzers/005-tilegrid/

Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>

database/artix7/settings.sh

@@ -1,3 +1,4 @@
+export XRAY_DATABASE="artix7"
 export XRAY_PART="xc7a50tfgg484-1"
 export XRAY_ROI="SLICE_X12Y100:SLICE_X27Y149"
 export XRAY_ROI_FRAMES="0x00020500:0x000208ff"

fuzzers/005-tilegrid/.gitignore

@@ -0,0 +1,2 @@
+/specimen_[0-9][0-9][0-9]/
+/database.txt

fuzzers/005-tilegrid/Makefile

@@ -0,0 +1,20 @@
+
+N := 1
+SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
+SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
+
+database.txt: $(SPECIMENS_OK)
+	: ../../tools/segmatch -o database.txt \
+		$(addsuffix /segdata_0.txt,$(SPECIMENS)) \
+		$(addsuffix /segdata_1.txt,$(SPECIMENS)) \
+		$(addsuffix /segdata_2.txt,$(SPECIMENS))
+
+$(SPECIMENS_OK):
+	bash generate.sh $(subst /OK,,$@)
+	touch $@
+
+clean:
+	rm -rf $(SPECIMENS)
+
+.PHONY: clean
+

fuzzers/005-tilegrid/generate.py

@@ -0,0 +1,24 @@
+#!/usr/bin/env python3
+
+import os, sys, json, re
+
+database = dict()
+
+tiles = list()
+site_baseaddr = dict()
+
+with open("tiles.txt") as f:
+    for line in f:
+        tiles.append(line.split())
+
+for arg in sys.argv[1:]:
+    with open(arg) as f:
+        line = f.read().strip()
+        site = arg[7:-6]
+        frame = int(line[5:5+8], 16)
+        site_baseaddr[site] = "0x%08x" % (frame & ~0x7f)
+
+# print(json.dumps(database, sort_keys=True, indent="\t"))
+# print(json.dumps(tiles, sort_keys=True, indent="\t"))
+print(json.dumps(site_baseaddr, sort_keys=True, indent="\t"))
+

fuzzers/005-tilegrid/generate.sh

@@ -0,0 +1,22 @@
+#!/bin/bash
+
+set -ex
+source ../../settings.sh
+
+test $# = 1
+test ! -e $1
+mkdir $1
+cd $1
+
+vivado -mode batch -source ../generate.tcl
+
+for x in design*.bit; do
+	../../../tools/bitread -F $XRAY_ROI_FRAMES -o ${x}s -zy < $x
+done
+
+for x in design_*.bits; do
+	diff -u design.bits $x | grep '^[-+]bit' > ${x%.bits}.delta
+done
+
+python3 ../generate.py design_*.delta
+

fuzzers/005-tilegrid/generate.tcl

@@ -0,0 +1,84 @@
+create_project -force -part $::env(XRAY_PART) design design
+
+read_verilog ../top.v
+synth_design -top top
+
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
+
+create_pblock roi
+add_cells_to_pblock [get_pblocks roi] [get_cells roi]
+resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+
+set luts [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ LUT*} */A6LUT]
+set selected_luts {}
+set lut_index 0
+
+set grid_min_x -1
+set grid_max_x -1
+set grid_min_y -1
+set grid_max_y -1
+
+foreach lut $luts {
+	set tile [get_tile -of_objects $lut]
+	set grid_x [get_property GRID_POINT_X $tile]
+	set grid_y [get_property GRID_POINT_Y $tile]
+
+	if [expr $grid_min_x < 0 || $grid_x < $grid_min_x] {set grid_min_x $grid_x}
+	if [expr $grid_max_x < 0 || $grid_x > $grid_max_x] {set grid_max_x $grid_x}
+
+	if [expr $grid_min_y < 0 || $grid_y < $grid_min_y] {set grid_min_y $grid_y}
+	if [expr $grid_max_y < 0 || $grid_y > $grid_max_y] {set grid_max_y $grid_y}
+
+	if [regexp "Y(0|[0-9]*[05]0)/" $lut] {
+		set cell [get_cells roi/is[$lut_index].lut]
+		set_property LOC [get_sites -of_objects $lut] $cell
+		set lut_index [expr $lut_index + 1]
+		lappend selected_luts $lut
+	}
+}
+
+place_design
+route_design
+
+write_checkpoint -force design.dcp
+write_bitstream -force design.bit
+
+set tiles [get_tiles -filter "GRID_POINT_X >= $grid_min_x && GRID_POINT_X <= $grid_max_x && GRID_POINT_Y >= $grid_min_y && GRID_POINT_Y <= $grid_max_y"]
+
+set fp [open "tiles.txt" w]
+foreach tile $tiles {
+	set type [get_property TYPE $tile]
+	set grid_x [get_property GRID_POINT_X $tile]
+	set grid_y [get_property GRID_POINT_Y $tile]
+	set sites [get_sites -quiet -of_objects $tile]
+	set typed_sites {}
+
+	if [llength $sites] {
+		set site_types [get_property SITE_TYPE $sites]
+		foreach t $site_types s $sites {
+			lappend typed_sites $t $s
+		}
+	}
+
+	puts $fp "$type $tile $grid_x $grid_y $typed_sites"
+}
+close $fp
+
+for {set i 0} {$i < $lut_index} {incr i} {
+	set cell [get_cells roi/is[$i].lut]
+	set orig_init [get_property INIT $cell]
+	set new_init [regsub "h8" $orig_init "h0"]
+	set_property INIT $new_init $cell
+	write_bitstream -force design_[get_sites -of_objects [lindex $selected_luts $i]].bit
+	set_property INIT $orig_init $cell
+}
+

fuzzers/005-tilegrid/top.v

@@ -0,0 +1,48 @@
+`define N 100
+
+module top(input clk, stb, di, output do);
+	localparam integer DIN_N = 6;
+	localparam integer DOUT_N = `N;
+
+	reg [DIN_N-1:0] din;
+	wire [DOUT_N-1:0] dout;
+
+	reg [DIN_N-1:0] din_shr;
+	reg [DOUT_N-1:0] dout_shr;
+
+	always @(posedge clk) begin
+		din_shr <= {din_shr, di};
+		dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+		if (stb) begin
+			din <= din_shr;
+			dout_shr <= dout;
+		end
+	end
+
+	assign do = dout_shr[DOUT_N-1];
+
+	roi roi (
+		.clk(clk),
+		.din(din),
+		.dout(dout)
+	);
+endmodule
+
+module roi(input clk, input [5:0] din, output [`N-1:0] dout);
+	genvar i;
+	generate
+		for (i = 0; i < `N; i = i+1) begin:is
+			LUT6 #(
+				.INIT(64'h8000_0000_0000_0001 + (i << 16))
+			) lut (
+				.I0(din[0]),
+				.I1(din[1]),
+				.I2(din[2]),
+				.I3(din[3]),
+				.I4(din[4]),
+				.I5(din[5]),
+				.O(dout[i])
+			);
+		end
+	endgenerate
+endmodule