mirror of https://github.com/openXC7/prjxray.git
Add fuzzers/005-tilegrid/
Signed-off-by: Clifford Wolf <clifford@clifford.at> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
Clifford Wolf
parent
7789083b1e
commit
6a2965caa2
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@ -1,3 +1,4 @@
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export XRAY_DATABASE="artix7"
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export XRAY_PART="xc7a50tfgg484-1"
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export XRAY_ROI="SLICE_X12Y100:SLICE_X27Y149"
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export XRAY_ROI_FRAMES="0x00020500:0x000208ff"
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@ -0,0 +1,2 @@
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/specimen_[0-9][0-9][0-9]/
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/database.txt
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N := 1
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database.txt: $(SPECIMENS_OK)
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: ../../tools/segmatch -o database.txt \
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$(addsuffix /segdata_0.txt,$(SPECIMENS)) \
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$(addsuffix /segdata_1.txt,$(SPECIMENS)) \
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$(addsuffix /segdata_2.txt,$(SPECIMENS))
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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clean:
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rm -rf $(SPECIMENS)
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.PHONY: clean
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#!/usr/bin/env python3
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import os, sys, json, re
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database = dict()
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tiles = list()
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site_baseaddr = dict()
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with open("tiles.txt") as f:
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for line in f:
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tiles.append(line.split())
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for arg in sys.argv[1:]:
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with open(arg) as f:
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line = f.read().strip()
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site = arg[7:-6]
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frame = int(line[5:5+8], 16)
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site_baseaddr[site] = "0x%08x" % (frame & ~0x7f)
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# print(json.dumps(database, sort_keys=True, indent="\t"))
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# print(json.dumps(tiles, sort_keys=True, indent="\t"))
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print(json.dumps(site_baseaddr, sort_keys=True, indent="\t"))
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@ -0,0 +1,22 @@
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#!/bin/bash
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set -ex
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source ../../settings.sh
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test $# = 1
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test ! -e $1
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mkdir $1
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cd $1
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vivado -mode batch -source ../generate.tcl
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for x in design*.bit; do
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../../../tools/bitread -F $XRAY_ROI_FRAMES -o ${x}s -zy < $x
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done
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for x in design_*.bits; do
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diff -u design.bits $x | grep '^[-+]bit' > ${x%.bits}.delta
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done
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python3 ../generate.py design_*.delta
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@ -0,0 +1,84 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog ../top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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set luts [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ LUT*} */A6LUT]
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set selected_luts {}
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set lut_index 0
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set grid_min_x -1
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set grid_max_x -1
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set grid_min_y -1
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set grid_max_y -1
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foreach lut $luts {
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set tile [get_tile -of_objects $lut]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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if [expr $grid_min_x < 0 || $grid_x < $grid_min_x] {set grid_min_x $grid_x}
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if [expr $grid_max_x < 0 || $grid_x > $grid_max_x] {set grid_max_x $grid_x}
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if [expr $grid_min_y < 0 || $grid_y < $grid_min_y] {set grid_min_y $grid_y}
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if [expr $grid_max_y < 0 || $grid_y > $grid_max_y] {set grid_max_y $grid_y}
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if [regexp "Y(0|[0-9]*[05]0)/" $lut] {
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set cell [get_cells roi/is[$lut_index].lut]
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set_property LOC [get_sites -of_objects $lut] $cell
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set lut_index [expr $lut_index + 1]
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lappend selected_luts $lut
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}
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}
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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set tiles [get_tiles -filter "GRID_POINT_X >= $grid_min_x && GRID_POINT_X <= $grid_max_x && GRID_POINT_Y >= $grid_min_y && GRID_POINT_Y <= $grid_max_y"]
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set fp [open "tiles.txt" w]
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foreach tile $tiles {
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set type [get_property TYPE $tile]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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set sites [get_sites -quiet -of_objects $tile]
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set typed_sites {}
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if [llength $sites] {
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set site_types [get_property SITE_TYPE $sites]
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foreach t $site_types s $sites {
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lappend typed_sites $t $s
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}
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}
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puts $fp "$type $tile $grid_x $grid_y $typed_sites"
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}
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close $fp
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for {set i 0} {$i < $lut_index} {incr i} {
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set cell [get_cells roi/is[$i].lut]
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set orig_init [get_property INIT $cell]
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set new_init [regsub "h8" $orig_init "h0"]
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set_property INIT $new_init $cell
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write_bitstream -force design_[get_sites -of_objects [lindex $selected_luts $i]].bit
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set_property INIT $orig_init $cell
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}
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@ -0,0 +1,48 @@
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`define N 100
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 6;
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localparam integer DOUT_N = `N;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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module roi(input clk, input [5:0] din, output [`N-1:0] dout);
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genvar i;
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generate
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for (i = 0; i < `N; i = i+1) begin:is
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LUT6 #(
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.INIT(64'h8000_0000_0000_0001 + (i << 16))
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) lut (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(dout[i])
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);
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end
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endgenerate
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endmodule
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