luke
/
prjxray
mirror of https://github.com/openXC7/prjxray.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #1599 from antmicro/fix-gtp-prefixes 

segmaker: fix site_type prefixes for GTP sites
This commit is contained in:
litghost 2021-03-04 08:10:43 -08:00 committed by GitHub
parent dbf0237b9a 7932de32d1
commit 67fc48ddef
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
fuzzers/031-cmt-mmcm/write_mmcm_reg.py
View File

@ -171,7 +171,7 @@ def passthrough_non_register_segbits(seg_in):
Other features generated in fuzzing are passed through.
"""
base_offset_register = 'CMT_LOWER_B.MMCME2.CLKOUT5_DIVIDE[1]'
base_offset_register = 'CMT_LOWER_B.MMCME2_ADV.CLKOUT5_DIVIDE[1]'
bit_offset = None
in_use = None
@ -266,7 +266,7 @@ def output_registers(bit_offset, in_use):
continue
print(
'CMT_LOWER_B.MMCME2.{}_{}_{}[{}] {}'.format(
'CMT_LOWER_B.MMCME2_ADV.{}_{}_{}[{}] {}'.format(
register_name, layout, field, bit,
reg.next_bit()))
else:
@ -279,7 +279,7 @@ def output_registers(bit_offset, in_use):
continue
print(
'CMT_LOWER_B.MMCME2.{}[{}] {}'.format(
'CMT_LOWER_B.MMCME2_ADV.{}[{}] {}'.format(
field, start_bit + bit, reg.next_bit()))
assert bit_count == 16
@ -287,11 +287,11 @@ def output_registers(bit_offset, in_use):
for bit in range(16):
if register_name != layout or layout in ['CLKOUT1', 'CLKOUT2']:
print(
'CMT_LOWER_B.MMCME2.{}_{}[{}] {}'.format(
'CMT_LOWER_B.MMCME2_ADV.{}_{}[{}] {}'.format(
register_name, layout, bit, reg.next_bit()))
else:
print(
'CMT_LOWER_B.MMCME2.{}[{}] {}'.format(
'CMT_LOWER_B.MMCME2_ADV.{}[{}] {}'.format(
register_name, bit, reg.next_bit()))
parts = in_use.split()

10
fuzzers/032-cmt-pll/write_pll_reg.py
View File

@ -151,7 +151,7 @@ def passthrough_non_register_segbits(seg_in):
Other features generated in fuzzing are passed through.
"""
base_offset_register = 'CMT_UPPER_T.PLLE2.CLKOUT5_DIVIDE[1]'
base_offset_register = 'CMT_UPPER_T.PLLE2_ADV.CLKOUT5_DIVIDE[1]'
bit_offset = None
in_use = None
@ -244,7 +244,7 @@ def output_registers(bit_offset, in_use):
continue
print(
'CMT_UPPER_T.PLLE2.{}_{}_{}[{}] {}'.format(
'CMT_UPPER_T.PLLE2_ADV.{}_{}_{}[{}] {}'.format(
register_name, layout, field, bit,
reg.next_bit()))
else:
@ -257,7 +257,7 @@ def output_registers(bit_offset, in_use):
continue
print(
'CMT_UPPER_T.PLLE2.{}[{}] {}'.format(
'CMT_UPPER_T.PLLE2_ADV.{}[{}] {}'.format(
field, start_bit + bit, reg.next_bit()))
assert bit_count == 16
@ -265,11 +265,11 @@ def output_registers(bit_offset, in_use):
for bit in range(16):
if register_name != layout or layout in ['CLKOUT1', 'CLKOUT2']:
print(
'CMT_UPPER_T.PLLE2.{}_{}[{}] {}'.format(
'CMT_UPPER_T.PLLE2_ADV.{}_{}[{}] {}'.format(
register_name, layout, bit, reg.next_bit()))
else:
print(
'CMT_UPPER_T.PLLE2.{}[{}] {}'.format(
'CMT_UPPER_T.PLLE2_ADV.{}[{}] {}'.format(
register_name, bit, reg.next_bit()))
parts = in_use.split()

2
fuzzers/063-gtp-common-conf/generate.py
View File

@ -134,7 +134,7 @@ def main():
for i in range(2):
segmk.add_tile_tag(
tile, "IBUFDS_GTE2.%s[%u]" % (param, i), bitstr[i])
tile, "IBUFDS_GTE2.CLKSWING_CFG[%u]" % (i), bitstr[i])
if tile_type.startswith("GTP_COMMON_MID"):
bitfilter = bitfilter_gtp_common_mid

4
prjxray/segmaker.py
View File

@ -283,7 +283,7 @@ class Segmaker:
segment["tags"][tag] = value
def add_site_tags():
site_prefix = site.split('_')[0]
site_prefix = "_".join(site.split('_')[0:-1])
def name_slice():
'''
@ -331,7 +331,7 @@ class Segmaker:
'IDELAY': name_y0y1,
'ILOGIC': name_y0y1,
'OLOGIC': name_y0y1,
'IBUFDS': name_y0y1,
'IBUFDS_GTE2': name_y0y1,
}.get(site_prefix, name_default)()
self.verbose and print(
'site %s w/ %s prefix => tag %s' %