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Merge pull request #195 from mcmasterg/bram_config 

Bram INV config
This commit is contained in:
John McMaster 2018-10-25 10:17:41 -07:00 committed by GitHub
parent 308fcb5749 39ddfd8e6b
commit 6444399c20
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
16 changed files with 559 additions and 160 deletions
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2
fuzzers/005-tilegrid/generate.py
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@ -486,7 +486,7 @@ def db_add_bits(database, segments):
("CLBLM", "CLB_IO_CLK"): (36, 2, 2),
("HCLK", "CLB_IO_CLK"): (26, 1, 1),
("INT", "CLB_IO_CLK"): (28, 2, 2),
("BRAM", "CLB_IO_CLK"): (28, 2, None),
("BRAM", "CLB_IO_CLK"): (28, 10, None),
("BRAM", "BLOCK_RAM"): (128, 10, None),
("DSP", "CLB_IO_CLK"): (28, 2, 10),
("INT_INTERFACE", "CLB_IO_CLK"): (28, 2, None),

2
fuzzers/101-bram-config/.gitignore vendored Normal file
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@ -0,0 +1,2 @@
/specimen_[0-9][0-9][0-9]/
/seg_clbl[lm].segbits

23
fuzzers/101-bram-config/Makefile Normal file
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@ -0,0 +1,23 @@
N := 1
SPECIMENS := $(addprefix build/specimen_,$(shell seq -f '%03.0f' $(N)))
SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
database: $(SPECIMENS_OK)
${XRAY_SEGMATCH} -o build/seg_bramx.block_ram.segbits $(addsuffix /segdata_bram_[lr].txt,$(SPECIMENS))
pushdb:
${XRAY_MERGEDB} bram_l.block_ram build/seg_bramx.block_ram.segbits
${XRAY_MERGEDB} bram_r.block_ram build/seg_bramx.block_ram.segbits
build:
mkdir build
$(SPECIMENS_OK): build
bash generate.sh $(subst /OK,,$@)
touch $@
clean:
rm -rf build
.PHONY: database pushdb clean

2
fuzzers/101-bram-config/README.md Normal file
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@ -0,0 +1,2 @@
Solves for BRAM configuration bits (18K vs 36K, etc)

35
fuzzers/101-bram-config/generate.py Normal file
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@ -0,0 +1,35 @@
#!/usr/bin/env python3
import json
from prjxray.segmaker import Segmaker
from prjxray import verilog
segmk = Segmaker("design.bits", verbose=True)
print("Loading tags")
f = open('params.jl', 'r')
f.readline()
for l in f:
j = json.loads(l)
ps = j['params']
assert j['module'] == 'my_RAMB18E1'
site = verilog.unquote(ps['LOC'])
#print('site', site)
# all of these bits are inverted
ks = [
('IS_CLKARDCLK_INVERTED', 'ZINV_CLKARDCLK'),
('IS_CLKBWRCLK_INVERTED', 'ZINV_CLKBWRCLK'),
('IS_ENARDEN_INVERTED', 'ZINV_ENARDEN'),
('IS_ENBWREN_INVERTED', 'ZINV_ENBWREN'),
('IS_RSTRAMARSTRAM_INVERTED', 'ZINV_RSTRAMARSTRAM'),
('IS_RSTRAMB_INVERTED', 'ZINV_RSTRAMB'),
('IS_RSTREGARSTREG_INVERTED', 'ZINV_RSTREGARSTREG'),
('IS_RSTREGB_INVERTED', 'ZINV_RSTREGB'),
]
for param, tagname in ks:
segmk.add_site_tag(site, tagname, 1 ^ verilog.parsei(ps[param]))
segmk.compile()
segmk.write()

18
fuzzers/101-bram-config/generate.sh Normal file
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@ -0,0 +1,18 @@
#!/bin/bash
set -ex
FUZDIR=$PWD
source ${XRAY_GENHEADER}
python3 $FUZDIR/top.py >top.v
vivado -mode batch -source $FUZDIR/generate.tcl
test -z "$(fgrep CRITICAL vivado.log)"
for x in design*.bit; do
${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x
done
python3 $FUZDIR/generate.py

26
fuzzers/101-bram-config/generate.tcl Normal file
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@ -0,0 +1,26 @@
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
create_pblock roi
set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
add_cells_to_pblock [get_pblocks roi] [get_cells roi]
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit

308
fuzzers/101-bram-config/top.py Normal file
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@ -0,0 +1,308 @@
import os
import random
random.seed(int(os.getenv("SEED"), 16))
from prjxray import util
from prjxray import verilog
import sys
import json
def gen_bram18():
'''
sample:
"sites": {
"RAMB18_X0Y50": "FIFO18E1",
"RAMB18_X0Y51": "RAMB18E1",
"RAMB36_X0Y25": "RAMBFIFO36E1"
},
'''
for _tile_name, site_name, _site_type in sorted(util.get_roi().gen_sites(
['RAMB18E1', 'FIFO18E1'])):
yield site_name
def gen_bram36():
for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
['RAMBFIFO36E1']):
yield site_name
def gen_brams():
'''
Correctly assign a site to either bram36 or 2x bram18
'''
# FIXME
#yield ('RAMBFIFO36E1', "RAMB36_X0Y20")
#return
#for _tile_name, site_name, _site_type in util.get_roi().gen_tiles():
#for site in gen_bram36():
# yield ('RAMBFIFO36E1', site)
for site in gen_bram18():
yield ('RAMB18E1', site)
brams = list(gen_brams())
DUTN = len(brams)
DIN_N = DUTN * 8
DOUT_N = DUTN * 8
verilog.top_harness(DIN_N, DOUT_N)
f = open('params.jl', 'w')
f.write('module,loc,params\n')
print(
'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
(DIN_N - 1, DOUT_N - 1))
def vrandbit():
if random.randint(0, 1):
return "1'b1"
else:
return "1'b0"
for loci, (site_type, site) in enumerate(brams):
def place_bram18():
ports = {
'clk': 'clk',
'din': 'din[ %d +: 8]' % (8 * loci, ),
'dout': 'dout[ %d +: 8]' % (8 * loci, ),
}
params = {
'LOC': verilog.quote(site),
'IS_CLKARDCLK_INVERTED': vrandbit(),
'IS_CLKBWRCLK_INVERTED': vrandbit(),
'IS_ENARDEN_INVERTED': vrandbit(),
'IS_ENBWREN_INVERTED': vrandbit(),
'IS_RSTRAMARSTRAM_INVERTED': vrandbit(),
'IS_RSTRAMB_INVERTED': vrandbit(),
'IS_RSTREGARSTREG_INVERTED': vrandbit(),
'IS_RSTREGB_INVERTED': vrandbit(),
'RAM_MODE': '"TDP"',
'WRITE_MODE_A': '"WRITE_FIRST"',
'WRITE_MODE_B': '"WRITE_FIRST"',
}
return ('my_RAMB18E1', ports, params)
def place_bram36():
ports = {
'clk': 'clk',
'din': 'din[ %d +: 8]' % (8 * loci, ),
'dout': 'dout[ %d +: 8]' % (8 * loci, ),
}
params = {
'LOC': verilog.quote(site),
'IS_CLKARDCLK_INVERTED': vrandbit(),
'IS_CLKBWRCLK_INVERTED': vrandbit(),
'IS_ENARDEN_INVERTED': vrandbit(),
'IS_ENBWREN_INVERTED': vrandbit(),
'IS_RSTRAMARSTRAM_INVERTED': vrandbit(),
'IS_RSTRAMB_INVERTED': vrandbit(),
'IS_RSTREGARSTREG_INVERTED': vrandbit(),
'IS_RSTREGB_INVERTED': vrandbit(),
'RAM_MODE': '"TDP"',
'WRITE_MODE_A': '"WRITE_FIRST"',
'WRITE_MODE_B': '"WRITE_FIRST"',
}
return ('my_RAMB36E1', ports, params)
modname, ports, params = {
'RAMB18E1': place_bram18,
'RAMBFIFO36E1': place_bram36,
}[site_type]()
verilog.instance(modname, 'inst_%u' % loci, ports, params=params)
j = {'module': modname, 'i': loci, 'params': params}
f.write('%s\n' % (json.dumps(j)))
print('')
'''
def randbits(n):
return ''.join([random.choice(('0', '1')) for _x in range(n)])
loci = 0
def make(module, gen_locs, pdatan, datan):
global loci
for loci, loc in enumerate(gen_locs()):
if loci >= DUTN:
break
pdata = randbits(pdatan * 0x100)
data = randbits(datan * 0x100)
print(' %s #(' % module)
for i in range(pdatan):
print(
" .INITP_%02X(256'b%s)," %
(i, pdata[i * 256:(i + 1) * 256]))
for i in range(datan):
print(
" .INIT_%02X(256'b%s)," %
(i, data[i * 256:(i + 1) * 256]))
print(' .LOC("%s"))' % (loc, ))
print(
' inst_%d (.clk(clk), .din(din[ %d +: 8]), .dout(dout[ %d +: 8]));'
% (loci, 8 * loci, 8 * loci))
f.write('%s,%s,%s,%s\n' % (module, loc, pdata, data))
print('')
loci += 1
assert loci == DUTN
#make('my_RAMB18E1', gen_bram18, 0x08, 0x40)
make('my_RAMB36E1', gen_bram36, 0x10, 0x80)
'''
f.close()
print(
'''endmodule
// ---------------------------------------------------------------------
''')
# RAMB18E1
print(
'''
module my_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
parameter RAM_MODE = "TDP";
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
''')
print('''\
(* LOC=LOC *)
RAMB18E1 #(''')
for i in range(8):
print(" .INITP_%02X(256'b0)," % (i, ))
print('')
for i in range(0x40):
print(" .INIT_%02X(256'b0)," % (i, ))
print('')
print(
'''
.IS_CLKARDCLK_INVERTED(IS_CLKARDCLK_INVERTED),
.IS_CLKBWRCLK_INVERTED(IS_CLKBWRCLK_INVERTED),
.IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED),
.IS_ENBWREN_INVERTED(IS_ENBWREN_INVERTED),
.IS_RSTRAMARSTRAM_INVERTED(IS_RSTRAMARSTRAM_INVERTED),
.IS_RSTRAMB_INVERTED(IS_RSTRAMB_INVERTED),
.IS_RSTREGARSTREG_INVERTED(IS_RSTREGARSTREG_INVERTED),
.IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED),
.RAM_MODE(RAM_MODE),
.WRITE_MODE_A(WRITE_MODE_A),
.WRITE_MODE_B(WRITE_MODE_B)
) ram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEBWE(din[1]),
.DOADO(dout[0]),
.DOBDO(dout[1]),
.DOPADOP(dout[2]),
.DOPBDOP(dout[3]));
endmodule
''')
print(
'''
module my_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
parameter RAM_MODE = "TDP";
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
''')
print('')
print('''\
(* LOC=LOC *)
RAMB36E1 #(''')
for i in range(16):
print(" .INITP_%02X(256'b0)," % (i, ))
print('')
for i in range(0x80):
print(" .INIT_%02X(256'b0)," % (i, ))
print('')
print(
'''
.IS_CLKARDCLK_INVERTED(IS_CLKARDCLK_INVERTED),
.IS_CLKBWRCLK_INVERTED(IS_CLKBWRCLK_INVERTED),
.IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED),
.IS_ENBWREN_INVERTED(IS_ENBWREN_INVERTED),
.IS_RSTRAMARSTRAM_INVERTED(IS_RSTRAMARSTRAM_INVERTED),
.IS_RSTRAMB_INVERTED(IS_RSTRAMB_INVERTED),
.IS_RSTREGARSTREG_INVERTED(IS_RSTREGARSTREG_INVERTED),
.IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED),
.RAM_MODE(RAM_MODE),
.WRITE_MODE_A(WRITE_MODE_A),
.WRITE_MODE_B(WRITE_MODE_B)
) ram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEBWE(din[1]),
.DOADO(dout[0]),
.DOBDO(dout[1]),
.DOPADOP(dout[2]),
.DOPBDOP(dout[3]));
endmodule
''')

1
fuzzers/102-bram-data/generate.py
View File

@ -2,7 +2,6 @@
import sys, re, os
sys.path.append("../../../utils/")
from prjxray.segmaker import Segmaker
c2i = {'0': 0, '1': 1}

96
fuzzers/102-bram-data/top.py
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@ -1,19 +1,4 @@
'''
Need coverage for the following:
RAM32X1S_N
RAM32X1D
RAM32M
RAM64X1S_N
RAM64X1D_N
RAM64M
RAM128X1S_N
RAM128X1D
RAM256X1S
SRL16E_N
SRLC32E_N
Note: LUT6 was added to try to simplify reduction, although it might not be needed
'''
#!/usr/bin/env python
import os
import random
@ -23,13 +8,6 @@ from prjxray import verilog
import sys
def gen_bram18():
# yield "RAMB18_X%dY%d" % (x, y)
for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
['RAMB18E1']):
yield site_name
def gen_bram36():
#yield "RAMB36_X%dY%d" % (x, y)
for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
@ -54,11 +32,8 @@ def randbits(n):
return ''.join([random.choice(('0', '1')) for _x in range(n)])
loci = 0
def make(module, gen_locs, pdatan, datan):
global loci
loci = 0
for loci, loc in enumerate(gen_locs()):
if loci >= DUTN:
@ -87,7 +62,6 @@ def make(module, gen_locs, pdatan, datan):
assert loci == DUTN
#make('my_RAMB18E1', gen_bram18, 0x08, 0x40)
make('my_RAMB36E1', gen_bram36, 0x10, 0x80)
f.close()
@ -98,74 +72,8 @@ print(
''')
# RAMB18E1
print(
'''
module my_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
''')
for i in range(8):
print(
" parameter INITP_%02X = 256'h0000000000000000000000000000000000000000000000000000000000000000;"
% i)
print('')
for i in range(0x40):
print(
" parameter INIT_%02X = 256'h0000000000000000000000000000000000000000000000000000000000000000;"
% i)
print('')
print('''\
(* LOC=LOC *)
RAMB18E1 #(''')
for i in range(8):
print(' .INITP_%02X(INITP_%02X),' % (i, i))
print('')
for i in range(0x40):
print(' .INIT_%02X(INIT_%02X),' % (i, i))
print('')
print(
'''
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.SIM_DEVICE("VIRTEX6")
) ram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEBWE(din[1]),
.DOADO(dout[0]),
.DOBDO(dout[1]),
.DOPADOP(dout[2]),
.DOPBDOP(dout[3]));
endmodule
''')
print(
'''
module my_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
''')

9
minitests/bram_basic/.gitignore vendored
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@ -1,8 +1 @@
/.Xil
/design/
/design.bit
/design.bits
/design.dcp
/usage_statistics_webtalk.*
/vivado*
/design.txt
build

18
minitests/bram_basic/Makefile
View File

@ -1,8 +1,12 @@
all: build/roi_bramd_bit01.diff build/roi_bramd_bits01.diff build/roi_bramds_bit01.diff build/roi_bramis_bit01.diff
all: build/env build/roi_bramd_bit01.diff build/roi_bramd_bits01.diff build/roi_bramds_bit01.diff build/roi_bramis_bit01.diff
clean:
rm -rf build
# hard coded LOCs in .v
build/env:
test "$(XRAY_PART)" = "xc7a50tfgg484-1"
# Toggle one bit to locate where first BRAM data is
build/roi_bramd_bit01.diff:
$(MAKE) -f diff.mk OUT_DIFF=build/roi_bramd_bit01.diff PRJL=roi_bramd_bit0 PRJR=roi_bramd_bit1
@ -18,7 +22,19 @@ build/roi_bramd_bits01.diff:
build/roi_bramds_bit01.diff:
$(MAKE) -f diff.mk OUT_DIFF=build/roi_bramds_bit01.diff PRJL=roi_bramds_bit0 PRJR=roi_bramds_bit1
# Toggle one bit in BRAM config section
build/roi_brami_bit01.diff:
$(MAKE) -f diff.mk OUT_DIFF=build/roi_brami_bit01.diff PRJL=roi_brami_bit0 PRJR=roi_brami_bit1
# Toggle one bit in each BRAM18 config section
# together they match the 2 BRAM36 bits above
build/roi_bram18iy0_bit01.diff:
$(MAKE) -f diff.mk OUT_DIFF=build/roi_bram18iy0_bit01.diff PRJL=roi_bram18i_bit0 PRJR=roi_bram18iy0_bit1
build/roi_bram18iy1_bit01.diff:
$(MAKE) -f diff.mk OUT_DIFF=build/roi_bram18iy1_bit01.diff PRJL=roi_bram18i_bit0 PRJR=roi_bram18iy1_bit1
# Toggle one bit in each BRAM config section
build/roi_bramis_bit01.diff:
$(MAKE) -f diff.mk OUT_DIFF=build/roi_bramis_bit01.diff PRJL=roi_bramis_bit0 PRJR=roi_bramis_bit1

132
minitests/bram_basic/top.v
View File

@ -1,10 +1,3 @@
/*
ROM128X1: 128-Deep by 1-Wide ROM
ROM256X1: 256-Deep by 1-Wide ROM
ROM32X1: 32-Deep by 1-Wide ROM
ROM64X1: 64-Deep by 1-Wide ROM
*/
`ifndef ROI
ERROR: must set ROI
`endif
@ -46,17 +39,17 @@ DATA ROI
Toggle a single data bit to locate a single instance
******************************************************************************/
module roi_bramd_bit0(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(1'b0), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b0), .INIT({256{1'b0}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
module roi_bramd_bit1(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(1'b1), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b1), .INIT({256{1'b0}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
module roi_bramd2_bit1(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(256'b10), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(256'b10), .INIT({256{1'b0}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
@ -75,12 +68,12 @@ Toggle all bits to show the size of the data section
******************************************************************************/
module roi_bramd_bits0(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0({256{1'b0}}), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0({256{1'b0}}), .INIT({256{1'b0}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
module roi_bramd_bits1(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0({256{1'b1}}), .INIT({256{1'b1}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0({256{1'b1}}), .INIT({256{1'b1}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
@ -89,48 +82,48 @@ Toggle all the data bits in the ROI to show pitch between entries
******************************************************************************/
module roi_bramds_bit0(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(1'b0), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b0), .INIT({256{1'b0}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y11"), .INIT0(1'b0), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y21"), .INIT0(1'b0), .INIT({256{1'b0}}))
r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y12"), .INIT0(1'b0), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y22"), .INIT0(1'b0), .INIT({256{1'b0}}))
r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y13"), .INIT0(1'b0), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y23"), .INIT0(1'b0), .INIT({256{1'b0}}))
r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y14"), .INIT0(1'b0), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y24"), .INIT0(1'b0), .INIT({256{1'b0}}))
r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y15"), .INIT0(1'b0), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y25"), .INIT0(1'b0), .INIT({256{1'b0}}))
r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y16"), .INIT0(1'b0), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y26"), .INIT0(1'b0), .INIT({256{1'b0}}))
r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y17"), .INIT0(1'b0), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y27"), .INIT0(1'b0), .INIT({256{1'b0}}))
r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y18"), .INIT0(1'b0), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y28"), .INIT0(1'b0), .INIT({256{1'b0}}))
r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y19"), .INIT0(1'b0), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y29"), .INIT0(1'b0), .INIT({256{1'b0}}))
r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
endmodule
module roi_bramds_bit1(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(1'b1), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b1), .INIT({256{1'b0}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y11"), .INIT0(1'b1), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y21"), .INIT0(1'b1), .INIT({256{1'b0}}))
r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y12"), .INIT0(1'b1), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y22"), .INIT0(1'b1), .INIT({256{1'b0}}))
r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y13"), .INIT0(1'b1), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y23"), .INIT0(1'b1), .INIT({256{1'b0}}))
r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y14"), .INIT0(1'b1), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y24"), .INIT0(1'b1), .INIT({256{1'b0}}))
r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y15"), .INIT0(1'b1), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y25"), .INIT0(1'b1), .INIT({256{1'b0}}))
r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y16"), .INIT0(1'b1), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y26"), .INIT0(1'b1), .INIT({256{1'b0}}))
r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y17"), .INIT0(1'b1), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y27"), .INIT0(1'b1), .INIT({256{1'b0}}))
r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y18"), .INIT0(1'b1), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y28"), .INIT0(1'b1), .INIT({256{1'b0}}))
r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y19"), .INIT0(1'b1), .INIT({256{1'b0}}))
ram_RAMB36E1 #(.LOC("RAMB36_X0Y29"), .INIT0(1'b1), .INIT({256{1'b0}}))
r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
endmodule
@ -138,49 +131,81 @@ endmodule
CONFIG ROI
******************************************************************************/
module roi_bramis_bit0(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
module roi_bram18i_bit0(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y11"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
ram_RAMB18E1 #(.LOC("RAMB18_X0Y41"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y12"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
endmodule
module roi_bram18iy0_bit1(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y41"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
endmodule
module roi_bram18iy1_bit1(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y41"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
endmodule
module roi_brami_bit0(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
module roi_brami_bit1(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
module roi_bramis_bit0(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y42"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y44"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y13"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
ram_RAMB18E1 #(.LOC("RAMB18_X0Y46"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y14"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
ram_RAMB18E1 #(.LOC("RAMB18_X0Y48"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y15"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
ram_RAMB18E1 #(.LOC("RAMB18_X0Y50"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y16"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
ram_RAMB18E1 #(.LOC("RAMB18_X0Y52"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y17"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
ram_RAMB18E1 #(.LOC("RAMB18_X0Y54"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y18"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
ram_RAMB18E1 #(.LOC("RAMB18_X0Y56"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y19"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
ram_RAMB18E1 #(.LOC("RAMB18_X0Y58"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
endmodule
module roi_bramis_bit1(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y11"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
ram_RAMB18E1 #(.LOC("RAMB18_X0Y42"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y12"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
ram_RAMB18E1 #(.LOC("RAMB18_X0Y44"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y13"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
ram_RAMB18E1 #(.LOC("RAMB18_X0Y46"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y14"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
ram_RAMB18E1 #(.LOC("RAMB18_X0Y48"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y15"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
ram_RAMB18E1 #(.LOC("RAMB18_X0Y50"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y16"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
ram_RAMB18E1 #(.LOC("RAMB18_X0Y52"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y17"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
ram_RAMB18E1 #(.LOC("RAMB18_X0Y54"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y18"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
ram_RAMB18E1 #(.LOC("RAMB18_X0Y56"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y19"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
ram_RAMB18E1 #(.LOC("RAMB18_X0Y58"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
endmodule
@ -380,6 +405,7 @@ module ram_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout);
parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter IS_ENARDEN_INVERTED = 1'b0;
(* LOC=LOC *)
RAMB36E1 #(
.INITP_00(INIT),
.INITP_01(INIT),

26
prjxray/segmaker.py
View File

@ -122,6 +122,8 @@ class Segmaker:
self.addtag('SLICE_X13Y101', 'CLB.SLICE_X0.AFF.DMUX.CY', 1)
Indicates that the SLICE_X13Y101 site has an element called 'CLB.SLICE_X0.AFF.DMUX.CY'
'''
if '"' in site:
raise ValueError("Invalid site: %s" % site)
self.site_tags.setdefault(site, dict())[name] = value
def add_tile_tag(self, tile, name, value):
@ -130,6 +132,7 @@ class Segmaker:
def compile(self, bitfilter=None):
print("Compiling segment data.")
tags_used = set()
sites_used = set()
tile_types_found = set()
self.segments_by_type = dict()
@ -225,6 +228,15 @@ class Segmaker:
else:
assert 0
def name_bram18():
# RAMB18_X0Y41
if re.match(r"^RAMB18_X.*Y[0-9]*[02468]$", site):
return "RAMB18_Y0"
elif re.match(r"^RAMB18_X.*Y[0-9]*[13579]$", site):
return "RAMB18_Y1"
else:
assert 0
def name_default():
# most sites are unique within their tile
# TODO: maybe verify against DB?
@ -232,7 +244,11 @@ class Segmaker:
sitekey = {
'SLICE': name_slice,
'RAMB18': name_bram18,
}.get(site_prefix, name_default)()
self.verbose and print(
'site %s w/ %s prefix => tag %s' %
(site, site_prefix, sitekey))
for name, value in self.site_tags[site].items():
tags_used.add((site, name))
@ -241,6 +257,7 @@ class Segmaker:
tag = tag.replace(".SLICEM.", ".")
tag = tag.replace(".SLICEL.", ".")
segments[segname]["tags"][tag] = value
sites_used.add(site)
tile_type = tiledata["type"]
tile_types_found.add(tile_type)
@ -279,8 +296,15 @@ class Segmaker:
add_site_tags()
if self.verbose:
ntags = recurse_sum(self.site_tags) + recurse_sum(self.tile_tags)
n_site_tags = recurse_sum(self.site_tags)
n_tile_tags = recurse_sum(self.tile_tags)
ntags = n_site_tags + n_tile_tags
print("Used %u / %u tags" % (len(tags_used), ntags))
print("Tag sites: %u" % (n_site_tags, ))
if n_site_tags:
print(' Ex: %s' % list(self.site_tags.keys())[0])
print("Tag tiles: %u" % (n_tile_tags, ))
print("Used %u sites" % len(sites_used))
print("Grid DB had %u tile types" % len(tile_types_found))
assert ntags and ntags == len(tags_used)

20
prjxray/verilog.py
View File

@ -48,4 +48,22 @@ def instance(mod, name, ports, params={}, sort=True):
for i, (portk, portv) in enumerate(tosort(ports.items())):
comma = '' if i == len(ports) - 1 else ','
print(' .%s(%s)%s' % (portk, portv, comma))
print(' ));')
print(' );')
def quote(s):
return '"' + s + '"'
def unquote(s):
assert s[0] == '"' and s[-1] == '"'
return s[1:-1]
def parsei(s):
if s == "1'b0":
return 0
elif s == "1'b1":
return 1
else:
assert 0, 'FIXME'

1
utils/genheader.sh
View File

@ -12,6 +12,7 @@ test $# = 1 || exit 1
test ! -e "$SPECN"
SPECN=$1
rm -rf "$SPECN"
mkdir "$SPECN"
cd "$SPECN"