Add fuzzers/051-imuxlout

Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>

fuzzers/051-imuxlout/.gitignore

@@ -0,0 +1,13 @@
+/filtered_seg_int_l.segbits
+/filtered_seg_int_r.segbits
+/pattern_l.txt
+/pattern_r.txt
+/piplist.dcp
+/piplist/
+/pips_int_l.txt
+/pips_int_r.txt
+/seg_int_l.segbits
+/seg_int_r.segbits
+/specimen_[0-9][0-9][0-9]/
+/todo.txt
+/vivado*

fuzzers/051-imuxlout/Makefile

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+
+N := 10
+SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
+SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
+
+database: $(SPECIMENS_OK)
+	grep '^INT_L\.' todo.txt | sed 's/INT_L\./^INT./; s/$$/ ./;' > pattern_l.txt
+	grep '^INT_R\.' todo.txt | sed 's/INT_R\./^INT./; s/$$/ ./;' > pattern_r.txt
+	${XRAY_SEGMATCH} -m 5 -M 15 -o seg_int_l.segbits $(addsuffix /segdata_clbl[lm]_l_[0-9][0-9][0-9].txt,$(SPECIMENS))
+	${XRAY_SEGMATCH} -m 5 -M 15 -o seg_int_r.segbits $(addsuffix /segdata_clbl[lm]_r_[0-9][0-9][0-9].txt,$(SPECIMENS))
+	grep -f pattern_l.txt seg_int_l.segbits > filtered_seg_int_l.segbits
+	grep -f pattern_l.txt seg_int_r.segbits > filtered_seg_int_r.segbits
+
+pushdb:
+	${XRAY_MERGEDB} int_l filtered_seg_int_l.segbits
+	${XRAY_MERGEDB} int_r filtered_seg_int_r.segbits
+	${XRAY_DBFIXUP}
+
+$(SPECIMENS_OK): todo.txt
+	bash generate.sh $(subst /OK,,$@)
+	touch $@
+
+todo.txt:
+	vivado -mode batch -source piplist.tcl
+	python3 maketodo.py > todo.txt
+
+clean:
+	rm -rf .Xil/ .cache/ filtered_seg_int_[lr].segbits
+	rm -rf todo.txt vivado* piplist/ piplist.dcp pattern_[lr].txt pips_int_[lr].txt
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_int_[lr].segbits mask_clbl[lm]_[lr].segbits
+
+.PHONY: database pushdb clean
+

fuzzers/051-imuxlout/generate.sh

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+#!/bin/bash
+
+source ${XRAY_GENHEADER}
+
+vivado -mode batch -source ../generate.tcl
+
+${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
+python3 ../../050-intpips/generate.py
+

fuzzers/051-imuxlout/generate.tcl

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+create_project -force -part $::env(XRAY_PART) design design
+
+read_verilog ../top.v
+synth_design -top top
+
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
+
+create_pblock roi
+resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+place_design
+route_design
+
+# write_checkpoint -force design.dcp
+
+source ../../../utils/utils.tcl
+
+set fp [open "../todo.txt" r]
+set todo_lines {}
+for {gets $fp line} {$line != ""} {gets $fp line} {
+	lappend todo_lines [split $line .]
+}
+close $fp
+
+set int_l_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_L}]]
+set int_r_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_R}]]
+
+set idx 0
+for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
+	set line [lindex $todo_lines $idx]
+
+	set tile_type [lindex $line 0]
+	set dst_wire [lindex $line 1]
+	set src_wire [lindex $line 2]
+
+	if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]}
+	if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]}
+
+	set clb_dst_wire [get_wires -filter {TILE_NAME =~ CLB*} -of_objects [get_nodes -of_objects [get_wire $tile/$dst_wire]]]
+	set clb_src_wire [get_wires -filter {TILE_NAME =~ CLB*} -of_objects [get_nodes -of_objects [get_wire $tile/$src_wire]]]
+
+	set clb_dst_pin [get_site_pins -of_objects [get_nodes -downhill -of_objects [get_pips -of_objects $clb_dst_wire]]]
+	set clb_src_pin [get_site_pins -of_objects [get_nodes -uphill -of_objects [get_pips -of_objects $clb_src_wire]]]
+
+	set src_prefix [regsub {(.*/.).*} ${clb_src_pin} {\1}]
+	set dst_prefix [regsub {(.*/.).*} ${clb_dst_pin} {\1}]
+
+	if {$src_prefix == $dst_prefix} {
+		set slice [get_sites -of_objects $clb_dst_pin]
+		set lut [regsub {.*/} $src_prefix {}]6LUT
+
+		puts "=== $slice $lut ($clb_src_pin -> $clb_dst_pin)"
+
+		set mynet [create_net mynet_$idx]
+		set mylut [create_cell -reference LUT1 mylut_$idx]
+		set lutin [regsub {.*(.)} $clb_dst_pin {A\1}]
+		set_property -dict "LOC $slice BEL $lut LOCK_PINS I0:$lutin" $mylut
+		connect_net -net $mynet -objects "$mylut/I0 $mylut/O"
+	}
+}
+
+proc write_txtdata {filename} {
+	puts "Writing $filename."
+	set fp [open $filename w]
+	set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
+	if {$all_pips != {}} {
+		puts "Dumping pips."
+		foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
+			foreach pip [filter $all_pips "TILE == $tile"] {
+				set src_wire [get_wires -uphill -of_objects $pip]
+				set dst_wire [get_wires -downhill -of_objects $pip]
+				set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
+				set dir_prop [get_property IS_DIRECTIONAL $pip]
+				puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
+			}
+		}
+	}
+	close $fp
+}
+
+route_design
+write_checkpoint -force design.dcp
+write_bitstream -force design.bit
+write_txtdata design.txt
+

fuzzers/051-imuxlout/maketodo.py

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+#!/usr/bin/env python3
+
+import os, re
+
+def maketodo(pipfile, dbfile):
+    todos = set()
+    with open(pipfile, "r") as f:
+        for line in f:
+            line = line.split()
+            todos.add(line[0])
+    with open(dbfile, "r") as f:
+        for line in f:
+            line = line.split()
+            todos.remove(line[0])
+    for line in todos:
+        if re.match(r"^INT_[LR].IMUX(_L)?[0-9]+\.LOGIC_OUTS(_L)?[0-9]+$", line):
+            print(line)
+
+maketodo("pips_int_l.txt", "%s/%s/segbits_int_l.db" % (os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE")))
+maketodo("pips_int_r.txt", "%s/%s/segbits_int_r.db" % (os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE")))
+

fuzzers/051-imuxlout/piplist.tcl

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+create_project -force -part $::env(XRAY_PART) piplist piplist
+
+read_verilog top.v
+synth_design -top top
+
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
+
+create_pblock roi
+resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+place_design
+route_design
+
+write_checkpoint -force piplist.dcp
+
+source ../../utils/utils.tcl
+
+proc print_tile_pips {tile_type filename} {
+	set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
+	puts "Dumping and PIPs for tile $tile ($tile_type) to $filename."
+	set fp [open $filename w]
+	foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
+		set src [get_wires -uphill -of_objects $pip]
+		set dst [get_wires -downhill -of_objects $pip]
+		if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
+			puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
+		}
+	}
+	close $fp
+}
+
+print_tile_pips INT_L pips_int_l.txt
+print_tile_pips INT_R pips_int_r.txt
+

fuzzers/051-imuxlout/top.v

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+module top (input i, output o);
+	assign o = i;
+endmodule