mirror of https://github.com/openXC7/prjxray.git
Add fuzzers/051-imuxlout
Signed-off-by: Clifford Wolf <clifford@clifford.at> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
Clifford Wolf
Tim 'mithro' Ansell
parent
62dd2f94a5
commit
63cab282ca
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/filtered_seg_int_l.segbits
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/filtered_seg_int_r.segbits
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/pattern_l.txt
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/pattern_r.txt
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/piplist.dcp
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/piplist/
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/pips_int_l.txt
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/pips_int_r.txt
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/seg_int_l.segbits
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/seg_int_r.segbits
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/specimen_[0-9][0-9][0-9]/
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/todo.txt
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/vivado*
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@ -0,0 +1,33 @@
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N := 10
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: $(SPECIMENS_OK)
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grep '^INT_L\.' todo.txt | sed 's/INT_L\./^INT./; s/$$/ ./;' > pattern_l.txt
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grep '^INT_R\.' todo.txt | sed 's/INT_R\./^INT./; s/$$/ ./;' > pattern_r.txt
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${XRAY_SEGMATCH} -m 5 -M 15 -o seg_int_l.segbits $(addsuffix /segdata_clbl[lm]_l_[0-9][0-9][0-9].txt,$(SPECIMENS))
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${XRAY_SEGMATCH} -m 5 -M 15 -o seg_int_r.segbits $(addsuffix /segdata_clbl[lm]_r_[0-9][0-9][0-9].txt,$(SPECIMENS))
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grep -f pattern_l.txt seg_int_l.segbits > filtered_seg_int_l.segbits
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grep -f pattern_l.txt seg_int_r.segbits > filtered_seg_int_r.segbits
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pushdb:
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${XRAY_MERGEDB} int_l filtered_seg_int_l.segbits
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${XRAY_MERGEDB} int_r filtered_seg_int_r.segbits
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${XRAY_DBFIXUP}
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$(SPECIMENS_OK): todo.txt
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bash generate.sh $(subst /OK,,$@)
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touch $@
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todo.txt:
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vivado -mode batch -source piplist.tcl
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python3 maketodo.py > todo.txt
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clean:
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rm -rf .Xil/ .cache/ filtered_seg_int_[lr].segbits
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rm -rf todo.txt vivado* piplist/ piplist.dcp pattern_[lr].txt pips_int_[lr].txt
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rm -rf specimen_[0-9][0-9][0-9]/ seg_int_[lr].segbits mask_clbl[lm]_[lr].segbits
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.PHONY: database pushdb clean
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#!/bin/bash
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source ${XRAY_GENHEADER}
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vivado -mode batch -source ../generate.tcl
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
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python3 ../../050-intpips/generate.py
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@ -0,0 +1,90 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog ../top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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# write_checkpoint -force design.dcp
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source ../../../utils/utils.tcl
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set fp [open "../todo.txt" r]
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set todo_lines {}
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for {gets $fp line} {$line != ""} {gets $fp line} {
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lappend todo_lines [split $line .]
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}
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close $fp
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set int_l_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_L}]]
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set int_r_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_R}]]
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set idx 0
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for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
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set line [lindex $todo_lines $idx]
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set tile_type [lindex $line 0]
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set dst_wire [lindex $line 1]
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set src_wire [lindex $line 2]
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if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]}
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if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]}
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set clb_dst_wire [get_wires -filter {TILE_NAME =~ CLB*} -of_objects [get_nodes -of_objects [get_wire $tile/$dst_wire]]]
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set clb_src_wire [get_wires -filter {TILE_NAME =~ CLB*} -of_objects [get_nodes -of_objects [get_wire $tile/$src_wire]]]
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set clb_dst_pin [get_site_pins -of_objects [get_nodes -downhill -of_objects [get_pips -of_objects $clb_dst_wire]]]
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set clb_src_pin [get_site_pins -of_objects [get_nodes -uphill -of_objects [get_pips -of_objects $clb_src_wire]]]
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set src_prefix [regsub {(.*/.).*} ${clb_src_pin} {\1}]
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set dst_prefix [regsub {(.*/.).*} ${clb_dst_pin} {\1}]
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if {$src_prefix == $dst_prefix} {
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set slice [get_sites -of_objects $clb_dst_pin]
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set lut [regsub {.*/} $src_prefix {}]6LUT
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puts "=== $slice $lut ($clb_src_pin -> $clb_dst_pin)"
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set mynet [create_net mynet_$idx]
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set mylut [create_cell -reference LUT1 mylut_$idx]
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set lutin [regsub {.*(.)} $clb_dst_pin {A\1}]
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set_property -dict "LOC $slice BEL $lut LOCK_PINS I0:$lutin" $mylut
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connect_net -net $mynet -objects "$mylut/I0 $mylut/O"
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}
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}
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proc write_txtdata {filename} {
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puts "Writing $filename."
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set fp [open $filename w]
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set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
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if {$all_pips != {}} {
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puts "Dumping pips."
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foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
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foreach pip [filter $all_pips "TILE == $tile"] {
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set src_wire [get_wires -uphill -of_objects $pip]
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set dst_wire [get_wires -downhill -of_objects $pip]
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set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
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set dir_prop [get_property IS_DIRECTIONAL $pip]
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puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
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}
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}
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}
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close $fp
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}
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_txtdata design.txt
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@ -0,0 +1,21 @@
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#!/usr/bin/env python3
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import os, re
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def maketodo(pipfile, dbfile):
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todos = set()
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with open(pipfile, "r") as f:
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for line in f:
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line = line.split()
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todos.add(line[0])
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with open(dbfile, "r") as f:
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for line in f:
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line = line.split()
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todos.remove(line[0])
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for line in todos:
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if re.match(r"^INT_[LR].IMUX(_L)?[0-9]+\.LOGIC_OUTS(_L)?[0-9]+$", line):
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print(line)
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maketodo("pips_int_l.txt", "%s/%s/segbits_int_l.db" % (os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE")))
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maketodo("pips_int_r.txt", "%s/%s/segbits_int_r.db" % (os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE")))
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@ -0,0 +1,39 @@
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create_project -force -part $::env(XRAY_PART) piplist piplist
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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write_checkpoint -force piplist.dcp
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source ../../utils/utils.tcl
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proc print_tile_pips {tile_type filename} {
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set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
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puts "Dumping and PIPs for tile $tile ($tile_type) to $filename."
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set fp [open $filename w]
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foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
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set src [get_wires -uphill -of_objects $pip]
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set dst [get_wires -downhill -of_objects $pip]
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if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
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puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
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}
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}
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close $fp
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}
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print_tile_pips INT_L pips_int_l.txt
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print_tile_pips INT_R pips_int_r.txt
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@ -0,0 +1,3 @@
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module top (input i, output o);
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assign o = i;
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endmodule
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