mirror of https://github.com/openXC7/prjxray.git
Merge pull request #606 from antmicro/roi-harness-fix
roi_harness: added zybo support
This commit is contained in:
litghost
GitHub
commit
62fb5290d1
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@ -1,6 +1,8 @@
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# XC7A35TICSG324-1L
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export XRAY_PART=xc7a35tcsg324-1
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export XRAY_PINCFG=ARTY-A7-SWBUT
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export XRAY_DIN_N_LARGE=8
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export XRAY_DOUT_N_LARGE=8
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# For generating DB
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export XRAY_PIN_00="G13"
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@ -11,4 +13,23 @@ export XRAY_PIN_04="D13"
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export XRAY_PIN_05="J17"
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export XRAY_PIN_06="U14"
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# HCLK Tile
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export XRAY_ROI_HCLK="CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0"
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# PITCH
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export XRAY_PITCH=2
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# INT_L/R for DOUT and DIN
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export XRAY_ROI_DIN_INT_L_X="0"
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export XRAY_ROI_DIN_INT_R_X="25"
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export XRAY_ROI_DOUT_INT_L_X="2"
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export XRAY_ROI_DOUT_INT_R_X="23"
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# PIPS for DOUT and DIN
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export XRAY_ROI_DIN_LPIP="EE2BEG2"
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export XRAY_ROI_DIN_RPIP="WW2BEG1"
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export XRAY_ROI_DOUT_LPIP="SW6BEG0"
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export XRAY_ROI_DOUT_RPIP="LH12"
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source $XRAY_DIR/utils/environment.sh
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@ -1,6 +1,8 @@
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# XC7A35T-1CPG236C
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export XRAY_PART=xc7a35tcpg236-1
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export XRAY_PINCFG=BASYS3-SWBUT
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export XRAY_DIN_N_LARGE=17
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export XRAY_DOUT_N_LARGE=17
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# For generating DB
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export XRAY_PIN_00="V17"
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@ -11,4 +13,25 @@ export XRAY_PIN_04="W15"
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export XRAY_PIN_05="V15"
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export XRAY_PIN_06="W14"
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# ROI is in the top left
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export XRAY_ROI_LARGE=SLICE_X0Y100:SLICE_X35Y149
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# HCLK Tile
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export XRAY_ROI_HCLK="CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0"
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# PITCH
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export XRAY_PITCH=2
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# INT_L/R for DOUT and DIN
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export XRAY_ROI_DIN_INT_L_X="0"
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export XRAY_ROI_DIN_INT_R_X="25"
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export XRAY_ROI_DOUT_INT_L_X="2"
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export XRAY_ROI_DOUT_INT_R_X="23"
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# PIPS for DOUT and DIN
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export XRAY_ROI_DIN_LPIP="EE2BEG2"
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export XRAY_ROI_DIN_RPIP="WW2BEG1"
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export XRAY_ROI_DOUT_LPIP="SW6BEG0"
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export XRAY_ROI_DOUT_RPIP="LH12"
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source $XRAY_DIR/utils/environment.sh
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@ -26,19 +26,23 @@ stat ${XRAY_DIR}/database/${XRAY_DATABASE}/${XRAY_PART}.yaml >/dev/null
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# 6x by 18y CLBs (108)
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if [ "$SMALL" = Y ] ; then
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echo "Design: small"
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export PITCH=1
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export PITCH=${XRAY_PITCH:-1}
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export DIN_N=${XRAY_DIN_N_SMALL:-8}
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export DOUT_N=${XRAY_DOUT_N_SMALL:-8}
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export XRAY_ROI=${XRAY_ROI_SMALL:-SLICE_X12Y100:SLICE_X17Y117}
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# All of CMT X0Y2
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else
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echo "Design: large"
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export PITCH=2
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export PITCH=${XRAY_PITCH:-2}
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export DIN_N=${XRAY_DIN_N_LARGE:-8}
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export DOUT_N=${XRAY_DOUT_N_LARGE:-8}
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export XRAY_ROI=${XRAY_ROI_LARGE:-SLICE_X0Y100:SLICE_X35Y149}
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fi
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echo ${DIN_N}
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echo ${DOUT_N}
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echo ${XRAY_ROI}
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mkdir -p $BUILD_DIR
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pushd $BUILD_DIR
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@ -18,6 +18,46 @@ if { [info exists ::env(PITCH) ] } {
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set PITCH "$::env(PITCH)"
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}
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if { [info exists ::env(XRAY_ROI_HCLK)] } {
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set XRAY_ROI_HCLK "$::env(XRAY_ROI_HCLK)"
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} else {
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puts "WARNING: No HCLK has been set"
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}
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# Setting all the PIPs for DIN and DOUT
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if { [info exists ::env(XRAY_ROI_DIN_LPIP)] } {
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set DIN_LPIP "$::env(XRAY_ROI_DIN_LPIP)"
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} else { puts "Warning: No left pip for DIN has been set" }
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if { [info exists ::env(XRAY_ROI_DIN_RPIP)] } {
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set DIN_RPIP "$::env(XRAY_ROI_DIN_RPIP)"
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} else { puts "Warning: No right pip for DIN has been set" }
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if { [info exists ::env(XRAY_ROI_DOUT_LPIP)] } {
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set DOUT_LPIP "$::env(XRAY_ROI_DOUT_LPIP)"
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} else { puts "Warning: No left pip for DOUT has been set" }
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if { [info exists ::env(XRAY_ROI_DOUT_RPIP)] } {
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set DOUT_RPIP "$::env(XRAY_ROI_DOUT_RPIP)"
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} else { puts "Warning: No right pip for DOUT has been set" }
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# Setting all INT_L/R tiles for DIN and DOUT X values
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if { [info exists ::env(XRAY_ROI_DIN_INT_L_X)] } {
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set DIN_INT_L_X "$::env(XRAY_ROI_DIN_INT_L_X)"
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} else { puts "Warning: No INT_L for DIN has been set" }
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if { [info exists ::env(XRAY_ROI_DIN_INT_R_X)] } {
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set DIN_INT_R_X "$::env(XRAY_ROI_DIN_INT_R_X)"
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} else { puts "Warning: No INT_R for DIN has been set" }
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if { [info exists ::env(XRAY_ROI_DOUT_INT_L_X)] } {
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set DOUT_INT_L_X "$::env(XRAY_ROI_DOUT_INT_L_X)"
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} else { puts "Warning: No INT_L for DOUT has been set" }
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if { [info exists ::env(XRAY_ROI_DOUT_INT_R_X)] } {
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set DOUT_INT_R_X "$::env(XRAY_ROI_DOUT_INT_R_X)"
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} else { puts "Warning: No INT_R for DOUT has been set" }
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# X12 in the ROI, X10 just to the left
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# Start at bottom left of ROI and work up
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# (IOs are to left)
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@ -40,6 +80,9 @@ set Y_DIN_BASE [expr "$Y_CLK_BASE + $PITCH"]
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# Note: can actually go up one more if we want
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set Y_DOUT_BASE [expr "$XRAY_ROI_Y1 - $DIN_N * $PITCH"]
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# Y_OFFSET: offset amount to shift the components on the y column to avoid hard blocks
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set Y_OFFSET 24
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set part "$::env(XRAY_PART)"
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set pincfg ""
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if { [info exists ::env(XRAY_PINCFG) ] } {
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@ -129,6 +172,7 @@ if {$part eq "xc7a50tfgg484-1"} {
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set pin [lindex $leds $i]
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set net2pin(dout[$i]) $pin
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}
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# Arty A7 pmod
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# Disabled per above
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} elseif {$pincfg eq "ARTY-A7-PMOD"} {
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@ -210,6 +254,9 @@ if {$part eq "xc7a50tfgg484-1"} {
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set net2pin(dout[$i]) $pin
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}
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# setting Y_OFFSET to zero only for zynq parts
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set Y_OFFSET 0
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} else {
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error "Unsupported config $pincfg"
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}
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@ -315,7 +362,7 @@ if {$fixed_xdc eq ""} {
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puts "Placing ROI inputs"
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set y_left $Y_DIN_BASE
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# Shift y_right up to avoid PCIe block that makes routing hard.
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set y_right [expr {$Y_DIN_BASE + 24}]
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set y_right [expr {$Y_DIN_BASE + $Y_OFFSET}]
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for {set i 0} {$i < $DIN_N} {incr i} {
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if {[net_bank_left "din[$i]"]} {
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loc_lut_in $i $XRAY_ROI_X0 $y_left
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@ -423,7 +470,7 @@ if {$fixed_xdc eq ""} {
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# It will go to high level interconnect that goes everywhere
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# But we still need to record something, so lets force a route
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# FIXME: very ROI specific
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set node "CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0"
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set node "$XRAY_ROI_HCLK"
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set wire [node2wire $node]
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route_via2 "clk_IBUF_BUFG" "$node"
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set net "clk"
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@ -433,15 +480,15 @@ if {$fixed_xdc eq ""} {
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puts "Routing ROI inputs"
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# Arbitrary offset as observed
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set y_left $Y_DIN_BASE
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set y_right [expr {$Y_DIN_BASE + 24}]
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set y_right [expr {$Y_DIN_BASE + $Y_OFFSET}]
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for {set i 0} {$i < $DIN_N} {incr i} {
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# needed to force routes away to avoid looping into ROI
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if {[net_bank_left "din[$i]"]} {
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set node "INT_L_X0Y${y_left}/EE2BEG2"
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set node "INT_L_X${DIN_INT_L_X}Y${y_left}/${DIN_LPIP}"
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route_via2 "din_IBUF[$i]" "$node"
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set y_left [expr {$y_left + $PITCH}]
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} else {
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set node "INT_R_X25Y${y_right}/WW2BEG1"
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set node "INT_R_X${DIN_INT_R_X}Y${y_right}/${DIN_RPIP}"
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route_via2 "din_IBUF[$i]" "$node"
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set y_right [expr {$y_right + $PITCH}]
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}
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@ -460,25 +507,12 @@ if {$fixed_xdc eq ""} {
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set y_right [expr {$Y_DOUT_BASE + 0}]
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for {set i 0} {$i < $DOUT_N} {incr i} {
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if {[net_bank_left "dout[$i]"]} {
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# XXX: find a better solution if we need harness long term
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# works on 50t but not 35t
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if {$part eq "xc7a50tfgg484-1"} {
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set node "INT_L_X1Y${y_left}/WW2BEG0"
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route_via2 "roi/dout[$i]" "$node"
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# works on 35t but not 50t
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} elseif {$part eq "xc7a35tcsg324-1"} {
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set node "INT_L_X2Y${y_left}/SW6BEG0"
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route_via2 "roi/dout[$i]" "$node"
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} elseif {$part eq "xc7a35tcpg236-1"} {
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set node "INT_L_X2Y${y_left}/SW6BEG0"
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route_via2 "roi/dout[$i]" "$node"
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} else {
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error "Routing: unsupported part $part"
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}
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set node "INT_L_X${DOUT_INT_L_X}Y${y_left}/${DOUT_LPIP}"
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route_via2 "roi/dout[$i]" "$node"
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set y_left [expr {$y_left + $PITCH}]
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# XXX: only care about right ports on Arty
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} else {
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set node "INT_R_X23Y${y_right}/LH12"
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set node "INT_R_X${DOUT_INT_R_X}Y${y_right}/${DOUT_RPIP}"
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route_via2 "roi/dout[$i]" "$node"
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set y_right [expr {$y_right + $PITCH}]
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}
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@ -16,4 +16,22 @@ export XRAY_PIN_06="K19"
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# ROI is in top right
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export XRAY_ROI_LARGE="SLICE_X22Y50:SLICE_X43Y99"
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# HCLK Tile
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export XRAY_ROI_HCLK="CLK_HROW_TOP_R_X82Y78/CLK_HROW_CK_BUFHCLK_R0"
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# PITCH
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export XRAY_PITCH=3
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# INT_L/R for DOUT and DIN
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export XRAY_ROI_DIN_INT_L_X=
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export XRAY_ROI_DIN_INT_R_X="31"
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export XRAY_ROI_DOUT_INT_L_X=
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export XRAY_ROI_DOUT_INT_R_X="29"
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# PIPS for DOUT and DIN
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export XRAY_ROI_DIN_LPIP=
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export XRAY_ROI_DIN_RPIP="WW2BEG1"
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export XRAY_ROI_DOUT_LPIP=
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export XRAY_ROI_DOUT_RPIP="EE2BEG0"
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source $XRAY_DIR/utils/environment.sh
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