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fuzzers: 017: rename PRECYINIT_{0|1} -> PRECYINIT_{C0|C1} 

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
This commit is contained in:
Karol Gugala 2019-01-02 21:18:11 +01:00
parent 3b3b347af5
commit 5fcfc4d61b
2 changed files with 9 additions and 6 deletions
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4
fuzzers/017-clbprecyinit/bits.dbf
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@ -1,3 +1,3 @@
00_12 30_14 30_13,CLB.SLICE_X0.PRECYINIT.0
01_11 31_13 31_12,CLB.SLICE_X1.PRECYINIT.0
00_12 30_14 30_13,CLB.SLICE_X0.PRECYINIT.C0
01_11 31_13 31_12,CLB.SLICE_X1.PRECYINIT.C0

11
fuzzers/017-clbprecyinit/generate.py
View File

@ -9,17 +9,20 @@ f = open('params.csv', 'r')
f.readline()
for l in f:
module, loc, loc2 = l.split(',')
tmp = module.replace('clb_PRECYINIT_0', 'C0')
tmp = tmp.replace('clb_PRECYINIT_1', 'C1')
# clb_PRECYINIT_AX => AX
src = module.replace('clb_PRECYINIT_', '')
src = tmp.replace('clb_PRECYINIT_', '')
'''
PRECYINIT
00_12 30_14 30_13
1 0 1 0
C1 0 1 0
AX 1 0 0
CIN 0 0 1
0 0 0 0
C0 0 0 0
'''
srcs = ('0', '1', 'AX', 'CIN')
srcs = ('C0', 'C1', 'AX', 'CIN')
for asrc in srcs:
segmk.add_site_tag(loc, "PRECYINIT.%s" % asrc, int(src == asrc))