mirror of https://github.com/openXC7/prjxray.git
xadc: tilegrid support
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
parent
0594db79c6
commit
5acda63b46
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@ -22,7 +22,7 @@ build/bram/deltas:
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build/iob/deltas:
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build/iob/deltas:
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bash generate.sh build/iob iob
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bash generate.sh build/iob iob
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build/tilegrid_tdb.json: iob/build/segbits_tilegrid.tdb mmcm/build/segbits_tilegrid.tdb pll/build/segbits_tilegrid.tdb
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build/tilegrid_tdb.json: add_tdb.py iob/build/segbits_tilegrid.tdb mmcm/build/segbits_tilegrid.tdb pll/build/segbits_tilegrid.tdb
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python3 add_tdb.py --fn-in build/basicdb/tilegrid.json --fn-out build/tilegrid_tdb.json
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python3 add_tdb.py --fn-in build/basicdb/tilegrid.json --fn-out build/tilegrid_tdb.json
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iob/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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iob/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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@ -34,6 +34,10 @@ mmcm/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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pll/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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pll/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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cd pll && $(MAKE)
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cd pll && $(MAKE)
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# FIXME: add monitor to ROI
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monitor/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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cd monitor && $(MAKE)
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build/tilegrid.json: generate_full.py build/tilegrid_tdb.json build/clb/deltas build/bram/deltas
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build/tilegrid.json: generate_full.py build/tilegrid_tdb.json build/clb/deltas build/bram/deltas
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cd build && python3 ${FUZDIR}/generate_full.py \
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cd build && python3 ${FUZDIR}/generate_full.py \
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--json-in tilegrid_tdb.json --json-out ${BUILD_DIR}/tilegrid.json \
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--json-in tilegrid_tdb.json --json-out ${BUILD_DIR}/tilegrid.json \
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@ -2,6 +2,7 @@
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from prjxray import util
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from prjxray import util
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import json
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import json
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import os
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# Copied from generate_full.py
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# Copied from generate_full.py
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@ -101,6 +102,12 @@ def run(fn_in, fn_out, verbose=False):
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# FIXME: height
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# FIXME: height
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("pll/build/segbits_tilegrid.tdb", 30, 101),
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("pll/build/segbits_tilegrid.tdb", 30, 101),
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]
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]
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# FIXME: support XADC in ROI
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if os.path.exists("monitor/build/segbits_tilegrid.tdb"):
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# FIXME: height
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tdb_fns.append(("monitor/build/segbits_tilegrid.tdb", 30, 101))
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for (tdb_fn, frames, words) in tdb_fns:
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for (tdb_fn, frames, words) in tdb_fns:
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for (tile, frame, wordidx) in load_db(tdb_fn):
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for (tile, frame, wordidx) in load_db(tdb_fn):
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tilej = database[tile]
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tilej = database[tile]
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@ -0,0 +1,4 @@
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N ?= 2
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GENERATE_ARGS?="--oneval 1 --design params.csv --dframe 1C --dword 53 --dbit 24"
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include ../fuzzaddr/common.mk
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@ -0,0 +1,26 @@
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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run
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@ -0,0 +1,90 @@
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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def gen_sites():
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# yield ("MONITOR_BOT_X46Y79", "XADC_X0Y0")
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for tile_name, site_name, _site_type in util.get_roi().gen_sites(['XADC']):
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yield tile_name, site_name
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def write_params(params):
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pinstr = 'tile,val,site\n'
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for tile, (site, val) in sorted(params.items()):
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pinstr += '%s,%s,%s\n' % (tile, val, site)
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open('params.csv', 'w').write(pinstr)
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def run():
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print(
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'''
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 8;
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localparam integer DOUT_N = 8;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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''')
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params = {}
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# only one for now, worry about later
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sites = list(gen_sites())
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assert len(sites) == 1, len(sites)
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for (tile_name, site_name), isone in zip(sites,
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util.gen_fuzz_states(len(sites))):
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INIT_43 = isone
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params[tile_name] = (site_name, INIT_43)
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print(
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'''
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(* KEEP, DONT_TOUCH *)
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XADC #(/*.LOC("%s"),*/ .INIT_43(%u)) dut_%s(
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.BUSY(),
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.DRDY(),
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.EOC(),
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.EOS(),
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.JTAGBUSY(),
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.JTAGLOCKED(),
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.JTAGMODIFIED(),
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.OT(),
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.DO(),
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.ALM(),
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.CHANNEL(),
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.MUXADDR(),
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.CONVST(),
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.CONVSTCLK(clk),
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.DCLK(clk),
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.DEN(),
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.DWE(),
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.RESET(),
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.VN(),
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.VP(),
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.DI(),
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.VAUXN(),
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.VAUXP(),
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.DADDR());
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''' % (site_name, INIT_43, site_name))
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print("endmodule")
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write_params(params)
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if __name__ == '__main__':
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run()
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