luke
/
prjxray
mirror of https://github.com/openXC7/prjxray.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

docs: hierarchy 

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
Unai Martinez-Corral 2022-02-23 03:18:29 +01:00
parent a92d3a1d8e
commit 5a41cf408b
3 changed files with 16 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
docs/architecture/index.rst
View File

@ -1,16 +0,0 @@
============================
Xilinx 7-series Architecture
============================
.. toctree::
:maxdepth: 1
overview
configuration
bitstream_format
interconnect
dram_configuration
glossary
reference
code_of_conduct
updating_the_docs

15
docs/db_dev_process/index.rst
View File

@ -1,15 +0,0 @@
============================
Database Development Process
============================
.. toctree::
:maxdepth: 1
readme
contributing
new_fuzzer
fuzzers/index
minitests/index
parts
newpart

18
docs/index.rst
View File

@ -25,13 +25,27 @@ to develop a free and open Verilog to bitstream toolchain for these devices.
:maxdepth: 2
:caption: Xilinx 7-Series Architecture
architecture/index
architecture/overview
architecture/configuration
architecture/bitstream_format
architecture/interconnect
architecture/dram_configuration
architecture/glossary
architecture/reference
architecture/code_of_conduct
architecture/updating_the_docs
.. toctree::
:maxdepth: 2
:caption: Database Development Process
db_dev_process/index
db_dev_process/readme
db_dev_process/contributing
db_dev_process/new_fuzzer
db_dev_process/fuzzers/index
db_dev_process/minitests/index
db_dev_process/parts
db_dev_process/newpart
.. toctree::
:maxdepth: 2