luke
/
prjxray
mirror of https://github.com/openXC7/prjxray.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Run make format. 

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-02-01 13:49:26 -08:00
parent 6caa47202b
commit 570b99dd4f
2 changed files with 35 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
fuzzers/028-fifo-config/generate.py
View File

@ -8,16 +8,24 @@ from prjxray import verilog
def add_enum_bits(segmk, params, key, options):
for opt in options:
segmk.add_site_tag(params['tile'], '{}_{}'.format(key, opt), params[key] == opt)
segmk.add_site_tag(
params['tile'], '{}_{}'.format(key, opt), params[key] == opt)
def output_integer_tags(segmk, params, key, invert=False):
tile = params['tile']
bits = verilog.parse_bitstr(params[key])
for bit, tag_val in enumerate(bits):
if not invert:
segmk.add_tile_tag(tile, "{}[{}]".format(key, len(bits)-bit-1), tag_val)
segmk.add_tile_tag(
tile, "{}[{}]".format(key,
len(bits) - bit - 1), tag_val)
else:
segmk.add_tile_tag(tile, "Z{}[{}]".format(key, len(bits)-bit-1), 0 if tag_val else 1)
segmk.add_tile_tag(
tile, "Z{}[{}]".format(key,
len(bits) - bit - 1),
0 if tag_val else 1)
def main():
segmk = Segmaker("design.bits")
@ -28,8 +36,10 @@ def main():
for tile_param in params:
if tile_param['EN_SYN'] and tile_param['DATA_WIDTH'] == 4:
output_integer_tags(segmk, tile_param, 'ALMOST_EMPTY_OFFSET', invert=True)
output_integer_tags(segmk, tile_param, 'ALMOST_FULL_OFFSET', invert=True)
output_integer_tags(
segmk, tile_param, 'ALMOST_EMPTY_OFFSET', invert=True)
output_integer_tags(
segmk, tile_param, 'ALMOST_FULL_OFFSET', invert=True)
for param in ('EN_SYN', 'FIRST_WORD_FALL_THROUGH'):
segmk.add_tile_tag(tile_param['tile'], param, tile_param[param])

32
fuzzers/028-fifo-config/top.py
View File

@ -9,6 +9,7 @@ from prjxray import verilog
from prjxray.verilog import vrandbits
from prjxray.db import Database
def gen_sites():
db = Database(util.get_db_root())
grid = db.grid()
@ -25,6 +26,7 @@ def gen_sites():
yield tile_name, sites
@functools.lru_cache(maxsize=None)
def prepare_rand_int_choices(minval, maxval):
""" Creates list ints between minval and maxval to allow fuzzer to uniquely identify all bits."""
@ -32,14 +34,15 @@ def prepare_rand_int_choices(minval, maxval):
assert maxval >= minval
min_p2 = math.floor(math.log(max(minval, 1), 2))
max_p2 = math.ceil(math.log(maxval+1, 2))
max_p2 = math.ceil(math.log(maxval + 1, 2))
if 2**max_p2 > maxval:
max_search_p2 = max_p2 - 1
else:
max_search_p2 = max_p2
choices = set([minval, maxval, 2**(min_p2+1)-1, 2**(max_search_p2)-1])
choices = set(
[minval, maxval, 2**(min_p2 + 1) - 1, 2**(max_search_p2) - 1])
lb = min_p2
ub = max_search_p2
@ -65,7 +68,7 @@ def prepare_rand_int_choices(minval, maxval):
choices.add(2**bit)
else:
choices.add(2**bit | 2**max_search_p2)
choices.add(2**bit | 2**(max_search_p2-1))
choices.add(2**bit | 2**(max_search_p2 - 1))
zeros = set()
ones = set()
@ -85,9 +88,11 @@ def prepare_rand_int_choices(minval, maxval):
return tuple(sorted(choices))
def rand_int(minval, maxval):
return random.choice(prepare_rand_int_choices(minval, maxval))
def main():
print('''
module top();
@ -146,18 +151,23 @@ module top();
MIN_ALMOST_EMPTY_OFFSET = MIN_ALMOST_FULL_OFFSET + 1
MAX_ALMOST_EMPTY_OFFSET = MAX_ALMOST_FULL_OFFSET + 1
ALMOST_EMPTY_OFFSET = rand_int(MIN_ALMOST_EMPTY_OFFSET, MAX_ALMOST_EMPTY_OFFSET)
ALMOST_FULL_OFFSET = rand_int(MIN_ALMOST_FULL_OFFSET, MAX_ALMOST_FULL_OFFSET)
params['ALMOST_EMPTY_OFFSET'] = "13'b{:013b}".format(ALMOST_EMPTY_OFFSET)
ALMOST_EMPTY_OFFSET = rand_int(
MIN_ALMOST_EMPTY_OFFSET, MAX_ALMOST_EMPTY_OFFSET)
ALMOST_FULL_OFFSET = rand_int(
MIN_ALMOST_FULL_OFFSET, MAX_ALMOST_FULL_OFFSET)
params['ALMOST_EMPTY_OFFSET'] = "13'b{:013b}".format(
ALMOST_EMPTY_OFFSET)
params['ALMOST_FULL_OFFSET'] = "13'b{:013b}".format(ALMOST_FULL_OFFSET)
if params['DATA_WIDTH'] == 36:
params['FIFO_MODE'] = verilog.quote('FIFO36_72')
else:
params['FIFO_MODE'] = verilog.quote('FIFO36_72')#verilog.quote('FIFO18') #verilog.quote(random.choice(('FIFO18', 'FIFO18_36')))
params['FIFO_MODE'] = verilog.quote(
'FIFO36_72'
) #verilog.quote('FIFO18') #verilog.quote(random.choice(('FIFO18', 'FIFO18_36')))
params['INIT'] = '0' #vrandbits(36)
params['SRVAL'] = '0' #vrandbits(36)
params['INIT'] = '0' #vrandbits(36)
params['SRVAL'] = '0' #vrandbits(36)
print(
'''
@ -174,9 +184,7 @@ module top();
.SRVAL({SRVAL})
) fifo_{site} (
);
'''.format(
**params,
))
'''.format(**params, ))
params['FIFO_MODE'] = verilog.unquote(params['FIFO_MODE'])