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Merge pull request #94 from unixb0y/master 

Fixed the newly renamed README.md files
This commit is contained in:
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53
fuzzers/005-tilegrid/README.md
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This fuzzer creates the tilegrid.json bitstream database
This database contains segment definitions including base frame address and frame offsets
# Tilegrid Fuzzer
Example workflow for CLB:
generate.tcl LOCs one LUT per segment column towards generating frame base addresses
A reference bitstream is generated and then a series of bitstreams are generated each with one LUT bit toggled
These are compared to find a toggled bit in the CLB segment column
The resulting address is truncated to get the base frame address
Finally, generate.py calculates the segment word offsets based on known segment column structure
This fuzzer creates the tilegrid.json bitstream database
This database contains segment definitions including base frame address and frame offsets
## Example workflow for CLB
generate.tcl LOCs one LUT per segment column towards generating frame base addresses
A reference bitstream is generated and then a series of bitstreams are generated each with one LUT bit toggled
These are compared to find a toggled bit in the CLB segment column
The resulting address is truncated to get the base frame address
Finally, generate.py calculates the segment word offsets based on known segment column structure
Environment variables
## Environment variables
XRAY_ROI
This environment variable must be set with a valid ROI
See database for example values
### XRAY_ROI
This environment variable must be set with a valid ROI
See database for example values
XRAY_ROI_FRAMES
This can be set to a specific value to speed up processing and reduce disk space
If you don't know where your ROI is, just set to to include all values (0x00000000:0xfffffff)
XRAY_ROI_GRID_*
Optionally these as a small performance optimization:
-XRAY_ROI_GRID_X1
-XRAY_ROI_GRID_X2
-XRAY_ROI_GRID_Y1
-XRAY_ROI_GRID_Y2
Which should, if unused, be set to -1, with this caveat:
WARNING: CLB test generates this based on CLBs but implicitly includes INT
Therefore, if you don't set an explicit XRAY_ROI_GRID_* it may fail
if you don't have a CLB*_L at left and a CLB*_R at right
### XRAY_ROI_FRAMES
This can be set to a specific value to speed up processing and reduce disk space
If you don't know where your ROI is, just set to to include all values (0x00000000:0xfffffff)
### XRAY_ROI_GRID_*
Optionally these as a small performance optimization:
-XRAY_ROI_GRID_X1
-XRAY_ROI_GRID_X2
-XRAY_ROI_GRID_Y1
-XRAY_ROI_GRID_Y2
Which should, if unused, be set to -1, with this caveat:
WARNING: CLB test generates this based on CLBs but implicitly includes INT
Therefore, if you don't set an explicit XRAY_ROI_GRID_* it may fail
if you don't have a CLB*_L at left and a CLB*_R at right

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fuzzers/011-ffconfig/README.md
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Documents the following:
-FF clock inversion
-FF primitive mapping
-FF initialization value
# FFConfig Fuzzer
Clock inversion is per slice (as BEL CLKINV)
Vivado GUI is misleading as it often shows it per FF, which is not actually true
FFSYNC LATCH ZRST
Sample 00_48 30_32 30_12
FDPE
FDSE X
FDRE X X
FDCE X
LDCE X X
LDPE X
Documents the following:
-FF clock inversion
-FF primitive mapping
-FF initialization value
Clock inversion is per slice (as BEL CLKINV)
Vivado GUI is misleading as it often shows it per FF, which is not actually true
| |FFSYNC|LATCH|ZRST |
|------|------|-----|-----|
|Sample| 00_48|30_32|30_12|
|FDPE | | | |
|FDSE | X | | |
|FDRE | X | | X |
|FDCE | | | X |
|LDCE | | X | X |
|LDPE | | X | |
```
CLB.SLICE_X0.A5FF.ZINIT 31_06
CLB.SLICE_X0.A5FF.ZRESET 01_07
CLB.SLICE_X0.AFF.ZINIT 31_03
@ -55,4 +58,4 @@ CLB.SLICE_X1.DFF.ZINIT 31_59
CLB.SLICE_X1.DFF.ZRESET 31_50
CLB.SLICE_X1.FFSYNC 01_31
CLB.SLICE_X1.LATCH 31_32
```

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fuzzers/012-clbn5ffmux/README.md
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Purpose:
# CLBn5FFMUX Fuzzer
## Purpose
Document A5FFMUX family of CLB muxes
Algorithm:
*5FFMUX
Inputs can come from either the LUT6_2 NO5 output or the CLB NX input
To perturb the CLB the smallest, want LUT6 always instantiated
However, some routing congestion that would require putting FFs in bypass
(which turns out is actually okay, but didn't realize that at the time)
Decided instead ot instantiate LUT8, but not use the output
Turns out this is okay and won't optimize things away
So then, the 5FF D input is switched between the O5 output and an external CLB input
## Algorithm
5FFMUX
Inputs can come from either the LUT6_2 NO5 output or the CLB NX input
To perturb the CLB the smallest, want LUT6 always instantiated
However, some routing congestion that would require putting FFs in bypass
(which turns out is actually okay, but didn't realize that at the time)
Decided instead ot instantiate LUT8, but not use the output
Turns out this is okay and won't optimize things away
So then, the 5FF D input is switched between the O5 output and an external CLB input
Outcome:
## Outcome
Bits are one hot encoded per mux position

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fuzzers/013-clbncy0/README.md
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Purpose:
# CLBnCY0 Fuzzer
## Purpose
Document ACY0 family of CLB muxes
Algorithm:
Outcome:
## Algorithm
## Outcome

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fuzzers/014-ffsrcemux/README.md
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Purpose:
# FFSRCEMUX Fuzzer
## Purpose
Document CEUSEDMUX, SRUSEDMUX muxes
Algorithm:
## Algorithm
Results:
## Results
CEUSEDMUX: whether clock enable (CE) is used or clock always on
0: always on
1: controlled
CLB.SLICE_X0.CEUSEDMUX 00_39
CLB.SLICE_X1.CEUSEDMUX <0 candidates>
### CEUSEDMUX: whether clock enable (CE) is used or clock always on
0: always on
1: controlled
CLB.SLICE_X0.CEUSEDMUX 00_39
CLB.SLICE_X1.CEUSEDMUX <0 candidates>
SRUSEDMUX: whether FF can be reset or simply uses D value
(How used when SR?)
0: never reset
1: controlled
CLB.SLICE_X0.SRUSEDMUX 00_35
CLB.SLICE_X1.SRUSEDMUX <0 candidates>
### SRUSEDMUX: whether FF can be reset or simply uses D value
(How used when SR?)
0: never reset
1: controlled
CLB.SLICE_X0.SRUSEDMUX 00_35
CLB.SLICE_X1.SRUSEDMUX <0 candidates>

81
fuzzers/015-clbnffmux/README.md
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Purpose:
Document nFFMUX family of CLB muxes
Algorithm:
Outcome:
CLB.SLICE_X0.AFFMUX.B0 30_00
CLB.SLICE_X0.AFFMUX.B1 30_01
CLB.SLICE_X0.AFFMUX.B2 30_02
CLB.SLICE_X0.AFFMUX.B3 30_03
CLB.SLICE_X0.BFFMUX.B0 30_27
CLB.SLICE_X0.BFFMUX.B1 30_26
CLB.SLICE_X0.BFFMUX.B2 30_25
CLB.SLICE_X0.BFFMUX.B3 30_24
CLB.SLICE_X0.CFFMUX.B0 30_35
CLB.SLICE_X0.CFFMUX.B1 30_36
CLB.SLICE_X0.CFFMUX.B2 30_37
CLB.SLICE_X0.CFFMUX.B3 30_38
CLB.SLICE_X0.DFFMUX.B0 30_62
CLB.SLICE_X0.DFFMUX.B1 30_61
CLB.SLICE_X0.DFFMUX.B2 30_60
CLB.SLICE_X0.DFFMUX.B3 30_59
CLB.SLICE_X1.AFFMUX.B0 31_00
CLB.SLICE_X1.AFFMUX.B1 31_01
CLB.SLICE_X1.AFFMUX.B2 31_02
CLB.SLICE_X1.AFFMUX.B3 30_04
CLB.SLICE_X1.BFFMUX.B0 31_25
CLB.SLICE_X1.BFFMUX.B1 31_27
CLB.SLICE_X1.BFFMUX.B2 31_26
CLB.SLICE_X1.BFFMUX.B3 31_24
CLB.SLICE_X1.CFFMUX.B0 31_35
CLB.SLICE_X1.CFFMUX.B1 31_38
CLB.SLICE_X1.CFFMUX.B2 31_37
CLB.SLICE_X1.CFFMUX.B3 31_36
CLB.SLICE_X1.DFFMUX.B0 30_58
CLB.SLICE_X1.DFFMUX.B1 31_61
CLB.SLICE_X1.DFFMUX.B2 31_62
CLB.SLICE_X1.DFFMUX.B3 31_60
# CLBnFFMUX Fuzzer
## Purpose
Document nFFMUX family of CLB muxes
## Algorithm
## Outcome
```
CLB.SLICE_X0.AFFMUX.B0 30_00
CLB.SLICE_X0.AFFMUX.B1 30_01
CLB.SLICE_X0.AFFMUX.B2 30_02
CLB.SLICE_X0.AFFMUX.B3 30_03
CLB.SLICE_X0.BFFMUX.B0 30_27
CLB.SLICE_X0.BFFMUX.B1 30_26
CLB.SLICE_X0.BFFMUX.B2 30_25
CLB.SLICE_X0.BFFMUX.B3 30_24
CLB.SLICE_X0.CFFMUX.B0 30_35
CLB.SLICE_X0.CFFMUX.B1 30_36
CLB.SLICE_X0.CFFMUX.B2 30_37
CLB.SLICE_X0.CFFMUX.B3 30_38
CLB.SLICE_X0.DFFMUX.B0 30_62
CLB.SLICE_X0.DFFMUX.B1 30_61
CLB.SLICE_X0.DFFMUX.B2 30_60
CLB.SLICE_X0.DFFMUX.B3 30_59
CLB.SLICE_X1.AFFMUX.B0 31_00
CLB.SLICE_X1.AFFMUX.B1 31_01
CLB.SLICE_X1.AFFMUX.B2 31_02
CLB.SLICE_X1.AFFMUX.B3 30_04
CLB.SLICE_X1.BFFMUX.B0 31_25
CLB.SLICE_X1.BFFMUX.B1 31_27
CLB.SLICE_X1.BFFMUX.B2 31_26
CLB.SLICE_X1.BFFMUX.B3 31_24
CLB.SLICE_X1.CFFMUX.B0 31_35
CLB.SLICE_X1.CFFMUX.B1 31_38
CLB.SLICE_X1.CFFMUX.B2 31_37
CLB.SLICE_X1.CFFMUX.B3 31_36
CLB.SLICE_X1.DFFMUX.B0 30_58
CLB.SLICE_X1.DFFMUX.B1 31_61
CLB.SLICE_X1.DFFMUX.B2 31_62
CLB.SLICE_X1.DFFMUX.B3 31_60
```

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fuzzers/016-clbnoutmux/README.md
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Purpose:
Document nOUTMUX family of CLB muxes
TODO: document O6
Algorithm:
Outcome:
CLB.SLICE_X0.AOUTMUX.B0 30_11
CLB.SLICE_X0.AOUTMUX.B1 30_08
CLB.SLICE_X0.AOUTMUX.B2 30_06
CLB.SLICE_X0.AOUTMUX.B3 30_07
CLB.SLICE_X0.BOUTMUX.B0 30_20
CLB.SLICE_X0.BOUTMUX.B1 30_21
CLB.SLICE_X0.BOUTMUX.B2 30_22
CLB.SLICE_X0.BOUTMUX.B3 30_23
CLB.SLICE_X0.COUTMUX.B0 30_45
CLB.SLICE_X0.COUTMUX.B1 30_44
CLB.SLICE_X0.COUTMUX.B2 30_40
CLB.SLICE_X0.COUTMUX.B3 30_43
CLB.SLICE_X0.DOUTMUX.B0 30_56
CLB.SLICE_X0.DOUTMUX.B1 30_51
CLB.SLICE_X0.DOUTMUX.B2 30_52
CLB.SLICE_X0.DOUTMUX.B3 30_57
CLB.SLICE_X1.AOUTMUX.B0 31_09
CLB.SLICE_X1.AOUTMUX.B1 31_07
CLB.SLICE_X1.AOUTMUX.B2 31_10
CLB.SLICE_X1.AOUTMUX.B3 30_05
CLB.SLICE_X1.BOUTMUX.B0 31_20
CLB.SLICE_X1.BOUTMUX.B1 30_28
CLB.SLICE_X1.BOUTMUX.B2 31_21
CLB.SLICE_X1.BOUTMUX.B3 30_29
CLB.SLICE_X1.COUTMUX.B0 31_43
CLB.SLICE_X1.COUTMUX.B1 30_42
CLB.SLICE_X1.COUTMUX.B2 31_40
CLB.SLICE_X1.COUTMUX.B3 30_41
CLB.SLICE_X1.DOUTMUX.B0 31_56
CLB.SLICE_X1.DOUTMUX.B1 30_53
CLB.SLICE_X1.DOUTMUX.B2 31_57
CLB.SLICE_X1.DOUTMUX.B3 31_53
# CLBnOUTMUX Fuzzer
## Purpose
Document nOUTMUX family of CLB muxes
## Algorithm
## Outcome
```
CLB.SLICE_X0.AOUTMUX.B0 30_11
CLB.SLICE_X0.AOUTMUX.B1 30_08
CLB.SLICE_X0.AOUTMUX.B2 30_06
CLB.SLICE_X0.AOUTMUX.B3 30_07
CLB.SLICE_X0.BOUTMUX.B0 30_20
CLB.SLICE_X0.BOUTMUX.B1 30_21
CLB.SLICE_X0.BOUTMUX.B2 30_22
CLB.SLICE_X0.BOUTMUX.B3 30_23
CLB.SLICE_X0.COUTMUX.B0 30_45
CLB.SLICE_X0.COUTMUX.B1 30_44
CLB.SLICE_X0.COUTMUX.B2 30_40
CLB.SLICE_X0.COUTMUX.B3 30_43
CLB.SLICE_X0.DOUTMUX.B0 30_56
CLB.SLICE_X0.DOUTMUX.B1 30_51
CLB.SLICE_X0.DOUTMUX.B2 30_52
CLB.SLICE_X0.DOUTMUX.B3 30_57
CLB.SLICE_X1.AOUTMUX.B0 31_09
CLB.SLICE_X1.AOUTMUX.B1 31_07
CLB.SLICE_X1.AOUTMUX.B2 31_10
CLB.SLICE_X1.AOUTMUX.B3 30_05
CLB.SLICE_X1.BOUTMUX.B0 31_20
CLB.SLICE_X1.BOUTMUX.B1 30_28
CLB.SLICE_X1.BOUTMUX.B2 31_21
CLB.SLICE_X1.BOUTMUX.B3 30_29
CLB.SLICE_X1.COUTMUX.B0 31_43
CLB.SLICE_X1.COUTMUX.B1 30_42
CLB.SLICE_X1.COUTMUX.B2 31_40
CLB.SLICE_X1.COUTMUX.B3 30_41
CLB.SLICE_X1.DOUTMUX.B0 31_56
CLB.SLICE_X1.DOUTMUX.B1 30_53
CLB.SLICE_X1.DOUTMUX.B2 31_57
CLB.SLICE_X1.DOUTMUX.B3 31_53
```
From manual O6 testing
30_11 X0 AOUTMUX O6
30_20 X0 BOUTMUX O6
30_45 X0 COUTMUX O6
30_56 X0 DOUTMUX O6
31_09 X1 AOUTMUX O6
31_20 X1 BOUTMUX O6
31_43 X1 COUTMUX O6
31_56 X1 DOUTMUX O6
```
30_11 X0 AOUTMUX O6
30_20 X0 BOUTMUX O6
30_45 X0 COUTMUX O6
30_56 X0 DOUTMUX O6
31_09 X1 AOUTMUX O6
31_20 X1 BOUTMUX O6
31_43 X1 COUTMUX O6
31_56 X1 DOUTMUX O6
```

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fuzzers/017-clbprecyinit/README.md
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Purpose:
# CLBPRECYINIT Fuzzer
## Purpose
Document PRECYINIT mux
Algorithm:
## Algorithm
Outcome:
## Outcome
```
CLB.SLICE_X0.PRECYINIT.0 <0 candidates>
CLB.SLICE_X0.PRECYINIT.1 00_12
CLB.SLICE_X0.PRECYINIT.AX 30_14
@ -13,4 +16,4 @@ CLB.SLICE_X1.PRECYINIT.0 <0 candidates>
CLB.SLICE_X1.PRECYINIT.1 01_11
CLB.SLICE_X1.PRECYINIT.AX 31_13
CLB.SLICE_X1.PRECYINIT.CIN 31_12
```

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fuzzers/018-clbram/README.md
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Solves SLICEM specific bits:
-Shift register LUT (SRL)
-Memory size
-RAM vs LUT
-Related muxes
# CLBRAM Fuzzer
## Purpose
Solves SLICEM specific bits:
-Shift register LUT (SRL)
-Memory size
-RAM vs LUT
-Related muxes
## Algorithm
## Outcome
```
CLB.SLICE_X0.ALUT.RAM 31_16
CLB.SLICE_X0.ALUT.SMALL 00_04
CLB.SLICE_X0.ALUT.SRL 30_16
@ -19,4 +26,4 @@ CLB.SLICE_X0.DLUT.SRL 30_47
CLB.SLICE_X0.WA7USED 00_40
CLB.SLICE_X0.WA8USED 01_27
CLB.SLICE_X0.WEMUX.CE 01_23
```

2
fuzzers/019-ndi1mux/README.md
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# NDI1MUX Fuzzer
See minitest for DI notes

7
minitests/bram/README.md
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# BRAM Minitest
## Purpose
Test to verify that all the ROM* primitives are just regular LUTs and not BRAMs with init values
Result:
Confirmed: floorplan shows as LUTs and no unknown bits observed
## Result
Confirmed: floorplan shows as LUTs and no unknown bits observed

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minitests/clb_bused/README.md
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Tests for BUSED bit
However got this
# CLB_BUSED Minitest
## Purpose
Tests for BUSED bit
## Result
However got this
```
seg SEG_CLBLL_R_X13Y101
bit 30_24
seg SEG_CLBLL_R_X13Y100
bit 30_24
```
which seems to indicate there is no such bit, or it was rolled into PIP stuff already

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minitests/clb_ffcfg/README.md
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# CLB_FFCFG Minitest
## Purpose
Tests all of the documented FF "primitives"
(there are only 4 real ones)
## Result

19
minitests/clb_muxf8/README.md
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This tests an issue related to Vivado 2017.2 vs 2017.3 changing MUXF8 behavior
The general issue is the LUT6_2 cannot be used with a MUXF8 (even if O5 is unused)
# CLB_MUXF8 Minitest
General notes:
-2017.2: LUT6_2 works with MUXF8
-2017.3: LUT6_2 does not work with MUXF8
-All: LUT6 works with MUXF8
-All: MUXF8 (even with MUXF7) can be instantiated unconnected
-2017.4 seems to behave like 2017.3
## Purpose
This tests an issue related to Vivado 2017.2 vs 2017.3 changing MUXF8 behavior
The general issue is the LUT6_2 cannot be used with a MUXF8 (even if O5 is unused)
## General notes:
-2017.2: LUT6_2 works with MUXF8
-2017.3: LUT6_2 does not work with MUXF8
-All: LUT6 works with MUXF8
-All: MUXF8 (even with MUXF7) can be instantiated unconnected
-2017.4 seems to behave like 2017.3

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minitests/clb_n5ffmux/README.md
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DFFMUX
30_09 30_54
A 1 0
B 0 1
# CLB_n5FFMUX Minitest
CFFMUX
30_39 31_45
A 0 1
B 1 0
## Purpose
BFFMUX
30_18 30_19
A 0 1
B 1 0
## Result
AFFMUX
30_09 30_55
A 1 0
B 0 1
|DFFMUX|30_09|30_54|
|------|-----|-----|
| A | 1| 0|
| B | 0| 1|
|CFFMUX|30_39|31_45|
|------|-----|-----|
|A | 0| 1|
|B | 1| 0|
|BFFMUX|30_18|30_19|
|------|-----|-----|
|A | 0| 1|
|B | 1| 0|
|AFFMUX|30_09|30_55|
|------|-----|-----|
|A | 1| 0|
|B | 0| 1|

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minitests/clb_ncy0/README.md
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DCY0
30_49
O5 1
AX 0
# CLB_nCY0 Minitest
CCY0
30_48
O5 1
AX 0
## Purpose
BCY0
01_15
O5 1
AX 0
## Result
ACY0
30_15
O5 1
AX 0
|DCY0|30_49|
|----|-----|
|O5 | 1|
|AX | 0|
|CCY0|30_48|
|----|-----|
|O5 | 1|
|AX | 0|
|BCY0|01_15|
|----|-----|
|O5 | 1|
|AX | 0|
|ACY0|30_15|
|----|-----|
|O5 | 1|
|AX | 0|

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minitests/clb_ndi1mux/README.md
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Trying to set SLICEM LUT DI1 inputs
These exist for LUTA, LUTB, and LUTC only
Can either be an external signal, another LUT's data input, or another LUT's carry
Note: mux input pattern is irregular
# CLB_nDI1MUX Minitest
Result:
The following bits are set for NI but not NMC31:
## Purpose
Trying to set SLICEM LUT DI1 inputs
These exist for LUTA, LUTB, and LUTC only
Can either be an external signal, another LUT's data input, or another LUT's carry
Note: mux input pattern is irregular
## Result
The following bits are set for NI but not NMC31:
```
bit 00_00 ADI1MUX.AI
bit 00_20 BDI1MUX.BI
bit 01_43 BDI1MUX.CI
Additionally, test with unknown DI mux bits don't appear near NI bits
There is something strange going on
```
Additionally, test with unknown DI mux bits don't appear near NI bits
There is something strange going on

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minitests/clb_nffmux/README.md
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AFFMUX
30_00 30_01 30_02 30_03
F78 1 1
CY 1 1
O5 1 1
AX 1
XOR 1
O6 1
# CLB_nFFMUX Minitest
## Purpose
## Result
|AFFMUX|30_00|30_01|30_02|30_03|
|------|-----|-----|-----|-----|
|F78 | 1| 1| | |
|CY | 1| | 1| |
|O5 | 1| | | 1|
|AX | | 1| | |
|XOR | | | 1| |
|O6 | | | | 1|

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minitests/clb_ram/README.md
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SLICEM RAM test
LUT6 => 64 bits
Focus on 64 bit
32 probably uses same O5/O6 stuff
128 probably uses same MUX stuff
Why isn't there a 256?
# CLB_RAM Minitest
## Purpose
SLICEM RAM test
LUT6 => 64 bits
Focus on 64 bit
32 probably uses same O5/O6 stuff
128 probably uses same MUX stuff
Why isn't there a 256?
## Result
```
RAM128X1D 128-Deep by 1-Wide Dual Port Random Access Memory (Select RAM)
RAM128X1S 128-Deep by 1-Wide Random Access Memory (Select RAM)
RAM256X1S 256-Deep by 1-Wide Random Access Memory (Select RAM)
@ -18,5 +23,4 @@ RAM64M 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM)
RAM64X1D 64-Deep by 1-Wide Dual Port Static Synchronous RAM
RAM64X1S 64-Deep by 1-Wide Static Synchronous RAM
RAM64X1S_1 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
```

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minitests/fixedpnr/README.md
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Preliminary result
# FIXEDPNR Minitest
00_48 30_12 31_03
FDPE
FDSE X
FDCE X X
FDRE X X X
## Purpose
## Result
Preliminary result
| |00_48|30_12|31_03|
|----|-----|-----|-----|
|FDPE| | | |
|FDSE| X | | |
|FDCE| | X | X |
|FDRE| X | X | X |

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minitests/picorv32-v/README.md
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# PICORV32-v Minitest
## Purpose
Unknown bits CPU synthesis test (Vivado synthesis + Vivado PnR)
## Result

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minitests/picorv32-y/README.md
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# PICORV32-y Minitest
## Purpose
Unknown bits CPU synthesis test (Yosys synthesis + Vivado for PnR)
## Result

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minitests/roi_harness/README.md
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Creates an ROI with clk, inputs, and outputs to use as a partial reconfiguration test harness
# ROI_HARNESS Minitest
Basic idea:
-LOC LUTs in the ROI to terminate input and output routing
-Let Vivado LOC the rest of the logic
-Manually route signals in and out of the ROI enough to avoid routing loops into the ROI
-Let Vivado finish the rest of the routes
## Purpose
Creates an ROI with clk, inputs, and outputs to use as a partial reconfiguration test harness
There is no logic outside of the ROI in order to keep IOB to ROI delays short
Its expected the end user will rip out everything inside the ROI
Basic idea:
-LOC LUTs in the ROI to terminate input and output routing
-Let Vivado LOC the rest of the logic
-Manually route signals in and out of the ROI enough to avoid routing loops into the ROI
-Let Vivado finish the rest of the routes
To target Arty A7 you should source the artix DB environment script then source arty.sh
There is no logic outside of the ROI in order to keep IOB to ROI delays short
Its expected the end user will rip out everything inside the ROI
To build the baseline harness:
To target Arty A7 you should source the artix DB environment script then source arty.sh
To build the baseline harness:
```
./runme.sh
```
To build a sample Vivado design using the harness:
```
XRAY_ROIV=roi_inv.v XRAY_FIXED_XDC=out_xc7a35tcpg236-1_BASYS3-SWBUT_roi_basev/fixed_noclk.xdc ./runme.sh
```
Note: this was intended for verification only and not as an end user flow (they should use SymbiFlow)
To use the harness for the basys3 demo, do something like:
```
python3 demo_sw_led.py out_xc7a35tcpg236-1_BASYS3-SWBUT_roi_basev 3 2
```
This example connects switch 3 to LED 2
## Result