mirror of https://github.com/openXC7/prjxray.git
Delete abandoned ROM minitest
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster
parent
f953c3ddbe
commit
543fcc8037
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@ -1,8 +0,0 @@
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/.Xil
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/design/
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/design.bit
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/design.bits
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/design.dcp
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/usage_statistics_webtalk.*
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/vivado*
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/design.txt
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@ -1,27 +0,0 @@
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N := 3
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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all:
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bash runme.sh
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test -z $(fgrep CRITICAL vivado.log)
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${XRAY_SEGPRINT} -z -D design.bits >design.txt
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database: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
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pushdb:
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${XRAY_MERGEDDB} clbll_l seg_clblx.segbits
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${XRAY_MERGEDDB} clbll_r seg_clblx.segbits
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${XRAY_MERGEDDB} clblm_l seg_clblx.segbits
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${XRAY_MERGEDDB} clblm_r seg_clblx.segbits
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil
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.PHONY: database pushdb clean
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@ -1,4 +0,0 @@
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Test to verify that all the ROM* primitives are just regular LUTs and not BRAMs with init values
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Result:
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Confirmed: floorplan shows as LUTs and no unknown bits observed
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@ -1,7 +0,0 @@
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#!/bin/bash
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set -ex
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# rm -f vivado*.log vivado*.jou
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vivado -mode batch -source runme.tcl
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
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#${XRAY_SEGPRINT} design.bits SLICE_X16Y100 SLICE_X16Y101 SLICE_X16Y102 SLICE_X16Y103
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@ -1,26 +0,0 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -1,111 +0,0 @@
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/*
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ROM128X1: 128-Deep by 1-Wide ROM
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ROM256X1: 256-Deep by 1-Wide ROM
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ROM32X1: 32-Deep by 1-Wide ROM
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ROM64X1: 64-Deep by 1-Wide ROM
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*/
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 256;
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localparam integer DOUT_N = 256;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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module roi(input clk, input [255:0] din, output [255:0] dout);
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rom_ROM128X1 #(.LOC("XXX"))
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rom_ROM128X1(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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rom_ROM256X1 #(.LOC("XXX"))
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rom_ROM256X1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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rom_ROM32X1 #(.LOC("XXX"))
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rom_ROM32X1(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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rom_ROM64X1 #(.LOC("XXX"))
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rom_ROM64X1(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
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endmodule
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//******************************************************************************
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//BOUTMUX tests
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/*
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Cell as SLICEM D6LUT + C6LUT + F7BMUX
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*/
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module rom_ROM128X1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_FIXME";
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//ROM128X1 #(.LOC(LOC), .N(N))
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ROM128X1 #(.INIT(128'b0))
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rom(
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.O(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.A6(din[6]));
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endmodule
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module rom_ROM256X1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_FIXME";
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ROM256X1 #(.INIT(256'b0))
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rom(
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.O(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.A6(din[6]),
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.A7(din[7]));
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endmodule
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module rom_ROM32X1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_FIXME";
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ROM32X1 #(.INIT(32'b0))
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rom(
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.O(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]));
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endmodule
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module rom_ROM64X1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_FIXME";
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ROM64X1 #(.INIT(64'b0))
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rom(
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.O(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]));
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endmodule
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