docs: Adding warning to FIXMEs.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>

docs/architecture/interconnect.rst

@@ -6,7 +6,7 @@ Fake :term:`PIPs <pip>`
 
 Some :term:`PIPs <pip>` are not "real", in the sense that no bit pattern in the bit-stream correspond to the PIP being used. This is the case for all the :term:`PIPs <pip>` in the switchbox in a CLB tile (ex: CLBLM_L_INTER): They either correspond to buffers that are always on (i.e. 1:1 connections such as `CLBLL_L.CLBLL_L_AQ->CLBLL_LOGIC_OUTS0`), or they correspond to permutations of LUT input signals, which is handled by changing the LUT init value accordingly, or they are used to "connect" two signals that are driven by the same signal from within the CLB.
 
-FIXME: Check the above is true.
+.. warning:: FIXME: Check the above is true.
 
 The bit switchbox in an :term:`INT`s tile also contains a few 1:1 connections that are in fact always present and have no corresponding configuration bits.
 
@@ -15,7 +15,7 @@ Regular :term:`PIPs <pip>`
 
 Regular :term:`PIPs <pip>` correspond to a bit pattern that is present in the bit stream when the PIP is used in the current design. There is a block of up to 10-ish bits for each destination signal. For each configuration (i.e. source net that can drive the destination) there is a pair of bits that is set.
 
-FIXME: Check if the above is true for PIPs outside of the INT switch box.
+.. warning:: FIXME: Check if the above is true for PIPs outside of the INT switch box.
 
 For example, when the bits 05_57 and 11_56 are set then SR1END3->SE2BEG3 is enabled, but when 08_56 and 11_56 are set then ER1END3->SE2BEG3 is enabled (in an :term:`INT_L`s tile paired with a CLBLL_L tile). A configuration in which all three bits are set is invalid. See `segbits_int_[lr].db` for a complete list of bit pattern for configuring :term:`PIPs <pip>`.
 

docs/format/db.rst

@@ -21,7 +21,7 @@ The first number indicates the frame address relative to the base frame address
 
 The second number indicates the bit position width.
 
-FIXME: Expand this section. We've had a couple questions around this, probably good to get a complete description of this that we can point people too. This is probably a good place to talk about tile grid and how it applies to segbit.
+.. warning:: FIXME: Expand this section. We've had a couple questions around this, probably good to get a complete description of this that we can point people too. This is probably a good place to talk about tile grid and how it applies to segbit.
 
 
 segbits_*.db
@@ -82,7 +82,7 @@ Tags that enable interconnect :term:`PIPs <pip>` have the following syntax: `<ti
 
 The `<tile_type>` may be `INT_L` or `INT_R`. The destination and source wires are wire names in that tile type. For example, consider the following entry in `segbits_int_l.db`: `INT_L.NL1BEG1.NN6END2 07_32 12_33`
 
-FIXME: This is probably a good place to reference tileconn as the documentation that explains how wires are connected outside of switchboxes (which is what pips document).
+.. warning:: FIXME: This is probably a good place to reference tileconn as the documentation that explains how wires are connected outside of switchboxes (which is what pips document).
 
 This means that the bits `07_32` and `12_33` must be set in the segment to drive the value from the wire `NN6END2` to the wire `NL1BEG1`.
 
@@ -136,7 +136,7 @@ So in summary:
 
 So, with this in mind, we have frame base address 0x00020500 and word # 2. This maps to tilegrid.json entry SEG_CLBLL_L_X12Y101 (has "baseaddr": ["0x00020600", 2]). This also yields "type": "clbll_l" meaning we are configuring a CLBLL_L.
 
-FIXME: This example is out of date with the new tilegrid format, should update it.
+.. warning:: FIXME: This example is out of date with the new tilegrid format, should update it.
 
 
 Looking at segbits_clbll_l.db, we need to look up the bit at segment column 11, offset at bit 5. However, this is not present, so we fall back to segbits_int_l.db. This yields a few entries related to EL1BEG (ex: INT_L.EL1BEG_N3.EL1END0 11_05 13_05).

docs/format/tile.rst

@@ -20,7 +20,7 @@ The file `tilegrid.json` contains lists of all tiles in the device and the confi
 
 For each segment this contains the configuration frame base address, and the word offset within the frames, as well as the number of frames for the segment and number of occupied words in each frame.
 
-FIXME: We should cross link to how to use the base address and word offset.
+.. warning:: FIXME: We should cross link to how to use the base address and word offset.
 
 For each tile this file contains the tile type, grid X/Y coordinates for the tile, and sites (slices) within the tile.
 
@@ -111,7 +111,7 @@ tileconn.json
 
 The file `tileconn.json` contains the information how the wires of neighboring tiles are connected to each other. It contains one entry for each pair of tile types, each containing a list of pairs of wires that belong to the same node.
 
-FIXME: This is a good place to add the tile wire, pip, site pin diagram.
+.. warning:: FIXME: This is a good place to add the tile wire, pip, site pin diagram.
 
 This file documents how adjacent tile pairs are connected.
 No directionality is given.