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gtp: fix inverted signals. Change ZINV feature to INV 

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi 2021-03-04 14:29:51 +01:00
parent dbf0237b9a
commit 4ad1aa61da
4 changed files with 22 additions and 7 deletions
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2
fuzzers/063-gtp-common-conf/generate.py
View File

@ -103,7 +103,7 @@ def main():
site, "%s[%u]" % (param, i), bitstr[i])
for param in ["PLL0LOCKDETCLK", "PLL1LOCKDETCLK", "DRPCLK"]:
segmk.add_site_tag(site, "ZINV_" + param, 1 ^ params[param])
segmk.add_site_tag(site, "INV_" + param, params[param])
for param in ["GTREFCLK0_USED", "GTREFCLK1_USED",
"BOTH_GTREFCLK_USED"]:

6
fuzzers/063-gtp-common-conf/top.py
View File

@ -159,6 +159,8 @@ IBUFDS_GTE2 #(
verilog_attr += """
.{}({}),""".format(param, value_str)
verilog_ports = ""
for param in ["PLL0LOCKDETCLK", "PLL1LOCKDETCLK", "DRPCLK"]:
is_inverted = random.randint(0, 1)
@ -166,12 +168,12 @@ IBUFDS_GTE2 #(
verilog_attr += """
.IS_{}_INVERTED({}),""".format(param, is_inverted)
verilog_ports += """
.{}({}),""".format(param, luts.get_next_output_net())
verilog_attr = verilog_attr.rstrip(",")
verilog_attr += "\n)"
verilog_ports = ""
for param in ["GTREFCLK0_USED", "GTREFCLK1_USED",
"BOTH_GTREFCLK_USED"]:
params[param] = 0

3
fuzzers/064-gtp-channel-conf/generate.py
View File

@ -113,8 +113,7 @@ def main():
for param in ["TXUSRCLK", "TXUSRCLK2", "TXPHDLYTSTCLK",
"SIGVALIDCLK", "RXUSRCLK", "RXUSRCLK2", "DRPCLK",
"DMONITORCLK", "CLKRSVD0", "CLKRSVD1"]:
segmk.add_site_tag(
site, "ZINV_" + param, 1 ^ params[param])
segmk.add_site_tag(site, "INV_" + param, params[param])
gtp_channel_x = [
"GTP_CHANNEL_0",

18
fuzzers/064-gtp-channel-conf/top.py
View File

@ -17,6 +17,7 @@ from collections import namedtuple
random.seed(int(os.getenv("SEED"), 16))
from prjxray import util
from prjxray import verilog
from prjxray.lut_maker import LutMaker
from prjxray.db import Database
INT = "INT"
@ -76,6 +77,8 @@ module top(
assign out = in;
''')
luts = LutMaker()
primitives_list = list()
for tile_name, tile_type, site_name, site_type in gen_sites(
@ -122,6 +125,7 @@ assign out = in;
verilog_attr += """
.{}({}),""".format(param, value_str)
verilog_ports = ""
for param in ["TXUSRCLK", "TXUSRCLK2", "TXPHDLYTSTCLK",
"SIGVALIDCLK", "RXUSRCLK", "RXUSRCLK2", "DRPCLK",
"DMONITORCLK", "CLKRSVD0", "CLKRSVD1"]:
@ -131,19 +135,29 @@ assign out = in;
verilog_attr += """
.IS_{}_INVERTED({}),""".format(param, is_inverted)
verilog_ports += """
.{}({}),""".format(param, luts.get_next_output_net())
verilog_attr = verilog_attr.rstrip(",")
verilog_attr += "\n)"
print("(* KEEP, DONT_TOUCH, LOC=\"{}\" *)".format(site_name))
print(
"""GTPE2_CHANNEL {} {} ();
""".format(verilog_attr, tile_type.lower()))
"""GTPE2_CHANNEL {attrs} {site} (
{ports}
);
""".format(
attrs=verilog_attr,
site=tile_type.lower(),
ports=verilog_ports.rstrip(",")))
params_list.append(params)
params_dict["params"] = params_list
primitives_list.append(params_dict)
for l in luts.create_wires_and_luts():
print(l)
print("endmodule")
with open('params.json', 'w') as f: