mirror of https://github.com/openXC7/prjxray.git
tilegrid: merge in KR WIP IOB
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster
parent
621ad8a575
commit
49aa56712f
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@ -56,8 +56,9 @@ def load_baseaddrs(deltas_fns):
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# clb/design_SLICE_X10Y100.delta
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# site = arg[7:-6]
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site = re.match(r".*/design_(.*).delta", arg).group(1)
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frame = int(line[5:5 + 8], 16)
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# was "0x%08x"
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# +bit_00400026_100_02
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_, frame_str, _, _ = line.split('_')
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frame = int(frame_str, 16)
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site_baseaddr[site] = frame & ~0x7f
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return site_baseaddr
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@ -126,7 +127,6 @@ def make_segments(database, tiles_by_grid, tile_baseaddrs, verbose=False):
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Create segments data structure
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Indicates how tiles are related to bitstream locations
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Also modify database to annotate which segment the tiles belong to
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segments key examples:
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SEG_CLBLM_R_X13Y72
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SEG_BRAM3_L_X6Y85
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@ -139,6 +139,22 @@ def make_segments(database, tiles_by_grid, tile_baseaddrs, verbose=False):
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grid_x = tile_data["grid_x"]
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grid_y = tile_data["grid_y"]
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def add_segment(name, tiles, segtype, baseaddr=None):
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assert name not in segments
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segment = segments.setdefault(name, {})
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segment["tiles"] = tiles
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segment["type"] = segtype
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if baseaddr:
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verbose and print(
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'make_segment: %s baseaddr %s' % (
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name,
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baseaddr,
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))
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segment["baseaddr"] = baseaddr
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for tile_name in tiles:
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database[tile_name]["segment"] = name
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def process_clb():
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if tile_type in ["CLBLL_L", "CLBLM_L"]:
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int_tile_name = tiles_by_grid[(grid_x + 1, grid_y)]
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@ -146,24 +162,51 @@ def make_segments(database, tiles_by_grid, tile_baseaddrs, verbose=False):
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int_tile_name = tiles_by_grid[(grid_x - 1, grid_y)]
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add_segment(
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database=database,
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segments=segments,
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name="SEG_" + tile_name,
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tiles=[tile_name, int_tile_name],
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segtype=tile_type.lower(),
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baseaddr=tile_baseaddrs.get(tile_name, None),
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verbose=verbose,
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)
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baseaddr=tile_baseaddrs.get(tile_name, None))
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def process_hclk():
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add_segment(
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database=database,
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segments=segments,
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name="SEG_" + tile_name,
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tiles=[tile_name],
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segtype=tile_type.lower())
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def process_iob2():
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tiles = [tile_name]
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if tile_type.startswith('LIOB'):
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# Two INT_L's
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tiles.append(tiles_by_grid[(grid_x + 4, grid_y)])
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tiles.append(tiles_by_grid[(grid_x + 4, grid_y - 1)])
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# One IO interface tile
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tiles.append(tiles_by_grid[(grid_x + 1, grid_y)])
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else:
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# Two INT_R's
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tiles.append(tiles_by_grid[(grid_x - 4, grid_y)])
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tiles.append(tiles_by_grid[(grid_x - 4, grid_y - 1)])
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# One IO interface tile
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tiles.append(tiles_by_grid[(grid_x - 1, grid_y)])
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add_segment(
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name="SEG_" + tile_name,
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tiles=tiles,
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segtype=tile_type.lower(),
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verbose=verbose,
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)
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baseaddr=tile_baseaddrs.get(tile_name, None))
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def process_iob():
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if tile_type.startswith('LIOB'):
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int_tile_name = tiles_by_grid[(grid_x + 4, grid_y)]
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io_interface_tile_name = tiles_by_grid[(grid_x + 1, grid_y)]
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else:
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int_tile_name = tiles_by_grid[(grid_x - 4, grid_y)]
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io_interface_tile_name = tiles_by_grid[(grid_x - 1, grid_y)]
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add_segment(
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name="SEG_" + tile_name,
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tiles=[tile_name, io_interface_tile_name, int_tile_name],
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segtype=tile_type.lower(),
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baseaddr=tile_baseaddrs.get(tile_name, None))
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def process_bram_dsp():
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for k in range(5):
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@ -190,16 +233,12 @@ def make_segments(database, tiles_by_grid, tile_baseaddrs, verbose=False):
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baseaddr = None
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add_segment(
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database=database,
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segments=segments,
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# BRAM_L_X6Y70 => SEG_BRAM4_L_X6Y70
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name="SEG_" + tile_name.replace("_", "%d_" % k, 1),
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tiles=tiles,
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# BRAM_L => bram4_l
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segtype=tile_type.lower().replace("_", "%d_" % k, 1),
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baseaddr=baseaddr,
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verbose=verbose,
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)
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baseaddr=baseaddr)
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def process_default():
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#verbose and nolr(tile_type) not in ('VBRK', 'INT', 'NULL') and print('make_segment: drop %s' % (tile_type,))
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@ -211,6 +250,10 @@ def make_segments(database, tiles_by_grid, tile_baseaddrs, verbose=False):
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"HCLK": process_hclk,
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"BRAM": process_bram_dsp,
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"DSP": process_bram_dsp,
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"RIOB33": process_iob2,
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"LIOB33": process_iob2,
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"RIOB33_SING": process_iob,
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"LIOB33_SIGN": process_iob,
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}.get(nolr(tile_type), process_default)()
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return segments
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@ -218,12 +261,9 @@ def make_segments(database, tiles_by_grid, tile_baseaddrs, verbose=False):
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def get_inttile(database, segment):
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'''Return interconnect tile for given segment'''
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inttiles = [
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return (
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tile for tile in segment["tiles"]
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if database[tile]["type"] in ["INT_L", "INT_R"]
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]
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assert len(inttiles) == 1
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return inttiles[0]
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if database[tile]["type"] in ["INT_L", "INT_R"])
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def get_bramtile(database, segment):
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@ -290,52 +330,49 @@ def seg_base_addr_lr_INT(database, segments, tiles_by_grid, verbose=False):
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verbose and print(' Skip non CLB')
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continue
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inttile = get_inttile(database, segment)
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grid_x = database[inttile]["grid_x"]
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grid_y = database[inttile]["grid_y"]
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for inttile in get_inttile(database, segment):
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grid_x = database[inttile]["grid_x"]
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grid_y = database[inttile]["grid_y"]
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if database[inttile]["type"] == "INT_L":
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grid_x += 1
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framebase = framebase + 0x80
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elif database[inttile]["type"] == "INT_R":
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grid_x -= 1
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framebase = framebase - 0x80
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else:
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assert 0
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if database[inttile]["type"] == "INT_L":
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grid_x += 1
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framebase = framebase + 0x80
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elif database[inttile]["type"] == "INT_R":
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grid_x -= 1
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framebase = framebase - 0x80
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else:
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assert 0
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# ROI at edge?
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if (grid_x, grid_y) not in tiles_by_grid:
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verbose and print(' Skip edge')
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continue
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tile = tiles_by_grid[(grid_x, grid_y)]
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if database[inttile]["type"] == "INT_L":
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assert database[tile]["type"] == "INT_R"
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elif database[inttile]["type"] == "INT_R":
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assert database[tile]["type"] == "INT_L"
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else:
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assert 0
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if 'segment' not in database[tile]:
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if database[tile]['type'] in ['T_TERM_INT']:
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# ROI at edge?
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if (grid_x, grid_y) not in tiles_by_grid:
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verbose and print(' Skip edge')
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continue
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create_segment_for_int_lr(
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database, segments, tile, tiles_by_grid, verbose)
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seg = database[tile]["segment"]
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tile = tiles_by_grid[(grid_x, grid_y)]
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seg_baseaddrs = segments[seg].setdefault("baseaddr", {})
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# At least one duplicate when we re-compute the entry for the base address
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# should give the same address
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if block_type in seg_baseaddrs:
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assert seg_baseaddrs[block_type] == [
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framebase, wordbase
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], (seg_baseaddrs[block_type], [framebase, wordbase])
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verbose and print(' Existing OK')
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else:
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seg_baseaddrs[block_type] = [framebase, wordbase]
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verbose and print(' Add new')
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if database[inttile]["type"] == "INT_L":
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assert database[tile]["type"] == "INT_R"
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elif database[inttile]["type"] == "INT_R":
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assert database[tile]["type"] == "INT_L"
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else:
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assert 0
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if "segment" not in database[tile]:
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continue
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seg = database[tile]["segment"]
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seg_baseaddrs = segments[seg].setdefault("baseaddr", {})
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# At least one duplicate when we re-compute the entry for the base address
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# should give the same address
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if block_type in seg_baseaddrs:
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assert seg_baseaddrs[block_type] == [
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framebase, wordbase
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], (seg_baseaddrs[block_type], [framebase, wordbase])
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verbose and print(' Existing OK')
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else:
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seg_baseaddrs[block_type] = [framebase, wordbase]
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verbose and print(' Add new')
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def seg_base_addr_up_INT(database, segments, tiles_by_grid, verbose=False):
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@ -366,50 +403,46 @@ def seg_base_addr_up_INT(database, segments, tiles_by_grid, verbose=False):
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Use it to locate in the grid, and find other segments related by tile offset
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'''
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inttile = get_inttile(database, src_segment)
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verbose and print(
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' up_INT CLK_IO_CLK: %s => inttile %s' %
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(src_segment_name, inttile))
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grid_x = database[inttile]["grid_x"]
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grid_y = database[inttile]["grid_y"]
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for inttile in get_inttile(database, src_segment):
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verbose and print(
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' up_INT CLK_IO_CLK: %s => inttile %s' %
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(src_segment_name, inttile),
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file=sys.stderr)
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grid_x = database[inttile]["grid_x"]
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grid_y = database[inttile]["grid_y"]
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for i in range(50):
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grid_y -= 1
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if grid_y < 0:
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break
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for i in range(50):
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grid_y -= 1
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loc = (grid_x, grid_y)
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dst_tile = database[tiles_by_grid[(grid_x, grid_y)]]
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if wordbase == 50:
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wordbase += 1
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else:
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wordbase += 2
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if 'segment' not in dst_tile:
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if dst_tile['type'] in ['T_TERM_INT']:
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if loc not in tiles_by_grid:
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continue
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create_segment_for_int_lr(
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database, segments, tiles_by_grid[(grid_x,
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grid_y)],
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tiles_by_grid, verbose)
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#verbose and print(' dst_tile', dst_tile)
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dst_segment_name = dst_tile["segment"]
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#verbose and print('up_INT: %s => %s' % (src_segment_name, dst_segment_name))
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segments[dst_segment_name].setdefault(
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"baseaddr", {})[block_type] = [framebase, wordbase]
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dst_tile = database[tiles_by_grid[loc]]
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if 'segment' not in dst_tile:
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continue
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#assert 'segment' in dst_tile, ((grid_x, grid_y), dst_tile, tiles_by_grid[(grid_x, grid_y)])
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if wordbase == 50:
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wordbase += 1
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else:
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wordbase += 2
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#verbose and print(' dst_tile', dst_tile)
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dst_segment_name = dst_tile["segment"]
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#verbose and print('up_INT: %s => %s' % (src_segment_name, dst_segment_name))
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segments[dst_segment_name].setdefault(
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"baseaddr",
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{})[block_type] = [framebase, wordbase]
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def process_BLOCK_RAM(wordbase):
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'''
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Lookup BRAM0 tile associated with this segment
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Use it to locate in the grid, and find other BRAM0 related by tile offset
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From minitest:
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build/roi_bramd_bit01.diff (lowest BRAM coordinate)
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> bit_00c00000_000_00
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build/roi_bramds_bit01.diff
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> bit_00c00000_000_00
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> bit_00c00000_010_00
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@ -437,9 +470,6 @@ def seg_base_addr_up_INT(database, segments, tiles_by_grid, verbose=False):
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grid_y -= 1
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wordbase += 1
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if (grid_x, grid_y) not in tiles_by_grid:
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continue
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dst_tile = database[tiles_by_grid[(grid_x, grid_y)]]
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assert nolr(dst_tile['type']) == 'BRAM', dst_tile
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@ -459,7 +489,6 @@ def add_tile_bits(tile_db, baseaddr, offset, frames, words, height=None):
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'''
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Record data structure geometry for the given tile baseaddr
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For most tiles there is only one baseaddr, but some like BRAM have multiple
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Notes on multiple block types:
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https://github.com/SymbiFlow/prjxray/issues/145
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'''
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@ -514,6 +543,20 @@ def db_add_bits(database, segments):
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("DSP", "CLB_IO_CLK"): (28, 2, 10),
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("INT_INTERFACE", "CLB_IO_CLK"): (28, 2, None),
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("BRAM_INT_INTERFACE", "CLB_IO_CLK"): (28, 2, None),
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# TODO: These are all guesses copied from CLBLL.
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("RIOI3", "CLB_IO_CLK"): (36, 2, 2),
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("LIOI3", "CLB_IO_CLK"): (36, 2, 2),
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("RIOI3_SING", "CLB_IO_CLK"): (36, 2, 2),
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("LIOI3_SING", "CLB_IO_CLK"): (36, 2, 2),
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("RIOI3_TBYTESRC", "CLB_IO_CLK"): (36, 2, 2),
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("LIOI3_TBYTESRC", "CLB_IO_CLK"): (36, 2, 2),
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("RIOI3_TBYTETERM", "CLB_IO_CLK"): (36, 2, 2),
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("LIOI3_TBYTETERM", "CLB_IO_CLK"): (36, 2, 2),
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("LIOB33", "CLB_IO_CLK"): (36, 2, 2),
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("RIOB33", "CLB_IO_CLK"): (36, 2, 2),
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("LIOB33", "CLB_IO_CLK"): (36, 2, 2),
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("RIOB33_SING", "CLB_IO_CLK"): (36, 2, 2),
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("LIOB33_SING", "CLB_IO_CLK"): (36, 2, 2),
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}.get((nolr(tile_type), block_type), None)
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if entry is None:
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# Other types are rare, not expected to have these
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