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Merge pull request #376 from antmicro/xc7z-fuzz001 

001-part-yaml: Modified script and tools to generate Zynq YAML.
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Tim Ansell 2018-12-24 17:54:42 -08:00 committed by GitHub
parent ca4b7bd309 82c6dad770
commit 4478859b59
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2 changed files with 4 additions and 8 deletions
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6
fuzzers/001-part-yaml/Makefile.specimen
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@ -1,5 +1,5 @@
part.yaml: design.debug.bit
${XRAY_TOOLS_DIR}/gen_part_base_yaml $< > $@
part.yaml: design.perframecrc.bit
${XRAY_TOOLS_DIR}/gen_part_base_yaml $< -f > $@
design.bit debug.perframecrc.bit design.debug.bit: ../generate.tcl
design.bit design.perframecrc.bit: ../generate.tcl
vivado -mode batch -source ../generate.tcl

6
fuzzers/001-part-yaml/generate.tcl
View File

@ -22,13 +22,9 @@ write_checkpoint -force design.dcp
# Write a normal bitstream that will do a singe FDRI write of all the frames.
write_bitstream -force design.bit
# Write a debug bitstream which writes each frame individually followed by
# Write a perframecrc bitstream which writes each frame individually followed by
# the frame address. This shows where there are gaps in the frame address
# space.
set_property BITSTREAM.GENERAL.DEBUGBITSTREAM YES [current_design]
write_bitstream -force design.debug.bit
set_property BITSTREAM.GENERAL.DEBUGBITSTREAM NO [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
write_bitstream -force design.perframecrc.bit
set_property BITSTREAM.GENERAL.PERFRAMECRC NO [current_design]