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101-bram-config: READ/WRITE_WIDTH 

Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster 2018-10-25 10:18:34 -07:00
parent f52c4d0b05
commit 419130a11a
5 changed files with 143 additions and 27 deletions
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3
fuzzers/101-bram-config/Makefile
View File

@ -1,4 +1,5 @@
N := 1
# read/write width is relatively slow to resolve
N := 2
SPECIMENS := $(addprefix build/specimen_,$(shell seq -f '%03.0f' $(N)))
SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))

77
fuzzers/101-bram-config/generate.py
View File

@ -5,19 +5,8 @@ import json
from prjxray.segmaker import Segmaker
from prjxray import verilog
segmk = Segmaker("design.bits", verbose=True)
#segmk.set_def_bt('BLOCK_RAM')
print("Loading tags")
f = open('params.jl', 'r')
f.readline()
for l in f:
j = json.loads(l)
ps = j['params']
assert j['module'] == 'my_RAMB18E1'
site = verilog.unquote(ps['LOC'])
#print('site', site)
def isenv_tags(segmk, ps, site):
# all of these bits are inverted
ks = [
('IS_CLKARDCLK_INVERTED', 'ZINV_CLKARDCLK'),
@ -31,6 +20,9 @@ for l in f:
]
for param, tagname in ks:
segmk.add_site_tag(site, tagname, 1 ^ verilog.parsei(ps[param]))
def bus_tags(segmk, ps, site):
'''
parameter DOA_REG = 1'b0;
parameter DOB_REG = 1'b0;
@ -45,5 +37,62 @@ for l in f:
for i in range(18):
segmk.add_site_tag(site, '%s[%u]' % (param, i), 1 ^ bitstr[i])
segmk.compile()
segmk.write()
def rw_width_tags(segmk, ps, site):
'''
Y0.READ_WIDTH_A
width 001_03 001_04 001_05
1 0 0 0
2 1 0 0
4 0 1 0
9 1 1 0
18 0 0 1
'''
'''
for param, vals in {
"READ_WIDTH_A": [1, 2, 4, 9, 18],
"READ_WIDTH_B": [1, 2, 4, 9, 18],
"WRITE_WIDTH_A": [1, 2, 4, 9, 18],
"WRITE_WIDTH_B": [1, 2, 4, 9, 18],
}.items():
set_val = int(ps[param])
for val in vals:
has = set_val == val
segmk.add_site_tag(site, '%s_B0' % (param), has)
'''
for param in ["READ_WIDTH_A", "READ_WIDTH_B", "WRITE_WIDTH_A",
"WRITE_WIDTH_B"]:
set_val = int(ps[param])
segmk.add_site_tag(site, '%s_B0' % (param), set_val in (2, 9))
segmk.add_site_tag(site, '%s_B1' % (param), set_val in (4, 9))
segmk.add_site_tag(site, '%s_B2' % (param), set_val in (18, ))
def run():
segmk = Segmaker("design.bits", verbose=True)
#segmk.set_def_bt('BLOCK_RAM')
print("Loading tags")
f = open('params.jl', 'r')
f.readline()
for l in f:
j = json.loads(l)
ps = j['params']
assert j['module'] == 'my_RAMB18E1'
site = verilog.unquote(ps['LOC'])
#print('site', site)
# isenv_tags(segmk, ps, site)
# bus_tags(segmk, ps, site)
rw_width_tags(segmk, ps, site)
def bitfilter(frame, bit):
# rw_width_tags() aliasing interconnect on large widths
return frame not in (20, 21)
segmk.compile(bitfilter=bitfilter)
segmk.write()
run()

17
fuzzers/101-bram-config/top.py
View File

@ -99,6 +99,12 @@ for loci, (site_type, site) in enumerate(brams):
"SRVAL_B": vrandbits(18),
"INIT_A": vrandbits(18),
"INIT_B": vrandbits(18),
# Datasheet says 72 is legal, but think its a copy paste error from BRAM36
# also 0 and 36 aren't real sizes
"READ_WIDTH_A": random.choice([1, 2, 4, 9, 18]),
"READ_WIDTH_B": random.choice([1, 2, 4, 9, 18]),
"WRITE_WIDTH_A": random.choice([1, 2, 4, 9, 18]),
"WRITE_WIDTH_B": random.choice([1, 2, 4, 9, 18]),
}
return ('my_RAMB18E1', ports, params)
@ -211,6 +217,10 @@ module my_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout);
parameter INIT_A = 18'b0;
parameter INIT_B = 18'b0;
parameter READ_WIDTH_A = 0;
parameter READ_WIDTH_B = 0;
parameter WRITE_WIDTH_A = 0;
parameter WRITE_WIDTH_B = 0;
''')
print('''\
(* LOC=LOC *)
@ -240,7 +250,12 @@ print(
.SRVAL_A(SRVAL_A),
.SRVAL_B(SRVAL_B),
.INIT_A(INIT_A),
.INIT_B(INIT_B)
.INIT_B(INIT_B),
.READ_WIDTH_A(READ_WIDTH_A),
.READ_WIDTH_B(READ_WIDTH_B),
.WRITE_WIDTH_A(WRITE_WIDTH_A),
.WRITE_WIDTH_B(WRITE_WIDTH_B)
) ram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),

2
minitests/bram_basic/Makefile
View File

@ -37,4 +37,6 @@ build/roi_bram18iy1_bit01.diff:
build/roi_bramis_bit01.diff:
$(MAKE) -f diff.mk OUT_DIFF=build/roi_bramis_bit01.diff PRJL=roi_bramis_bit0 PRJR=roi_bramis_bit1
build/roi_bram18_width.diff:
$(MAKE) -f diff.mk OUT_DIFF=build/roi_bram18_width.diff PRJL=roi_bram18_width_a PRJR=roi_bram18_width_b

71
minitests/bram_basic/top.v
View File

@ -265,6 +265,21 @@ module roi_hck(input clk, input [255:0] din, output [255:0] dout);
endmodule
/******************************************************************************
Misc ROI
******************************************************************************/
module roi_bram18_width_a(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .READ_WIDTH_A(1))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
//"READ_WIDTH_A": [0, 1, 2, 4, 9, 18, 36],
module roi_bram18_width_b(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .READ_WIDTH_A(0))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
/******************************************************************************
Library
******************************************************************************/
@ -280,10 +295,33 @@ for i in xrange(0x40): print '.INIT_%02X(INIT),' % i
*/
module ram_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter INIT0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter RAM_MODE = "TDP";
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
parameter RAM_MODE = "TDP";
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter DOA_REG = 1'b0;
parameter DOB_REG = 1'b0;
parameter SRVAL_A = 18'b0;
parameter SRVAL_B = 18'b0;
parameter INIT_A = 18'b0;
parameter INIT_B = 18'b0;
parameter READ_WIDTH_A = 0;
parameter READ_WIDTH_B = 0;
parameter WRITE_WIDTH_A = 0;
parameter WRITE_WIDTH_B = 0;
(* LOC=LOC *)
RAMB18E1 #(
@ -361,18 +399,29 @@ module ram_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout);
.INIT_3E(INIT),
.INIT_3F(INIT),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_CLKARDCLK_INVERTED(IS_CLKARDCLK_INVERTED),
.IS_CLKBWRCLK_INVERTED(IS_CLKBWRCLK_INVERTED),
.IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(IS_ENBWREN_INVERTED),
.IS_RSTRAMARSTRAM_INVERTED(IS_RSTRAMARSTRAM_INVERTED),
.IS_RSTRAMB_INVERTED(IS_RSTRAMB_INVERTED),
.IS_RSTREGARSTREG_INVERTED(IS_RSTREGARSTREG_INVERTED),
.IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED),
.RAM_MODE(RAM_MODE),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.SIM_DEVICE("VIRTEX6")
.WRITE_MODE_A(WRITE_MODE_A),
.WRITE_MODE_B(WRITE_MODE_B),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
.SRVAL_A(SRVAL_A),
.SRVAL_B(SRVAL_B),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.READ_WIDTH_A(READ_WIDTH_A),
.READ_WIDTH_B(READ_WIDTH_B),
.WRITE_WIDTH_A(WRITE_WIDTH_A),
.WRITE_WIDTH_B(WRITE_WIDTH_B)
) ram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),