mirror of https://github.com/openXC7/prjxray.git
Merge pull request #639 from antmicro/fan-alt-gfan-pips
FAN_ALT.*GFAN pips fuzzer
This commit is contained in:
litghost
GitHub
commit
3f99ef3408
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@ -9,7 +9,8 @@ SEGMATCH_FLAGS=-m 15 -M 45
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endif
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# Driven by int_loop.sh
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ITER := 1
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MAKETODO_FLAGS=--re ".*" --not-endswith ".VCC_WIRE"
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# FAN_ALT.*GFAN pips are left to be solved by a dedicated fuzzer
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MAKETODO_FLAGS=--re "^((?!FAN_ALT[0-9].GFAN).)*$$" --not-endswith ".VCC_WIRE"
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PIPLIST_TCL=$(XRAY_FUZZERS_DIR)/piplist/piplist.tcl
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SPECIMENS := $(addprefix build/$(ITER)/specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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@ -0,0 +1,6 @@
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MAKETODO_FLAGS=--re "^INT_[LR].FAN_ALT.*GFAN"
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GENERATE_FLAGS=--todo ../todo.txt
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N = 48
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SEGMATCH_FLAGS=-m 30 -M 45 -c 2
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include ../int_loop.mk
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@ -0,0 +1,5 @@
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Fuzzer for the ALT_FAN.*GFAN PIPs
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---------------------------------
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This fuzzer solves the ALT_FAN.GFAN PIPs which had collisions with the GFAN PIPs.
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@ -0,0 +1,118 @@
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc build_basic {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog $::env(FUZDIR)/top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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place_design
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route_design
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}
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proc load_todo {} {
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set fp [open "../../todo.txt" r]
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set todo_lines {}
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for {gets $fp line} {$line != ""} {gets $fp line} {
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lappend todo_lines [split $line .]
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}
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close $fp
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return $todo_lines
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}
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proc lremove { l val } {
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set idx [lsearch $l $val]
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return [lreplace $l $idx $idx]
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}
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proc route_todo {} {
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set todo_lines [load_todo]
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set int_l_tiles [filter [pblock_tiles roi] {TYPE == INT_L}]
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set int_r_tiles [filter [pblock_tiles roi] {TYPE == INT_R}]
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for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
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set line [lindex $todo_lines $idx]
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puts ""
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puts ""
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puts "== $idx: $line"
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set tile_type [lindex $line 0]
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set dst_wire [lindex $line 1]
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set src_wire [lindex $line 2]
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set mylut [create_cell -reference LUT1 mylut_$idx]
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set mynet [create_net mynet_$idx]
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connect_net -net $mynet -objects "$mylut/I0 $mylut/O"
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set tries 0
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while {1} {
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incr tries
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puts ""
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puts "$mynet: try $tries"
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if {$tile_type == "INT_L"} {
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set tile [randsample_list 1 $int_l_tiles]
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set int_l_tiles [lremove $int_l_tiles $tile]
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set other_tile [randsample_list 1 $int_r_tiles]
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set int_r_tiles [lremove $int_r_tiles $other_tile]
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} elseif {$tile_type == "INT_R"} {
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set tile [randsample_list 1 $int_r_tiles]
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set int_r_tiles [lremove $int_r_tiles $tile]
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set other_tile [randsample_list 1 $int_l_tiles]
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set int_l_tiles [lremove $int_l_tiles $other_tile]
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} else {
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error "Bad tile type $tile_type"
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}
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puts "PIP Tile: $tile, LUT tile: $other_tile"
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set driver_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
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-of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
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puts "LUT site: $driver_site"
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set_property -dict "LOC $driver_site BEL A6LUT" $mylut
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set route_list "$tile/$src_wire $tile/$dst_wire"
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puts "route_via $mynet $route_list"
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set rc [route_via $mynet $route_list 0]
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if {$rc != 0} {
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break
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}
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puts "WARNING: failed to route net"
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write_checkpoint -force route_todo_$idx.$tries.fail.dcp
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puts "Rolling back route"
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set_property is_route_fixed 0 $mynet
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set_property is_bel_fixed 0 $mylut
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set_property is_loc_fixed 1 $mylut
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route_design -unroute -nets $mynet
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# sometimes it gets stuck in specific orientations
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if {$tries >= 3} {
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puts "WARNING: failed to route net after $tries tries"
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break
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}
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}
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}
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}
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proc run {} {
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build_basic
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route_todo
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_pip_txtdata design.txt
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}
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run
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@ -0,0 +1,3 @@
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module top (input i, output o);
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assign o = i;
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endmodule
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@ -74,8 +74,9 @@ $(eval $(call fuzzer,050-pip-seed,005-tilegrid))
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$(eval $(call fuzzer,051-pip-imuxlout-bypalts,050-pip-seed))
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$(eval $(call fuzzer,052-pip-clkin,050-pip-seed))
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$(eval $(call fuzzer,053-pip-ctrlin,050-pip-seed))
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$(eval $(call fuzzer,054-pip-fan-alt,050-pip-seed))
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$(eval $(call fuzzer,055-pip-gnd,050-pip-seed))
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$(eval $(call fuzzer,056-pip-rem,051-pip-imuxlout-bypalts 052-pip-clkin 053-pip-ctrlin 055-pip-gnd))
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$(eval $(call fuzzer,056-pip-rem,051-pip-imuxlout-bypalts 052-pip-clkin 053-pip-ctrlin 054-pip-fan-alt 055-pip-gnd))
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$(eval $(call fuzzer,057-pip-bi,056-pip-rem))
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ifneq ($(QUICK),Y)
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$(eval $(call fuzzer,058-pip-hclk,056-pip-rem))
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