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Add small fixes to the database documentation

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Signed-off-by: Tomasz Michalak <[email protected]>
This commit is contained in:
Tomasz Michalak
2020-05-19 14:14:29 +02:00
committed by Robert Winkler
parent e8ff146443
commit 39813be4cb
11 changed files with 106 additions and 150 deletions
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docs/dev_database/common/index.rst
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@@ -1,15 +1,15 @@
=============================
Files Common for Architecture
=============================
=====================
Common database files
=====================
This section contains a description of :term:`database <database>` files
that are common for a whole chip architecture.
that are common for all Xilinx series 7 chip architectures.
.. toctree::
:maxdepth: 2
mask
ppips
segbits
site_type
tile_type
ppips
mask
docs/dev_database/common/mask.rst
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@@ -2,8 +2,8 @@
mask files
==========
The *mask files* are generated for every FPGA :term:`tile <tile>` type. They store
the information, which bits in the bitstream can configure the given
The *mask files* are generated for every FPGA :term:`tile <tile>` type.
They store the information which bits in the bitstream can configure the given
:term:`tile <tile>` type.
Naming convention
@@ -19,11 +19,11 @@ which produced the :term:`database <database>` file. This file is optional.
Every :term:`tile <tile>` is configured at least by one of three configurational
buses mentioned in the :doc:`Configuration Section <../../architecture/configuration>`.
The default bus is called ``CLB_IO_CLK``. If the :term:`tile <tile>` can also be
configured by another bus it has additional ``mask_<tile>.<bus_name>.db``
The default bus is called ``CLB_IO_CLK``.
If the :term:`tile <tile>` can also be configured by another bus, it has an additional ``mask_<tile>.<bus_name>.db``
related to that bus.
In example:
For example:
- ``mask_dsp_r.db``
- ``mask_bram_l.db`` (configured with default ``CLB_IO_CLK`` bus)
@@ -32,12 +32,12 @@ In example:
File format
-----------
The file consist of the records that describes configuration bits for
The file consists of records that describe the configuration bits for
the particular :term:`tile <tile>` type. Each entry inside the file is of the form::
bit <frame_address_offset>_<bit_position>
This means that the :term:`tile <tile>` can be configured by bit located in the
This means that the :term:`tile <tile>` can be configured by a bit located in the
:term:`frame <frame>` at the address ``<base_frame_addr> + <frame_address_offset>``,
at position ``<tile_offset> + <bit_position>``. Information about ``<base_frame_address>``
and ``<tile_offset>`` can be taken from part specific ``tilegrid.json`` file.
@@ -45,13 +45,13 @@ and ``<tile_offset>`` can be taken from part specific ``tilegrid.json`` file.
Example
-------
Below there is a part of artix7 ``mask_clbll_l.db`` file describing FPGA *CLBLL*
Below there is a part of artix7 ``mask_clbll_l.db`` file describing a FPGA *CLBLL*
:term:`tile <tile>`::
<...>
bit 00_61
bit 00_62
bit_00_63
bit 00_63
bit 01_00
bit 01_01
bit 01_02
@@ -62,7 +62,7 @@ configured by the bit located in the :term:`frame <frame>` at the address
``<base_frame_address> + 0x01``, at position ``<tile_offset> + 0x2``.
The ``tilegrid.json`` is a file specific to a given chip package.
For *xc7a35tcpg236-1* we can find exemplary *CLBLL_L* entry::
For *xc7a35tcpg236-1* we can find an exemplary *CLBLL_L* entry::
"CLBLL_L_X2Y0": {
"bits": {
docs/dev_database/common/ppips.rst
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@@ -5,8 +5,8 @@ ppips files
The *ppips files* are generated for every FPGA :term:`tile <tile>` type.
They store the information about the pseudo-PIPs, inside the tile.
Programable Interconnect point (:term:`PIP <pip>`) is a connection inside the
:term:`tile <tile>` that can be enabled or disabled. Pseudo PIPs appears as standard
Programable Interconnect Point (:term:`PIP <pip>`) is a connection inside the
:term:`tile <tile>` that can be enabled or disabled. Pseudo PIPs appear as standard
:term:`PIPs <pip>` in the Vivado tool, but they do not have actual configuration
bit pattern (they are not configurable).
@@ -17,7 +17,7 @@ The naming scheme for the PPIPs files is the following::
ppips_<tile>.db
In example:
For example:
- ``ppips_dsp_l.db``
- ``ppips_clbll_l.db``
@@ -57,6 +57,5 @@ Below there is a part of artix7 ``ppips_clbll_l.db`` file::
CLBLL_L.CLBLL_L_B.CLBLL_L_B4 hint
<...>
The ``<ppip_location>`` name is arbitrary. However, we named them in the convention
similar to the Vivado tool, which allows us to identify them quickly and provides
suggestions about their role in the FPGA chip.
The ``<ppip_location>`` name is arbitrary. However, the naming convention is
similar to the one in the Vivado tool, which allows for quick identification of their role in the FPGA chip.
docs/dev_database/common/segbits.rst
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@@ -35,7 +35,7 @@ Exemplary files:
File format
-----------
The file consists of the lines, containing the information about the feature
The file consists of lines containing the information about the feature
and the list of bits that should be enabled/disabled to provide the feature's
functionality::
@@ -49,10 +49,8 @@ where:
mark in front of it, that means it should be set to **0** for feature configuration,
otherwise it should be set to **1**.
The names of the features are arbitrary. However, we named them in the convention,
which allows us to identify them quickly and provides suggestions
about the functionality that they provide. The feature names are used in the
fasm files generation.
The names of the features are arbitrary. However, the naming convention allows for quick identifaction of the functionality that is being configured.
The feature names are used during the generation of the :doc:`FASM <../../../../fasm/docs/specification>` file.
Feature naming conventions
@@ -79,14 +77,14 @@ For example::
CLBLL_L.SLICEL_X0.ALUT.INIT[00]
This entry documents the initialization bits the *LSB LUT* for the *ALUT* in
This entry documents the initialization bits of the *LSB LUT* for the *ALUT* in
the *SLICEL_X0* within a *CLBLL_L tile.*
Example
-------
Below there is a part of ``segbits_liob33_l.db`` file for the *artix7*
architecture. The file describes *CLBLL* :term:`tile <tile>`::
Below there is a part of the ``segbits_liob33_l.db`` file for the *artix7*
architecture. The file describes the *CLBLL* :term:`tile <tile>`::
<...>
LIOB33.IOB_Y0.IBUFDISABLE.I 38_82
@@ -102,15 +100,15 @@ architecture. The file describes *CLBLL* :term:`tile <tile>`::
LIOB33.IOB_Y0.PULLTYPE.PULLUP !38_92 38_94 39_93
<...>
In example, the line::
For example, the line::
LIOB33.IOB_Y0.PULLTYPE.PULLUP !38_92 38_94 39_93
means that the feature ``LIOB33.IOB_Y0.PULLTYPE.PULLUP`` will be set by clearing
bit ``!38_92`` and setting bits ``38_94`` and ``39_93``.
Generally, ``<feature>`` name is connected with its functionality.
In example, ``LIOB33.IOB_Y0.PULLTYPE.PULLUP`` means that in the LIOB33
Generally, the ``<feature>`` name is linked with its functionality.
For example, ``LIOB33.IOB_Y0.PULLTYPE.PULLUP`` means that in the LIOB33
:term:`tile <tile>`,
in IOB_Y0 site the *pull type* will be set to *PULLUP*.
This simply means that all pins belonging to this particular IOB
docs/dev_database/common/site_type.rst
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@@ -13,7 +13,7 @@ The naming scheme for the :term:`site <site>` type files is the following::
site_type_<site>.json
Exemplary files:
Example files:
- ``site_type_IDELAYE2.json``
- ``site_type_PLLE2_ADV.json``
docs/dev_database/common/tile_type.rst
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@@ -4,7 +4,7 @@ tile_type files
The *tile_type files* are generated for every FPGA :term:`tile <tile>`
type. They store the information about the :term:`tile <tile>` configuration,
it's :term:`PIPs <pip>`, :term:`sites <site>`, wires and their properties.
its :term:`PIPs <pip>`, :term:`sites <site>`, wires and their properties.
Naming convention
-----------------
@@ -13,7 +13,7 @@ The naming scheme for the segbits files is the following::
tile_type_<tile>.json
Exemplary files:
Example files:
- ``tile_type_INT_L.json``
- ``tile_type_BRAM_L.json``
@@ -86,18 +86,18 @@ The :term:`tile <tile>` type files are JSON files with the following shape::
^^^^^^^^^^^^^^
The "pips" section describes all :term:`PIPs <pip>` in the :term:`tile <tile>`.
Every :term:`PIP <pip>` has it's name - ``"<PIN_NAME>"`` and may be
Every :term:`PIP <pip>` has its name - ``"<PIN_NAME>"`` and may be
characterized by the following attributes:
- ``"can_invert"`` - takes a value which can be either **1** or **0**.
- ``can_invert`` - takes a value which can be either **1** or **0**.
It defines whether the :term:`PIP <pip>` has an inverter on it's output or not.
- ``dst_to_src"`` - information about the connection in the direction
- ``dst_to_src`` - information about the connection in the direction
from destination to source. It describes the following properties of the connection:
- ``"delay"`` - four-element list, which contain information about the delays.
- ``"in_cap"`` - the input capacitance of the :term:`PIP <pip>`
- ``"res"`` - the resistance of the :term:`PIP <pip>`.
- ``delay`` - four-element list, which contain information about the delays.
- ``in_cap`` - the input capacitance of the :term:`PIP <pip>`
- ``res`` - the resistance of the :term:`PIP <pip>`.
- ``dst_wire`` - the destination wire name
@@ -118,37 +118,37 @@ characterized by the following attributes:
The "sites" section describes all :term:`sites <site>` in the :term:`tile <tile>`.
Every :term:`site <site>` may be characterized by the following attributes:
- ``"name"`` - location in the :term:`tile <tile>` grid
- ``name`` - location in the :term:`tile <tile>` grid
- ``"prefix"`` - the type of the :term:`site <site>`
- ``prefix`` - the type of the :term:`site <site>`
- ``"site_pins"`` - describes the pins that belong to the :term:`site <site>`.
Every pin has it's name - ``"<PIN_NAME>"`` and may be described
- ``site_pins`` - describes the pins that belong to the :term:`site <site>`.
Every pin has it's name - ``<PIN_NAME>`` and may be described
by the following attributes:
- ``"cap"`` - pin capacitance
- ``"delay"`` - pin delay
- ``"wire"`` - wire associated with the pin
- ``cap`` - pin capacitance
- ``delay`` - pin delay
- ``wire`` - wire associated with the pin
- ``"type"`` - indicates the type of the site
- ``type`` - indicates the type of the site
- ``"x_coord"`` - describes *x* coordinate of the site position inside the tile
- ``x_coord`` - describes *x* coordinate of the site position inside the tile
- ``y_coord"`` - describes the *y* coordinate of the site position inside the tile
- ``y_coord`` - describes the *y* coordinate of the site position inside the tile
"wires" section
^^^^^^^^^^^^^^^
The "wires" section describes the wires located in the :term:`tile <tile>`.
Every wire has it's name - ``"<WIRE_NAME>"`` and may be characterized
Every wire has it's name - ``<WIRE_NAME>`` and may be characterized
by the following attributes:
- ``"cap"`` - wire capacitance
- ``"res"`` - wire resistance
- ``cap`` - wire capacitance
- ``res`` - wire resistance
Other
^^^^^
- ``"tile_type"`` - indicates the type of the tile
- ``tile_type`` - indicates the type of the tile
Example