luke
/
prjxray
mirror of https://github.com/openXC7/prjxray.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fixed the LiteX generated SoC to be Linux capable 

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-06-17 13:45:11 +02:00
parent 4798c08ad8
commit 3783e7b2e3
10 changed files with 18394 additions and 13899 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
minitests/litex/README.md Normal file
View File

@ -0,0 +1,11 @@
# LiteX minitest
This folder contains a minitest for a Linux capable LiteX SoC for Arty board.
There are two variants: for Vivado only flow and for Yosys+Vivado flow. In order to run one of them enter the specific directory and run `make`.
The SoC "gateware" files were generated using the command:
```
./arty.py --cpu-type vexriscv --cpu-variant linux --with-ethernet --no-compile-software --no-compile-gateware
```

5760
minitests/litex/src.vivado/VexRiscv.v
View File

File diff suppressed because it is too large Load Diff

7789
minitests/litex/src.vivado/VexRiscv_Linux.v Normal file
View File

File diff suppressed because it is too large Load Diff

4
minitests/litex/src.vivado/top.tcl
View File

@ -1,7 +1,7 @@
create_project -force -name top -part xc7a35ticsg324-1L create_project -force -name top -part xc7a35ticsg324-1L
add_files {../top.v} add_files {../top.v}
add_files {../VexRiscv.v} add_files {../VexRiscv_Linux.v}
read_xdc {../top.xdc} read_xdc ../top.xdc
synth_design -top top -part xc7a35ticsg324-1L synth_design -top top -part xc7a35ticsg324-1L
report_timing_summary -file top_timing_synth.rpt report_timing_summary -file top_timing_synth.rpt
report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt

2587
minitests/litex/src.vivado/top.v
View File

File diff suppressed because it is too large Load Diff

5760
minitests/litex/src.yosys/VexRiscv.v
View File

File diff suppressed because it is too large Load Diff

7789
minitests/litex/src.yosys/VexRiscv_Linux.v Normal file
View File

File diff suppressed because it is too large Load Diff

2
minitests/litex/src.yosys/synth.ys
View File

@ -1,3 +1,3 @@
read_verilog top.v read_verilog top.v
read_verilog VexRiscv.v read_verilog VexRiscv_Linux.v
synth_xilinx -edif top.edif synth_xilinx -edif top.edif

2587
minitests/litex/src.yosys/top.v
View File

File diff suppressed because it is too large Load Diff