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docs: Fix some formatting 

Signed-off-by: Michael Gielda <mgielda@antmicro.com>
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Michael Gielda 2019-04-05 08:21:39 -07:00 committed by GitHub
parent 78c47ab82b
commit 3333a14e15
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1 changed files with 1 additions and 3 deletions
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docs/architecture/bitstream_format.rst
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@ -10,20 +10,19 @@ Bitstream format
* All data before 32-bit synchronization word (0xAA995566) is ignored by
configuration state machine
* Packetized format used to perform register reads/writes
* Three packet header types
* Type 0 packets exist only when performing zero-fill between rows
* Type 1 used for writes up to 4096 words
* Type 2 expands word count field to 27 bits by omitting register address
* Type 2 must always be proceeded by Type 1 which sets register address
* NOP packets are used for inserting required delays
* Most registers only accept 1 word of data
* Allowed register operations depends on interface used to send packets
* Writing LOUT via JTAG is treated as a bad command
* Single-frame FDRI writes via JTAG fail
* CRC
* Calculated automatically from writes: register address and data written
@ -32,7 +31,6 @@ Bitstream format
* Writes to CRC register can be safely removed from a bitstream
* Alternatively, replace with write to command register to reset calculated
CRC value
* Xilinx BIT header
* Additional information about how bitstream was generated