mirror of https://github.com/openXC7/prjxray.git
Run make format.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
3d70606d79
commit
3232ae3edc
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@ -17,6 +17,7 @@ process.
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"""
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import argparse
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def main():
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parser = argparse.ArgumentParser("Form ZDB groups for BUFG.")
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@ -56,11 +57,13 @@ def main():
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assert zero_feature is not None, dst
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print('{bits},{type}.{dst}.{src}'.format(
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bits=' '.join(sorted(bits)),
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type='CLK_BUFG',
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dst=dst,
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src=zero_feature))
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print(
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'{bits},{type}.{dst}.{src}'.format(
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bits=' '.join(sorted(bits)),
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type='CLK_BUFG',
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dst=dst,
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src=zero_feature))
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if __name__ == "__main__":
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main()
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@ -4,12 +4,14 @@ from prjxray.segmaker import Segmaker
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import os
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import os.path
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def bitfilter(frame, word):
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if frame < 26:
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return False
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return True
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def main():
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segmk = Segmaker("design.bits")
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@ -17,7 +19,8 @@ def main():
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pipdata = {}
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ignpip = set()
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build', 'clk_bufg', 'clk_bufg_bot_r.txt')) as f:
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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'clk_bufg', 'clk_bufg_bot_r.txt')) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if tile_type not in pipdata:
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@ -25,7 +28,8 @@ def main():
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pipdata[tile_type].append((src, dst))
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build', 'clk_bufg', 'clk_bufg_top_r.txt')) as f:
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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'clk_bufg', 'clk_bufg_top_r.txt')) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if tile_type not in pipdata:
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@ -86,5 +90,6 @@ def main():
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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if __name__ == "__main__":
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main()
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@ -95,7 +95,6 @@ class ClockSources(object):
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return source
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def main():
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"""
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BUFG's can be driven from:
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@ -105,7 +104,8 @@ def main():
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"""
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print('''
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print(
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'''
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module top();
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(* KEEP, DONT_TOUCH *)
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LUT6 dummy();
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@ -129,7 +129,6 @@ module top();
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if site_type == desired_site_type:
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yield tile_name, site
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for _, site in gen_sites('MMCME2_ADV'):
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mmcm_clocks = [
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'mmcm_clock_{site}_{idx}'.format(site=site, idx=idx)
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@ -176,7 +175,7 @@ module top();
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))
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for _, site in sorted(gen_sites("BUFGCTRL"),
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key=lambda x: BUFGCTRL_XY_FUN(x[1])):
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key=lambda x: BUFGCTRL_XY_FUN(x[1])):
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print(
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"""
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wire O_{site};
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@ -188,9 +187,11 @@ module top();
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wire I0_{site};
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wire CE1_{site};
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wire CE0_{site};
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""".format(site=site), file=wires)
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""".format(site=site),
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file=wires)
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print("""
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print(
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"""
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFGCTRL bufg_{site} (
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.O(O_{site}),
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@ -203,8 +204,8 @@ module top();
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.CE1(CE1_{site}),
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.CE0(CE0_{site})
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);
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""".format(site=site), file=bufgs)
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""".format(site=site),
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file=bufgs)
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""" BUFG clock sources:
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2 from interconnect
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@ -214,11 +215,11 @@ module top();
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"""
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CLOCK_CHOICES = (
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'LUT',
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'BUFG_+1',
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'BUFG_-1',
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'CASCADE',
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)
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'LUT',
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'BUFG_+1',
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'BUFG_-1',
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'CASCADE',
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)
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def find_bufg_cmt(tile):
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if '_BOT_' in tile:
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@ -231,7 +232,8 @@ module top();
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offset = 1
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while True:
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gridinfo = grid.gridinfo_at_loc((loc.grid_x, loc.grid_y+offset*inc))
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gridinfo = grid.gridinfo_at_loc(
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(loc.grid_x, loc.grid_y + offset * inc))
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if gridinfo.tile_type.startswith('CLK_HROW_'):
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return site_to_cmt[list(gridinfo.sites.keys())[0]]
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@ -244,7 +246,7 @@ module top();
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x, y = BUFGCTRL_XY_FUN(site)
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target_y = y + 1
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max_y = ((y // 16) + 1)*16
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max_y = ((y // 16) + 1) * 16
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if target_y >= max_y:
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target_y -= 16
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@ -254,7 +256,7 @@ module top();
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x, y = BUFGCTRL_XY_FUN(site)
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target_y = y - 1
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min_y = (y // 16)*16
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min_y = (y // 16) * 16
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if target_y < min_y:
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target_y += 16
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@ -267,20 +269,27 @@ module top();
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assert False, source_type
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for tile, site in sorted(gen_sites("BUFGCTRL"),
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key=lambda x: BUFGCTRL_XY_FUN(x[1])):
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key=lambda x: BUFGCTRL_XY_FUN(x[1])):
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if random.randint(0, 1):
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print("""
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print(
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"""
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assign I0_{site} = {i0_net};""".format(
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site=site,
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i0_net=get_clock_net(tile, site, random.choice(CLOCK_CHOICES))), file=bufgs)
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site=site,
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i0_net=get_clock_net(
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tile, site, random.choice(CLOCK_CHOICES))),
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file=bufgs)
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if random.randint(0, 1):
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print("""
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print(
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"""
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assign I1_{site} = {i1_net};""".format(
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site=site,
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i1_net = get_clock_net(tile, site, random.choice(CLOCK_CHOICES))), file=bufgs)
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site=site,
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i1_net=get_clock_net(
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tile, site, random.choice(CLOCK_CHOICES))),
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file=bufgs)
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print("""
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print(
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"""
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assign S0_{site} = {s0_net};
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assign S1_{site} = {s1_net};
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assign IGNORE0_{site} = {ignore0_net};
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@ -288,14 +297,15 @@ module top();
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assign CE0_{site} = {ce0_net};
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assign CE1_{site} = {ce1_net};
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""".format(
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site=site,
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s0_net=luts.get_next_output_net(),
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s1_net=luts.get_next_output_net(),
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ignore0_net=luts.get_next_output_net(),
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ignore1_net=luts.get_next_output_net(),
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ce0_net=luts.get_next_output_net(),
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ce1_net=luts.get_next_output_net(),
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), file=bufgs)
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site=site,
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s0_net=luts.get_next_output_net(),
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s1_net=luts.get_next_output_net(),
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ignore0_net=luts.get_next_output_net(),
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ignore1_net=luts.get_next_output_net(),
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ce0_net=luts.get_next_output_net(),
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ce1_net=luts.get_next_output_net(),
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),
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file=bufgs)
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for l in luts.create_wires_and_luts():
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print(l)
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@ -306,18 +316,19 @@ module top();
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itr = iter(gen_sites('BUFHCE'))
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for tile, site in sorted(gen_sites("BUFGCTRL"),
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key=lambda x: BUFGCTRL_XY_FUN(x[1])):
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key=lambda x: BUFGCTRL_XY_FUN(x[1])):
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if random.randint(0, 1):
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_, bufhce_site = next(itr)
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print("""
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print(
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"""
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(* KEEP, DONT_TOUCH, LOC = "{bufhce_site}" *)
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BUFHCE bufhce_{bufhce_site} (
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.I(O_{site})
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);""".format(
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site=site,
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bufhce_site=bufhce_site,
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))
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site=site,
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bufhce_site=bufhce_site,
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))
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print("endmodule")
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