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docs: fixed some READMEs and removed empty .md file generation 

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi 2019-09-25 09:54:28 +02:00
parent f1fd0c975a
commit 2fab112c71
4 changed files with 6 additions and 12 deletions
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6
docs/Makefile
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@ -35,9 +35,6 @@ fuzzers-links:
ln -s $$i/README.md $${n}.md; \ ln -s $$i/README.md $${n}.md; \
else \ else \
echo "Missing $$i/README.md"; \ echo "Missing $$i/README.md"; \
echo "# $$n Fuzzer" > $${n}.md; \
echo "" >> $${n}.md; \
echo "Missing README.md!" >> $${n}.md; \
fi; \ fi; \
done done
@ -55,9 +52,6 @@ minitests-links:
ln -s $$i/README.md $${n}.md; \ ln -s $$i/README.md $${n}.md; \
else \ else \
echo "Missing $$i/README.md"; \ echo "Missing $$i/README.md"; \
echo "# $$n Minitest" > $${n}.md; \
echo "" >> $${n}.md; \
echo "Missing README.md!" >> $${n}.md; \
fi; \ fi; \
done done

4
minitests/partial_reconfig_flow/README.md
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@ -10,7 +10,7 @@ harness into a bitstream with fasm2frame and xc7patch. Since writting FASM is
rather tedious, rules are provided to convert Verilog ROI designs into FASM via rather tedious, rules are provided to convert Verilog ROI designs into FASM via
Vivado. Vivado.
# Usage ## Usage
make rules are provided for generating each step of the process so that make rules are provided for generating each step of the process so that
intermediate forms can be analyzed. Assuming you have a .fasm file, invoking intermediate forms can be analyzed. Assuming you have a .fasm file, invoking
@ -20,7 +20,7 @@ the %\_hand\_crafted.bit rule will generate a merged bitstream:
make foo.hand\_crafted.bit # reads foo.fasm make foo.hand\_crafted.bit # reads foo.fasm
``` ```
# Using Vivado to generate .fasm ## Using Vivado to generate .fasm
Vivado's Partial Reconfiguration flow can be used to synthesize and implement a Vivado's Partial Reconfiguration flow can be used to synthesize and implement a
ROI design that is then converted to .fasm. Write a Verilog module ROI design that is then converted to .fasm. Write a Verilog module

4
minitests/roi_harness/README.md
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@ -81,7 +81,7 @@ The following configurations are supported;
# 125 MHz CLK onboard # 125 MHz CLK onboard
K17 K17
# Quickstart ## Quickstart
``` ```
source settings/artix7.sh source settings/artix7.sh
@ -91,7 +91,7 @@ make clean
make copy make copy
``` ```
# How it works ## How it works
Basic idea: Basic idea:
- LOC LUTs in the ROI to terminate input and output routing - LOC LUTs in the ROI to terminate input and output routing

4
minitests/timing/README.md
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@ -13,14 +13,14 @@ comparision between the reduced model implemented in prjxray and the Vivado
timing results. timing results.
Model quality Model quality
============= -------------
The prjxray timing handles most nets +/- 1.5% delay. The large exception to The prjxray timing handles most nets +/- 1.5% delay. The large exception to
this is clock nets, which appear to use a table lookup that is not understood this is clock nets, which appear to use a table lookup that is not understood
at this time. at this time.
Running the model Running the model
================= -----------------
The provided Makefile will by default compile all examples. It a specific design The provided Makefile will by default compile all examples. It a specific design
family is desired, the family name can be provided. If a specific design within family is desired, the family name can be provided. If a specific design within