Add nodes_wires_list minitests

Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>

minitests/nodes_wires_list/.gitignore

@@ -0,0 +1,6 @@
+/.Xil
+/design/
+/design.bit
+/design.dcp
+/vivado*
+/nodes_wires_list.txt

minitests/nodes_wires_list/runme.tcl

@@ -0,0 +1,30 @@
+create_project -force -part $::env(XRAY_PART) design design
+
+read_verilog top.v
+synth_design -top top
+
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
+
+create_pblock roi
+resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+place_design
+route_design
+
+write_checkpoint -force design.dcp
+write_bitstream -force design.bit
+
+source ../../utils/utils.tcl
+
+set fp [open "nodes_wires_list.txt" w]
+foreach node [lsort [get_nodes -of_objects [pblock_tiles roi]]] {
+	set wires [lsort [get_wires -of_objects $node]]
+	if {$wires != $node} {puts $fp $wires}
+}
+close $fp
+

minitests/nodes_wires_list/top.v

@@ -0,0 +1,3 @@
+module top (input i, output o);
+	assign o = i;
+endmodule

utils/utils.tcl

@@ -54,6 +54,12 @@ proc randplace_pblock {num pblock} {
 	}
 }
 
+proc pblock_tiles {pblock} {
+	set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]]
+	set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]]
+	return [get_tiles "$clb_tiles $int_tiles"]
+}
+
 proc putl {lst} {
 	foreach line $lst {puts $line}
 }