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Added more bits to dbf, added varying of inverters for ISERDES 

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-07-26 16:05:36 +02:00
parent 3ad85e0e49
commit 2b87eec19a
4 changed files with 22 additions and 35 deletions
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4
fuzzers/035b-iob-iserdes/bits.dbf
View File

@ -2,5 +2,5 @@
26_99 27_98 ,IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE
26_29 27_28 ,IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE
26_29 27_28 ,IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE
26_101 26_107 26_109 26_111 26_115 26_117 26_121 27_108 27_110 27_112
26_15 26_17 26_19 27_6 27_10 27_12 27_16 27_18 27_20 27_26
26_101 26_107 26_109 26_111 26_115 26_117 26_121 27_108 27_110 27_112 28_126 29_123 29_125
26_15 26_17 26_19 27_6 27_10 27_12 27_16 27_18 27_20 27_26 28_2 28_4 29_1

34
fuzzers/035b-iob-iserdes/generate.py
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@ -66,8 +66,8 @@ for param_list in data:
for i in range(1, 4 + 1):
segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0)
segmk.add_site_tag(loc, "ISERDES.IS_CLKB_INVERTED", 1)
segmk.add_site_tag(loc, "ISERDES.IS_CLK_INVERTED", 0)
# segmk.add_site_tag(loc, "ISERDES.IS_CLKB_INVERTED", 0)
# segmk.add_site_tag(loc, "ISERDES.IS_CLK_INVERTED", 1)
segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0)
segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0)
@ -79,10 +79,6 @@ for param_list in data:
segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0)
# segmk.add_site_tag(loc, "CE1USED", 0)
# segmk.add_site_tag(loc, "IFF.SUSED", 0)
# segmk.add_site_tag(loc, "IFF.RUSED", 0)
# Site used as ISERDESE2
elif verilog.unquote(params["BEL_TYPE"]) == "ISERDESE2":
@ -144,14 +140,14 @@ for param_list in data:
if "IS_D_INVERTED" in params:
segmk.add_site_tag(loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0))
if "IS_CLKB_INVERTED" in params:
segmk.add_site_tag(
loc, "ISERDES.IS_CLKB_INVERTED",
params["IS_CLKB_INVERTED"])
# if "IS_CLKB_INVERTED" in params:
# segmk.add_site_tag(
# loc, "ISERDES.IS_CLKB_INVERTED",
# params["IS_CLKB_INVERTED"])
if "IS_CLK_INVERTED" in params:
segmk.add_site_tag(
loc, "ISERDES.IS_CLK_INVERTED", params["IS_CLK_INVERTED"])
# if "IS_CLK_INVERTED" in params:
# segmk.add_site_tag(
# loc, "ISERDES.IS_CLK_INVERTED", params["IS_CLK_INVERTED"])
if "DYN_CLKDIV_INV_EN" in params:
value = verilog.unquote(params["DYN_CLKDIV_INV_EN"])
@ -211,10 +207,6 @@ for param_list in data:
loc, "IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED",
int(value == "SAME_EDGE_PIPELINED"))
# A test
segmk.add_site_tag(loc, "ISERDES.IS_CLKB_INVERTED", 1)
segmk.add_site_tag(loc, "ISERDES.IS_CLK_INVERTED", 0)
if "SRTYPE" in params:
value = verilog.unquote(params["SRTYPE"])
if value == "ASYNC":
@ -240,14 +232,6 @@ for param_list in data:
segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0)
segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1)
# if "CE1USED" in params:
# segmk.add_site_tag(loc, "CE1USED", params["CE1USED"])
# if "SR_MODE" in params:
# value = verilog.unquote(params["SR_MODE"])
# segmk.add_site_tag(loc, "IFF.SUSED", int(value == "SET"))
# segmk.add_site_tag(loc, "IFF.RUSED", int(value == "RST"))
segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1)
segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0)

2
fuzzers/035b-iob-iserdes/generate.tcl
View File

@ -1,3 +1,5 @@
set_param general.maxThreads 1
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top

17
fuzzers/035b-iob-iserdes/top.py
View File

@ -74,17 +74,18 @@ def gen_iserdes(loc):
"SRVAL_Q3": random.randint(0, 1),
"SRVAL_Q4": random.randint(0, 1),
"NUM_CE": random.randint(1, 2),
# The following one shows negative correlation (0 - not inverted)
"IS_D_INVERTED": random.randint(0, 1),
# No bits were found for parameters below
#"IS_OCLKB_INVERTED": random.randint(0, 1),
#"IS_OCLK_INVERTED": random.randint(0, 1),
#"IS_CLKDIVP_INVERTED": random.randint(0, 1),
#"IS_CLKDIV_INVERTED": random.randint(0, 1),
#"IS_CLKB_INVERTED":
#random.randint(0, 1),
#"IS_CLK_INVERTED":
#random.randint(0, 1),
"IS_OCLKB_INVERTED": random.randint(0, 1),
"IS_OCLK_INVERTED": random.randint(0, 1),
"IS_CLKDIVP_INVERTED": random.randint(0, 1),
"IS_CLKDIV_INVERTED": random.randint(0, 1),
"IS_CLKB_INVERTED": random.randint(0, 1),
"IS_CLK_INVERTED": random.randint(0, 1),
"DYN_CLKDIV_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])),
"DYN_CLK_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])),
"IOBDELAY": verilog.quote(