mirror of https://github.com/openXC7/prjxray.git
Merge pull request #810 from mithro/import-wiki
Fixing issues from wiki import
This commit is contained in:
Tim Ansell
GitHub
commit
27bba88fc8
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@ -25,13 +25,13 @@ Glossary
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* Basic BEL - A logic unit which does things.
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* Routing BEL - A unit which is statically configured at routing time.
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Bitstream
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Binary data that is directly loaded into an :term:`FPGA` to perform
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configuration. Contains configuration :term:`frames <frame>` as well as
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programming sequences and other commands required to load and activate same.
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Block RAM
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Block RAM is inbuilt, configurable memory on an :term:`FPGA`, able to store
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more data than the :term:`flip flops <ff>`. The block RAM can function as
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@ -42,7 +42,7 @@ Glossary
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CFA
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A carry or fast adder (CFA) is a logic element on the :term:`FPGA` that
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performs fast arithmetic operations.
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Clock
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A clock is a square-wave timing signal (50% on, 50% off) generated by an
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external oscillator and passed into the :term:`FPGA`. The clock frequency
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@ -62,7 +62,7 @@ Glossary
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part of a :term:`horizontal clock row` to one side of the global
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:term:`clock spine`. The term also often refers to the
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:term:`tiles <tile>` that are associated with these clocks.
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Clock region
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Portion of a device including up to 12 :term:`clock domains <clock domain>`.
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A clock region is situated to the left or right of the global clock spine,
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@ -90,7 +90,7 @@ Glossary
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Fabric sub region
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FSR
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Another name for :term:`clock region`.
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Flip flop
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FF
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A flip flop (FF) is a logic element on the :term:`FPGA` that stores state.
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@ -117,7 +117,7 @@ Glossary
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For example, in a logic column with 50 tiles, the first tile is configured
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with the first two words in each frame, the next tile with the next two
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words, and so on.
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Frame base address
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The first configuration frame address for a :term:`column`. A frame base
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address has always the 7 LSB bits cleared.
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@ -135,7 +135,7 @@ Glossary
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You use a hardware definition language (HDL) to describe the behavior of an
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electronic circuit. Popular HDLs include Verilog (inspired by C) and VHDL
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(inspired by Ada).
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Horizontal clock row
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HROW
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Portion of a device including 12 horizontal :term:`clocks <clock>` and the
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@ -147,6 +147,11 @@ Glossary
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One of the configurable input/output blocks that connect the :term:`FPGA`
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to external devices.
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Interconnect tile
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INT
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An interconnect tile (`INT_L`, `INT_R`) is used to connect other tiles to
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the fabric. It is also frequently called a switch box.
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LUT
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A lookup table (LUT) is a logic element on the :term:`FPGA`. LUTs function
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as a ROM, apply combinatorial logic, and generate the output value for a
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@ -171,7 +176,7 @@ Glossary
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Place and route
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Place and route (PnR) is the process of taking logic and placing it into
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hardware logic elements on the :term:`FPGA`, and then routing the signals
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between the placed elements.
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between the placed elements.
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Region of interest
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ROI
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@ -222,4 +227,4 @@ Glossary
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Word
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32 bits stored in big-endian order. Fundamental unit of :term:`bitstream`
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format.
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format.
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@ -1,30 +1,30 @@
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Interconnect :term:`PIP`s
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=========================
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Interconnect :term:`PIPs <pip>`
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===============================
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Fake :term:`PIP`s
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-----------------
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Fake :term:`PIPs <pip>`
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-----------------------
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Some :term:`PIP`s are not "real", in the sense that no bit pattern in the bit-stream correspond to the PIP being used. This is the case for all the :term:`PIP`s in the switchbox in a CLB tile (ex: CLBLM_L_INTER): They either correspond to buffers that are always on (i.e. 1:1 connections such as `CLBLL_L.CLBLL_L_AQ->CLBLL_LOGIC_OUTS0`), or they correspond to permutations of LUT input signals, which is handled by changing the LUT init value accordingly, or they are used to "connect" two signals that are driven by the same signal from within the CLB.
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Some :term:`PIPs <pip>` are not "real", in the sense that no bit pattern in the bit-stream correspond to the PIP being used. This is the case for all the :term:`PIPs <pip>` in the switchbox in a CLB tile (ex: CLBLM_L_INTER): They either correspond to buffers that are always on (i.e. 1:1 connections such as `CLBLL_L.CLBLL_L_AQ->CLBLL_LOGIC_OUTS0`), or they correspond to permutations of LUT input signals, which is handled by changing the LUT init value accordingly, or they are used to "connect" two signals that are driven by the same signal from within the CLB.
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FIXME: Check the above is true.
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.. warning:: FIXME: Check the above is true.
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The bit switchbox in an :term:`INT`s tile also contains a few 1:1 connections that are in fact always present and have no corresponding configuration bits.
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The bit switchbox in an :term:`INTs <INT>` tile also contains a few 1:1 connections that are in fact always present and have no corresponding configuration bits.
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Regular :term:`PIP`s
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--------------------
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Regular :term:`PIPs <pip>`
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--------------------------
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Regular :term:`PIP`s correspond to a bit pattern that is present in the bit stream when the PIP is used in the current design. There is a block of up to 10-ish bits for each destination signal. For each configuration (i.e. source net that can drive the destination) there is a pair of bits that is set.
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Regular :term:`PIPs <pip>` correspond to a bit pattern that is present in the bit stream when the PIP is used in the current design. There is a block of up to 10-ish bits for each destination signal. For each configuration (i.e. source net that can drive the destination) there is a pair of bits that is set.
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FIXME: Check if the above is true for PIPs outside of the INT switch box.
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.. warning:: FIXME: Check if the above is true for PIPs outside of the INT switch box.
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For example, when the bits 05_57 and 11_56 are set then SR1END3->SE2BEG3 is enabled, but when 08_56 and 11_56 are set then ER1END3->SE2BEG3 is enabled (in an :term:`INT_L`s tile paired with a CLBLL_L tile). A configuration in which all three bits are set is invalid. See `segbits_int_[lr].db` for a complete list of bit pattern for configuring :term:`PIP`s.
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For example, when the bits 05_57 and 11_56 are set then SR1END3->SE2BEG3 is enabled, but when 08_56 and 11_56 are set then ER1END3->SE2BEG3 is enabled (in an :term:`INT_L <INT>`s tile paired with a CLBLL_L tile). A configuration in which all three bits are set is invalid. See `segbits_int_[lr].db` for a complete list of bit pattern for configuring :term:`PIPs <pip>`.
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VCC Drivers
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-----------
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The default state for a net is to be driven high. The :term:`PIP`s that drive a net from `VCC_WIRE` correspond to the "empty configuration" with no bits set.
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The default state for a net is to be driven high. The :term:`PIPs <pip>` that drive a net from `VCC_WIRE` correspond to the "empty configuration" with no bits set.
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Bidirectional :term:`PIP`s
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--------------------------
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Bidirectional :term:`PIPs <pip>`
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--------------------------------
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Bidirectional :term:`PIP`s are used to stitch together long traces (LV*, LVB*). In case of bidirectional :term:`PIP`s there are two different configuration patterns, one for each direction.
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Bidirectional :term:`PIPs <pip>` are used to stitch together long traces (LV*, LVB*). In case of bidirectional :term:`PIPs <pip>` there are two different configuration patterns, one for each direction.
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@ -21,7 +21,7 @@ The first number indicates the frame address relative to the base frame address
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The second number indicates the bit position width.
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FIXME: Expand this section. We've had a couple questions around this, probably good to get a complete description of this that we can point people too. This is probably a good place to talk about tile grid and how it applies to segbit.
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.. warning:: FIXME: Expand this section. We've had a couple questions around this, probably good to get a complete description of this that we can point people too. This is probably a good place to talk about tile grid and how it applies to segbit.
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segbits_*.db
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@ -73,16 +73,16 @@ Related tools:
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* Ex: CLB is solved by first solving LUT bits, and then solving FF bits
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Interconnect :term:`PIP` Tags
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Interconnect :term:`PIP <pip>` Tags
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Tags for interconnect :term:`PIP`s are stored in the `segbits_int_l.db` and `segbits_int_r.db` database files.
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Tags for interconnect :term:`PIPs <pip>` are stored in the `segbits_int_l.db` and `segbits_int_r.db` database files.
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Tags that enable interconnect :term:`PIP`s have the following syntax: `<tile_type>.<destination_wire>.<source_wire>`.
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Tags that enable interconnect :term:`PIPs <pip>` have the following syntax: `<tile_type>.<destination_wire>.<source_wire>`.
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The `<tile_type>` may be `INT_L` or `INT_R`. The destination and source wires are wire names in that tile type. For example, consider the following entry in `segbits_int_l.db`: `INT_L.NL1BEG1.NN6END2 07_32 12_33`
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FIXME: This is probably a good place to reference tileconn as the documentation that explains how wires are connected outside of switchboxes (which is what pips document).
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.. warning:: FIXME: This is probably a good place to reference tileconn as the documentation that explains how wires are connected outside of switchboxes (which is what pips document).
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This means that the bits `07_32` and `12_33` must be set in the segment to drive the value from the wire `NN6END2` to the wire `NL1BEG1`.
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@ -96,7 +96,7 @@ Tags for CLB tiles use a dot-separated hierarchy for their tag names. For exampl
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ppips_*.db
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----------
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Pseudo :term:`PIP`s are :term:`PIP`s in the Vivado tool, but do not have actual bit pattern. The `ppips_*.db` files contain information on pseudo-:term:`PIP`s. Those files contain one entry per pseudo-PIP, each with one of the following three tags: `always`, `default` or `hint`. The tag `always` is used for pseudo-:term:`PIP`s that are actually always-on, i.e. that are permanent connections between two wires. The tag `default` is used for pseudo-:term:`PIP`s that represent the default behavior if no other driver has been configured for the destination net (all `default` pseudo-:term:`PIP`s connect to the `VCC_WIRE` net). And the tag `hint` is used for :term:`PIP`s that are used by Vivado to tell the router that two logic slice outputs drive the same value, i.e. behave like they are connected as far as the routing process is concerned.
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Pseudo :term:`PIPs <pip>` are :term:`PIPs <pip>` in the Vivado tool, but do not have actual bit pattern. The `ppips_*.db` files contain information on pseudo-:term:`PIPs <pip>`. Those files contain one entry per pseudo-PIP, each with one of the following three tags: `always`, `default` or `hint`. The tag `always` is used for pseudo-:term:`PIPs <pip>` that are actually always-on, i.e. that are permanent connections between two wires. The tag `default` is used for pseudo-:term:`PIPs <pip>` that represent the default behavior if no other driver has been configured for the destination net (all `default` pseudo-:term:`PIPs <pip>` connect to the `VCC_WIRE` net). And the tag `hint` is used for :term:`PIPs <pip>` that are used by Vivado to tell the router that two logic slice outputs drive the same value, i.e. behave like they are connected as far as the routing process is concerned.
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mask_*.db
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---------
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@ -136,7 +136,7 @@ So in summary:
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So, with this in mind, we have frame base address 0x00020500 and word # 2. This maps to tilegrid.json entry SEG_CLBLL_L_X12Y101 (has "baseaddr": ["0x00020600", 2]). This also yields "type": "clbll_l" meaning we are configuring a CLBLL_L.
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FIXME: This example is out of date with the new tilegrid format, should update it.
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.. warning:: FIXME: This example is out of date with the new tilegrid format, should update it.
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Looking at segbits_clbll_l.db, we need to look up the bit at segment column 11, offset at bit 5. However, this is not present, so we fall back to segbits_int_l.db. This yields a few entries related to EL1BEG (ex: INT_L.EL1BEG_N3.EL1END0 11_05 13_05).
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@ -20,7 +20,7 @@ The file `tilegrid.json` contains lists of all tiles in the device and the confi
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For each segment this contains the configuration frame base address, and the word offset within the frames, as well as the number of frames for the segment and number of occupied words in each frame.
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FIXME: We should cross link to how to use the base address and word offset.
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.. warning:: FIXME: We should cross link to how to use the base address and word offset.
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For each tile this file contains the tile type, grid X/Y coordinates for the tile, and sites (slices) within the tile.
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@ -111,7 +111,7 @@ tileconn.json
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The file `tileconn.json` contains the information how the wires of neighboring tiles are connected to each other. It contains one entry for each pair of tile types, each containing a list of pairs of wires that belong to the same node.
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FIXME: This is a good place to add the tile wire, pip, site pin diagram.
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.. warning:: FIXME: This is a good place to add the tile wire, pip, site pin diagram.
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This file documents how adjacent tile pairs are connected.
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No directionality is given.
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