looping int fuzzers: combine common makefiles, piplist

Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster 2018-12-05 16:05:17 -08:00
parent c4751558c6
commit 277be8d7ca
26 changed files with 107 additions and 424 deletions

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@ -1,14 +1,3 @@
/filtered_seg_int_l.segbits
/filtered_seg_int_r.segbits
/pattern_l.txt
/pattern_r.txt
/piplist.dcp
/piplist/
/pips_int_l.txt
/pips_int_r.txt
/seg_int_l.segbits
/seg_int_r.segbits
/specimen_[0-9][0-9][0-9]/
/todo.txt
/vivado*
/run.ok
build
run.ok
todo

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@ -1,33 +1,2 @@
N := 10
SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
database: $(SPECIMENS_OK)
${XRAY_SEGMATCH} -m 5 -M 15 -o segbits_int_l.db $(addsuffix /segdata_int_l.txt,$(SPECIMENS))
${XRAY_SEGMATCH} -m 5 -M 15 -o segbits_int_r.db $(addsuffix /segdata_int_r.txt,$(SPECIMENS))
pushdb:
${XRAY_DBFIXUP} --db-root . --clb-int
${XRAY_MERGEDB} int_l segbits_int_l.db
${XRAY_MERGEDB} int_r segbits_int_r.db
$(SPECIMENS_OK): todo.txt
bash generate.sh $(subst /OK,,$@)
touch $@
todo.txt:
vivado -mode batch -source piplist.tcl
python3 maketodo.py > todo.txt
run:
+set -ex; while make clean; make todo.txt; test -s todo.txt; do make database; make pushdb; done; true
touch run.ok
clean:
rm -rf .Xil/ .cache/ run.ok
rm -rf todo.txt vivado* piplist/ piplist.dcp pattern_[lr].txt pips_int_[lr].txt
rm -rf specimen_[0-9][0-9][0-9]/ segbits_int_[lr].db mask_clbl[lm]_[lr].segbits
.PHONY: database pushdb run clean
include ../int_loop.mk

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@ -1,6 +1,8 @@
source "$::env(XRAY_DIR)/utils/utils.tcl"
create_project -force -part $::env(XRAY_PART) design design
read_verilog ../top.v
read_verilog $::env(FUZDIR)/top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
@ -19,7 +21,6 @@ route_design
# write_checkpoint -force design.dcp
source ../../../utils/utils.tcl
set fp [open "../todo.txt" r]
set todo_lines {}

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@ -20,8 +20,8 @@ def maketodo(pipfile, dbfile):
maketodo(
"pips_int_l.txt", "%s/%s/segbits_int_l.db" %
"build/pips_int_l.txt", "%s/%s/segbits_int_l.db" %
(os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE")))
maketodo(
"pips_int_r.txt", "%s/%s/segbits_int_r.db" %
"build/pips_int_r.txt", "%s/%s/segbits_int_r.db" %
(os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE")))

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@ -1,39 +0,0 @@
create_project -force -part $::env(XRAY_PART) piplist piplist
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
place_design
route_design
write_checkpoint -force piplist.dcp
source ../../utils/utils.tcl
proc print_tile_pips {tile_type filename} {
set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
puts "Dumping PIPs for tile $tile ($tile_type) to $filename."
set fp [open $filename w]
foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
set src [get_wires -uphill -of_objects $pip]
set dst [get_wires -downhill -of_objects $pip]
if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
}
}
close $fp
}
print_tile_pips INT_L pips_int_l.txt
print_tile_pips INT_R pips_int_r.txt

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@ -1,14 +1,3 @@
/filtered_seg_int_l.segbits
/filtered_seg_int_r.segbits
/pattern_l.txt
/pattern_r.txt
/piplist.dcp
/piplist/
/pips_int_l.txt
/pips_int_r.txt
/seg_int_l.segbits
/seg_int_r.segbits
/specimen_[0-9][0-9][0-9]/
/todo.txt
/vivado*
/run.ok
build
run.ok
todo

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@ -1,33 +1,2 @@
N := 10
SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
database: $(SPECIMENS_OK)
${XRAY_SEGMATCH} -m 5 -M 15 -o segbits_int_l.db $(addsuffix /segdata_int_l.txt,$(SPECIMENS))
${XRAY_SEGMATCH} -m 5 -M 15 -o segbits_int_r.db $(addsuffix /segdata_int_r.txt,$(SPECIMENS))
pushdb:
${XRAY_DBFIXUP} --db-root . --clb-int
${XRAY_MERGEDB} int_l segbits_int_l.db
${XRAY_MERGEDB} int_r segbits_int_r.db
$(SPECIMENS_OK): todo.txt
bash generate.sh $(subst /OK,,$@)
touch $@
todo.txt:
vivado -mode batch -source piplist.tcl
python3 maketodo.py | sort -R | head -n10 > todo.txt
run:
+set -ex; while make clean; make todo.txt; test -s todo.txt; do make database; make pushdb; done; true
touch run.ok
clean:
rm -rf .Xil/ .cache/ filtered_seg_int_[lr].db run.ok
rm -rf todo.txt vivado* piplist/ piplist.dcp pattern_[lr].txt pips_int_[lr].txt
rm -rf specimen_[0-9][0-9][0-9]/ segbits_int_[lr].db mask_clbl[lm]_[lr].segbits
.PHONY: database pushdb run clean
include ../int_loop.mk

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@ -1,6 +1,8 @@
source "$::env(XRAY_DIR)/utils/utils.tcl"
create_project -force -part $::env(XRAY_PART) design design
read_verilog ../top.v
read_verilog $::env(FUZDIR)/top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
@ -19,7 +21,6 @@ route_design
# write_checkpoint -force design.dcp
source ../../../utils/utils.tcl
set fp [open "../todo.txt" r]
set todo_lines {}

View File

@ -19,8 +19,8 @@ def maketodo(pipfile, dbfile):
maketodo(
"pips_int_l.txt", "%s/%s/segbits_int_l.db" %
"build/pips_int_l.txt", "%s/%s/segbits_int_l.db" %
(os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE")))
maketodo(
"pips_int_r.txt", "%s/%s/segbits_int_r.db" %
"build/pips_int_r.txt", "%s/%s/segbits_int_r.db" %
(os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE")))

View File

@ -1,39 +0,0 @@
create_project -force -part $::env(XRAY_PART) piplist piplist
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
place_design
route_design
write_checkpoint -force piplist.dcp
source ../../utils/utils.tcl
proc print_tile_pips {tile_type filename} {
set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
puts "Dumping PIPs for tile $tile ($tile_type) to $filename."
set fp [open $filename w]
foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
set src [get_wires -uphill -of_objects $pip]
set dst [get_wires -downhill -of_objects $pip]
if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
}
}
close $fp
}
print_tile_pips INT_L pips_int_l.txt
print_tile_pips INT_R pips_int_r.txt

View File

@ -1,14 +1,3 @@
/filtered_seg_int_l.segbits
/filtered_seg_int_r.segbits
/pattern_l.txt
/pattern_r.txt
/piplist.dcp
/piplist/
/pips_int_l.txt
/pips_int_r.txt
/seg_int_l.segbits
/seg_int_r.segbits
/specimen_[0-9][0-9][0-9]/
/todo.txt
/vivado*
/run.ok
build
run.ok
todo

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@ -1,33 +1,2 @@
N := 10
SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
database: $(SPECIMENS_OK)
${XRAY_SEGMATCH} -m 5 -M 15 -o segbits_int_l.db $(addsuffix /segdata_int_l.txt,$(SPECIMENS))
${XRAY_SEGMATCH} -m 5 -M 15 -o segbits_int_r.db $(addsuffix /segdata_int_r.txt,$(SPECIMENS))
pushdb:
${XRAY_DBFIXUP} --db-root . --clb-int
${XRAY_MERGEDB} int_l segbits_int_l.db
${XRAY_MERGEDB} int_r segbits_int_r.db
$(SPECIMENS_OK): todo.txt
bash generate.sh $(subst /OK,,$@)
touch $@
todo.txt:
vivado -mode batch -source piplist.tcl
python3 maketodo.py | sort -R | head -n10 > todo.txt
run:
+set -ex; while make clean; make todo.txt; test -s todo.txt; do make database; make pushdb; done; true
touch run.ok
clean:
rm -rf .Xil/ .cache/ filtered_seg_int_[lr].db run.ok
rm -rf todo.txt vivado* piplist/ piplist.dcp pattern_[lr].txt pips_int_[lr].txt
rm -rf specimen_[0-9][0-9][0-9]/ segbits_int_[lr].db mask_clbl[lm]_[lr].segbits
.PHONY: database pushdb run clean
include ../int_loop.mk

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@ -1,6 +1,8 @@
source "$::env(XRAY_DIR)/utils/utils.tcl"
create_project -force -part $::env(XRAY_PART) design design
read_verilog ../top.v
read_verilog $::env(FUZDIR)/top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
@ -19,7 +21,6 @@ route_design
# write_checkpoint -force design.dcp
source ../../../utils/utils.tcl
set fp [open "../todo.txt" r]
set todo_lines {}

View File

@ -19,8 +19,8 @@ def maketodo(pipfile, dbfile):
maketodo(
"pips_int_l.txt", "%s/%s/segbits_int_l.db" %
"build/pips_int_l.txt", "%s/%s/segbits_int_l.db" %
(os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE")))
maketodo(
"pips_int_r.txt", "%s/%s/segbits_int_r.db" %
"build/pips_int_r.txt", "%s/%s/segbits_int_r.db" %
(os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE")))

View File

@ -1,39 +0,0 @@
create_project -force -part $::env(XRAY_PART) piplist piplist
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
place_design
route_design
write_checkpoint -force piplist.dcp
source ../../utils/utils.tcl
proc print_tile_pips {tile_type filename} {
set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
puts "Dumping PIPs for tile $tile ($tile_type) to $filename."
set fp [open $filename w]
foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
set src [get_wires -uphill -of_objects $pip]
set dst [get_wires -downhill -of_objects $pip]
if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
}
}
close $fp
}
print_tile_pips INT_L pips_int_l.txt
print_tile_pips INT_R pips_int_r.txt

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@ -1,13 +1,3 @@
/filtered_seg_int_l.segbits
/filtered_seg_int_r.segbits
/pattern_l.txt
/pattern_r.txt
/piplist.dcp
/piplist/
/pips_int_l.txt
/pips_int_r.txt
/seg_int_l.segbits
/seg_int_r.segbits
/specimen_[0-9][0-9][0-9]/
/todo.txt
/vivado*
build
run.ok
todo

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@ -1,33 +1,2 @@
N := 10
SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
database: $(SPECIMENS_OK)
${XRAY_SEGMATCH} -m 5 -M 15 -o segbits_int_l.db $(addsuffix /segdata_int_l.txt,$(SPECIMENS))
${XRAY_SEGMATCH} -m 5 -M 15 -o segbits_int_r.db $(addsuffix /segdata_int_r.txt,$(SPECIMENS))
pushdb:
${XRAY_DBFIXUP} --db-root . --clb-int
${XRAY_MERGEDB} int_l segbits_int_l.db
${XRAY_MERGEDB} int_r segbits_int_r.db
$(SPECIMENS_OK): todo.txt
bash generate.sh $(subst /OK,,$@)
touch $@
todo.txt:
vivado -mode batch -source piplist.tcl
python3 maketodo.py | sort -R | head -n10 > todo.txt
run:
+set -ex; while make clean; make todo.txt; test -s todo.txt; do make database; make pushdb; done; true
touch run.ok
clean:
rm -rf .Xil/ .cache/ filtered_seg_int_[lr].db run.ok
rm -rf todo.txt vivado* piplist/ piplist.dcp pattern_[lr].txt pips_int_[lr].txt
rm -rf specimen_[0-9][0-9][0-9]/ segbits_int_[lr].db mask_clbl[lm]_[lr].segbits
.PHONY: database pushdb run clean
include ../int_loop.mk

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@ -1,5 +1,7 @@
#!/bin/bash
echo "test: $PWD"
FUZDIR=$PWD
source ${XRAY_GENHEADER}
vivado -mode batch -source ../generate.tcl

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@ -1,9 +1,9 @@
source ../../../utils/utils.tcl
source "$::env(XRAY_DIR)/utils/utils.tcl"
proc base_project {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog ../top.v
read_verilog $::env(FUZDIR)/top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
@ -56,10 +56,7 @@ proc loop { line idx int_l_tile int_r_tile } {
set mynet [create_net mynet_$idx]
connect_net -net $mynet -objects "$mylut/I0 $mylut/O"
# In most cases a new design will successfully route
if { [route_via_ret $mynet "$tile/$src_wire $tile/$dst_wire"] == 0 } {
puts "WARNING: failed to route $mynet"
}
route_via $mynet "$tile/$src_wire $tile/$dst_wire"
}
proc load_todo_lines {} {

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@ -20,8 +20,8 @@ def maketodo(pipfile, dbfile):
maketodo(
"pips_int_l.txt", "%s/%s/segbits_int_l.db" %
"build/pips_int_l.txt", "%s/%s/segbits_int_l.db" %
(os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE")))
maketodo(
"pips_int_r.txt", "%s/%s/segbits_int_r.db" %
"build/pips_int_r.txt", "%s/%s/segbits_int_r.db" %
(os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE")))

View File

@ -1,39 +0,0 @@
create_project -force -part $::env(XRAY_PART) piplist piplist
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
place_design
route_design
write_checkpoint -force piplist.dcp
source ../../utils/utils.tcl
proc print_tile_pips {tile_type filename} {
set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
puts "Dumping PIPs for tile $tile ($tile_type) to $filename."
set fp [open $filename w]
foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
set src [get_wires -uphill -of_objects $pip]
set dst [get_wires -downhill -of_objects $pip]
if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
}
}
close $fp
}
print_tile_pips INT_L pips_int_l.txt
print_tile_pips INT_R pips_int_r.txt

View File

@ -30,7 +30,7 @@ run:
clean:
rm -rf .Xil/ .cache/ filtered_seg_int_[lr].db run.ok
rm -rf todo.txt vivado* piplist/ piplist.dcp pattern_[lr].txt pips_int_[lr].txt
rm -rf todo.txt vivado* pattern_[lr].txt pips_int_[lr].txt
rm -rf specimen_[0-9][0-9][0-9]/ segbits_int_[lr].db mask_clbl[lm]_[lr].segbits
.PHONY: database pushdb run clean

View File

@ -1,61 +1,2 @@
# WARNING: N cannot be reduced or -m will always fail
N := 10
SPECIMENS := $(addprefix build/specimen_,$(shell seq -f '%03.0f' $(N)))
SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
database: $(SPECIMENS_OK)
${XRAY_SEGMATCH} -m 5 -M 15 -o build/segbits_int_l.db $(addsuffix /segdata_int_l.txt,$(SPECIMENS))
${XRAY_SEGMATCH} -m 5 -M 15 -o build/segbits_int_r.db $(addsuffix /segdata_int_r.txt,$(SPECIMENS))
pushdb:
${XRAY_DBFIXUP} --db-root . --clb-int
${XRAY_MERGEDB} int_l build/segbits_int_l.db
${XRAY_MERGEDB} int_r build/segbits_int_r.db
$(SPECIMENS_OK): build/todo.txt
mkdir -p build
bash ${XRAY_DIR}/utils/top_generate.sh $(subst /OK,,$@)
touch $@
build/pips_int_l.txt: piplist.tcl
mkdir -p build
cd build && vivado -mode batch -source ../piplist.tcl
# Used 1) to see if we are done 2) pips to try in generate.tcl
build/todo.txt: build/pips_int_l.txt
#python3 maketodo.py --no-strict | sort -R | head -n10 > build/todo.txt.tmp
python3 maketodo.py >build/todo_all.txt
cat build/todo_all.txt | sort -R | head -n10 > build/todo.txt.tmp
mv build/todo.txt.tmp build/todo.txt
# XXX: conider moving to script
run:
\
set -ex; \
make clean; \
mkdir -p todo; \
while \
make cleanprj; \
make build/todo.txt || exit 1; \
test -s build/todo.txt; \
do \
i=$$((i+1)); \
cp build/todo.txt todo/$${i}.txt; \
cp build/todo_all.txt todo/$${i}_all.txt; \
if make database; then \
make pushdb; \
fi; \
done; \
true
touch run.ok
clean:
rm -rf build run.ok todo
# Remove iteration specific files, but keep piplist.tcl output
cleanprj:
rm -rf build/specimen_* build/todo.txt build/*.db
.PHONY: database pushdb run clean cleanprj
include ../int_loop.mk

View File

@ -1,6 +1,8 @@
source "$::env(XRAY_DIR)/utils/utils.tcl"
create_project -force -part $::env(XRAY_PART) design design
read_verilog ../../top.v
read_verilog $::env(FUZDIR)/top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
@ -19,8 +21,6 @@ route_design
# write_checkpoint -force design.dcp
source "$::env(XRAY_DIR)/utils/utils.tcl"
set fp [open "../todo.txt" r]
set todo_lines {}
for {gets $fp line} {$line != ""} {gets $fp line} {

63
fuzzers/int_loop.mk Normal file
View File

@ -0,0 +1,63 @@
# WARNING: N cannot be reduced or -m will always fail
N := 10
SPECIMENS := $(addprefix build/specimen_,$(shell seq -f '%03.0f' $(N)))
SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
# Individual fuzzer directory, such as ~/prjxray/fuzzers/010-lutinit
export FUZDIR=$(shell pwd)
database: $(SPECIMENS_OK)
${XRAY_SEGMATCH} -m 5 -M 15 -o build/segbits_int_l.db $(addsuffix /segdata_int_l.txt,$(SPECIMENS))
${XRAY_SEGMATCH} -m 5 -M 15 -o build/segbits_int_r.db $(addsuffix /segdata_int_r.txt,$(SPECIMENS))
pushdb:
${XRAY_DBFIXUP} --db-root . --clb-int
${XRAY_MERGEDB} int_l build/segbits_int_l.db
${XRAY_MERGEDB} int_r build/segbits_int_r.db
$(SPECIMENS_OK): build/todo.txt
mkdir -p build
bash ${XRAY_DIR}/utils/top_generate.sh $(subst /OK,,$@)
touch $@
build/pips_int_l.txt: $(FUZDIR)/../piplist.tcl
mkdir -p build
cd build && vivado -mode batch -source $(FUZDIR)/../piplist.tcl
# Used 1) to see if we are done 2) pips to try in generate.tcl
build/todo.txt: build/pips_int_l.txt maketodo.py
#python3 maketodo.py --no-strict | sort -R | head -n10 > build/todo.txt.tmp
python3 maketodo.py >build/todo_all.txt
cat build/todo_all.txt | sort -R | head -n10 > build/todo.txt.tmp
mv build/todo.txt.tmp build/todo.txt
# XXX: conider moving to script
run:
\
set -ex; \
make clean; \
mkdir -p todo; \
while \
make cleanprj; \
make build/todo.txt || exit 1; \
test -s build/todo.txt; \
do \
i=$$((i+1)); \
cp build/todo.txt todo/$${i}.txt; \
cp build/todo_all.txt todo/$${i}_all.txt; \
if make database; then \
make pushdb; \
fi; \
done; \
true
touch run.ok
clean:
rm -rf build run.ok todo
# Remove iteration specific files, but keep piplist.tcl output
cleanprj:
rm -rf build/specimen_* build/todo.txt build/*.db
.PHONY: database pushdb run clean cleanprj

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@ -1,6 +1,6 @@
create_project -force -part $::env(XRAY_PART) piplist piplist
read_verilog ../top.v
read_verilog $::env(FUZDIR)/top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]