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Merge pull request #711 from antmicro/zynq_roi 

zybo: Fix Zybq Zynq-7 roi_harness
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litghost 2019-03-12 11:58:48 -07:00 committed by GitHub
parent 1d93bd08f3 49c8aac143
commit 2389645525
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3 changed files with 20 additions and 6 deletions
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22
minitests/roi_harness/runme.tcl
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@ -78,7 +78,7 @@ set Y_DIN_BASE [expr "$Y_CLK_BASE + $PITCH"]
# set Y_DOUT_BASE [expr "$Y_DIN_BASE + $DIN_N"] # set Y_DOUT_BASE [expr "$Y_DIN_BASE + $DIN_N"]
# At top. This relieves routing pressure by spreading things out # At top. This relieves routing pressure by spreading things out
# Note: can actually go up one more if we want # Note: can actually go up one more if we want
set Y_DOUT_BASE [expr "$XRAY_ROI_Y1 - $DIN_N * $PITCH"] set Y_DOUT_BASE [expr "$XRAY_ROI_Y1 - $DOUT_N * $PITCH"]
# Y_OFFSET: offset amount to shift the components on the y column to avoid hard blocks # Y_OFFSET: offset amount to shift the components on the y column to avoid hard blocks
set Y_OFFSET 24 set Y_OFFSET 24
@ -234,9 +234,23 @@ if {$part eq "xc7a50tfgg484-1"} {
if {$pincfg eq "ZYBOZ7-SWBUT"} { if {$pincfg eq "ZYBOZ7-SWBUT"} {
# https://github.com/Digilent/digilent-xdc/blob/master/Zybo-Z7-Master.xdc # https://github.com/Digilent/digilent-xdc/blob/master/Zybo-Z7-Master.xdc
# Slide switches and buttons #
set ins "G15 P15 W13 T16" # J15 - UART_RX - JE3
set outs "M14 M15 G14 D18" # G15 - SW0
# K18 - BTN0
# K19 - BTN1
#
set ins "J15 G15 K18 K19"
#
# H15 - UART_TX - JE4
# E17 - ETH PHY reset (active low, keep high for 125 MHz clock)
# M14 - LD0
# G14 - LD2
# M15 - LD1
# D18 - LD3
#
set outs "H15 E17 M14 M15 D18 G14"
# 125 MHz CLK onboard # 125 MHz CLK onboard
set pin "K17" set pin "K17"

2
minitests/roi_harness/zybo.sh
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@ -2,7 +2,7 @@
export XRAY_PART=xc7z010clg400-1 export XRAY_PART=xc7z010clg400-1
export XRAY_PINCFG=ZYBOZ7-SWBUT export XRAY_PINCFG=ZYBOZ7-SWBUT
export XRAY_DIN_N_LARGE=4 export XRAY_DIN_N_LARGE=4
export XRAY_DOUT_N_LARGE=4 export XRAY_DOUT_N_LARGE=6
# For generating DB # For generating DB
export XRAY_PIN_00="G15" export XRAY_PIN_00="G15"

2
settings/zynq7.sh
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@ -9,7 +9,7 @@ export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X43Y99 RAMB18_X0Y0:RAMB18_X2Y39 RAMB3
export XRAY_ROI="SLICE_X00Y50:SLICE_X43Y99 RAMB18_X0Y20:RAMB18_X2Y39 RAMB36_X0Y10:RAMB36_X2Y19 IOB_X0Y50:IOB_X0Y99" export XRAY_ROI="SLICE_X00Y50:SLICE_X43Y99 RAMB18_X0Y20:RAMB18_X2Y39 RAMB36_X0Y10:RAMB36_X2Y19 IOB_X0Y50:IOB_X0Y99"
# Most of CMT X0Y2. # Most of CMT X0Y2.
export XRAY_ROI_GRID_X1="0" export XRAY_ROI_GRID_X1="83"
export XRAY_ROI_GRID_X2="118" export XRAY_ROI_GRID_X2="118"
# Include VBRK / VTERM # Include VBRK / VTERM
export XRAY_ROI_GRID_Y1="0" export XRAY_ROI_GRID_Y1="0"