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fixedpnr: try FF attributes 

Signed-off-by: John McMaster <JohnDMcMaster@gmail.com>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster 2017-11-17 20:55:13 -08:00 committed by Tim 'mithro' Ansell
parent 59c490c3d0
commit 20e9b80923
4 changed files with 58 additions and 7 deletions
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9
minitests/fixedpnr/.gitignore vendored
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@ -1,8 +1,9 @@
/.Xil/
/design_fd?e/
/design_fd?e.dcp
/design_fd?e.bit
/design_fd?e.bits
/design_*/
/design_*.dcp
/design_*.bit
/design_*.bits
/design_*.segd
/fixed.xdc
/usage_statistics_webtalk.*
/vivado*

5
minitests/fixedpnr/runme.sh
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@ -2,8 +2,9 @@
set -ex
vivado -mode batch -source runme.tcl
for ff in fdre fdse fdce fdpe; do
for ff in fdre fdse fdce fdce_inv fdpe; do
${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design_$ff.bits -z -y design_$ff.bit
python3 ../../utils/segprint.py design_$ff.bits >design_$ff.seg
${XRAY_SEGPRINT} design_$ff.bits >design_$ff.seg
done
diff -u design_fdre.bits design_fdse.bits

2
minitests/fixedpnr/runme.tcl
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@ -29,7 +29,7 @@ write_bitstream -force design_fdre.bit
close_project
foreach variant {fdse fdce fdpe} {
foreach variant {fdse fdce fdce_inv fdpe} {}
create_project -force -part $::env(XRAY_PART) design_${variant} design_${variant}
read_verilog top_${variant}.v
read_xdc fixed.xdc

49
minitests/fixedpnr/top_fdce_inv.v Normal file
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@ -0,0 +1,49 @@
module top(input clk, ce, sr, d, output q);
/*
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b1, IS_CLR_INVERTED=1'b1,
ERROR: [Place 30-1008] Instance ff has an inverted D pin which is expected to be used as an I/O flop.
However, it is used as a regular flop.
cliff didn't have constrained, also got annoyed
he is using slightly later version
ERROR: [Place 30-1008] Instance roi/ffs[0].genblk1.genblk1.ff
has an inverted D pin which is unsupported in the UltraScale and UltraScale+ architectures.
which is fine except...he's using 7 series
and now...
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b1,
ERROR: [Place 30-488] Failed to commit 1 instances:
ff with block Id: 4 (FF) at SLICE_X0Y104
ERROR: [Place 30-99] Placer failed with error: 'failed to commit all instances'
IS_C_INVERTED=1'b0, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b1,
failed with same message
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b0,
built!
diff design_fdce.segd design_fdce_inv.segd
> tag CLBLL_L.SLICEL_X0.CLKINV
expected
IS_C_INVERTED=1'b0, IS_D_INVERTED=1'b1, IS_CLR_INVERTED=1'b0,
ERROR: [Place 30-1008] Instance ff has an inverted D pin which is expected to be used as an I/O flop.
However, it is used as a regular flop.
ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer stopped due to earlier errors.
Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
*/
(*
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b0,
LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH
*)
FDCE ff (
.C(clk),
.CE(ce),
.CLR(sr),
.D(d),
.Q(q)
);
endmodule