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fuzzers: 007: handle output vector pins 

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
This commit is contained in:
Karol Gugala 2019-06-04 20:29:19 +02:00
parent cdcb759299
commit 209240e77f
1 changed files with 9 additions and 2 deletions
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11
fuzzers/007-timing/bel/tim2json.py
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@ -300,13 +300,14 @@ def read_raw_timings(fin, properties, pins, site_pins, pin_alias_map):
# is wider than 1 bit and timing defined for the whole # is wider than 1 bit and timing defined for the whole
# port # port
import re import re
if bel_input is None: if (bel_input is None) or (bel_output is None):
for pin in pins[slice][site_name][ for pin in pins[slice][site_name][
delay_btype_orig]: delay_btype_orig]:
number = re.search(r'\d+$', pin) number = re.search(r'\d+$', pin)
if number is not None: if number is not None:
orig_pin = pin[:-( orig_pin = pin[:-(
len(str(number.group())))] len(str(number.group())))]
orig_pin_full = pin
pim, pin = pin_in_model( pim, pin = pin_in_model(
orig_pin.lower(), pin_aliases, orig_pin.lower(), pin_aliases,
speed_model_clean) speed_model_clean)
@ -320,11 +321,17 @@ def read_raw_timings(fin, properties, pins, site_pins, pin_alias_map):
speed_model_clean) speed_model_clean)
if pim: if pim:
bel_input = pin if pins[slice][site_name][delay_btype_orig][orig_pin_full]['direction'] == 'IN' \
and bel_input is None:
bel_input = pin
if pins[slice][site_name][delay_btype_orig][orig_pin_full]['direction'] == 'OUT' \
and bel_output is None:
bel_output = pin
speed_model_clean = remove_pin_from_model( speed_model_clean = remove_pin_from_model(
orig_pin.lower(), orig_pin.lower(),
speed_model_clean) speed_model_clean)
# if we still don't have input, give up # if we still don't have input, give up
if bel_input is None: if bel_input is None:
delay_loc += 6 delay_loc += 6