Add picorv32 experiment

Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>

picorv32/.gitignore

@@ -0,0 +1,7 @@
+/.Xil/
+/design.log
+/design.tcl
+/design.xdc
+/design/
+/vivado.jou
+/vivado.log

picorv32/design.v

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+module top(input clk, din, stb, output dout);
+	reg [33:0] din_bits;
+	wire [70:0] dout_bits;
+
+	reg [33:0] din_shr;
+	reg [70:0] dout_shr;
+
+	always @(posedge clk) begin
+		if (stb) begin
+			din_bits <= din_shr;
+			dout_shr <= dout_bits;
+		end else begin
+			din_shr <= {din_shr, din};
+			dout_shr <= {dout_shr, din_shr[33]};
+		end
+	end
+
+	assign dout = dout_shr[70];
+
+	picorv32 picorv32 (
+		.clk(clk),
+		.resetn(din_bits[0]),
+		.mem_valid(dout_bits[0]),
+		.mem_instr(dout_bits[1]),
+		.mem_ready(din_bits[1]),
+		.mem_addr(dout_bits[33:2]),
+		.mem_wdata(dout_bits[66:34]),
+		.mem_wstrb(dout_bits[70:67]),
+		.mem_rdata(din_bits[33:2])
+	);
+endmodule

picorv32/runme.sh

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+#!/bin/bash
+
+set -ex
+
+source ../settings.sh
+
+cat > design.xdc << EOT
+set_property -dict {PACKAGE_PIN $XRAY_PIN_00 IOSTANDARD LVCMOS33} [get_ports clk]
+set_property -dict {PACKAGE_PIN $XRAY_PIN_01 IOSTANDARD LVCMOS33} [get_ports din]
+set_property -dict {PACKAGE_PIN $XRAY_PIN_02 IOSTANDARD LVCMOS33} [get_ports dout]
+set_property -dict {PACKAGE_PIN $XRAY_PIN_03 IOSTANDARD LVCMOS33} [get_ports stb]
+
+# set_property LOCK_PINS {I0:A1}                               [get_cells -quiet -filter {REF_NAME == LUT1} -hierarchical]
+# set_property LOCK_PINS {I0:A1 I1:A2}                         [get_cells -quiet -filter {REF_NAME == LUT2} -hierarchical]
+# set_property LOCK_PINS {I0:A1 I1:A2 I2:A3}                   [get_cells -quiet -filter {REF_NAME == LUT3} -hierarchical]
+# set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4}             [get_cells -quiet -filter {REF_NAME == LUT4} -hierarchical]
+# set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5}       [get_cells -quiet -filter {REF_NAME == LUT5} -hierarchical]
+# set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} [get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
+
+create_pblock pblock_1
+add_cells_to_pblock [get_pblocks pblock_1] [get_cells -quiet [list picorv32]]
+resize_pblock [get_pblocks pblock_1] -add {$XRAY_ROI}
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+EOT
+
+cat > design.tcl << EOT
+create_project -force -part $XRAY_PART design design
+
+read_xdc design.xdc
+read_verilog design.v
+read_verilog picorv32.v
+
+synth_design -top top
+place_design
+route_design
+
+write_checkpoint -force design.dcp
+write_bitstream -force design.bit
+EOT
+
+rm -rf design design.log
+vivado -nojournal -log design.log -mode batch -source design.tcl
+

settings.sh

@@ -1,4 +1,5 @@
 export XRAY_PART="xc7a50tfgg484-1"
+export XRAY_ROI="SLICE_X12Y100:SLICE_X27Y149"
 export XRAY_PIN_00="E22"
 export XRAY_PIN_01="D22"
 export XRAY_PIN_02="E21"