clbram fuzzer main bits. Some disabled due to automated ambiguity

Signed-off-by: John McMaster <JohnDMcMaster@gmail.com>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>

fuzzers/018-clbram/.gitignore

@@ -0,0 +1,4 @@
+/specimen_*/
+/*.segbits
+/vivado.log
+/vivado.jou

fuzzers/018-clbram/generate.py

@@ -7,27 +7,79 @@ from segmaker import segmaker
 
 segmk = segmaker("design.bits")
 
+# Can fit 4 per CLB
+# BELable
+multi_bels_by = [
+    'SRL16E',
+    'SRLC32E',
+    ]
+# Not BELable
+multi_bels_bn = [
+    'RAM32X1S',
+    'RAM64X1S',
+    ]
+
+# Those requiring special resources
+# Just make one per module
+greedy_modules = [
+    'my_RAM128X1D',
+    'my_RAM128X1S',
+    'my_RAM256X1S',
+    ]
+
 print("Loading tags")
 '''
-module,loc,n,def_a
+module,loc,bela,belb,belc,beld
-clb_N5FFMUX,SLICE_X12Y100,3,1
+my_ram_N,SLICE_X12Y100,SRL16E,SRLC32E,SRLC32E,SRLC32E
-clb_N5FFMUX,SLICE_X13Y100,0,1
+my_ram_N,SLICE_X12Y101,SRLC32E,SRL16E,SRL16E,SRLC32E
-clb_N5FFMUX,SLICE_X14Y100,3,1
+my_ram_N,SLICE_X12Y102,SRLC32E,SRL16E,SRLC32E,RAM32X1S
+my_RAM256X1S,SLICE_X12Y103,,,,
 '''
 f = open('params.csv', 'r')
 f.readline()
 for l in f:
-    module,loc,n,def_a = l.split(',')
+    l = l.strip()
-    def_a = int(def_a)
+    module,loc,bela,belb,belc,beld = l.split(',')
-    n = int(n)
+    bels = [bela,belb,belc,beld]
-    #which = chr(ord('A') + n)
+    if module in greedy_modules:
+        '''
+        my_RAM128X1D #(.LOC("SLICE_X12Y100"))
+            WA7USED
+        my_RAM128X1S #(.LOC("SLICE_X12Y102"))
+            WA7USED
+        my_RAM256X1S #(.LOC("SLICE_X12Y103"))
+            WA7USED, WA8USED
+        '''
+        which = 'D'
+        if 0:
+            segmk.addtag(loc, "WA7USED", 1)
+            segmk.addtag(loc, "WA8USED", module == 'my_RAM256X1S')
+    else:
+        '''
+        LUTD
+                    01_23   01_59   30_47   31_47
+        SRL16E      1       1       1
+        SRLC32E     1               1
+        RAM32X1S    1       1               1
+        RAM64X1S    1                       1
+
+        01_23: WEMUX.CE (more info needed)
+        01_59: half sized memory
+        30_47: SRL mode
+        31_47: RAM mode
+        '''
+        for which, bel in zip('ABCD', bels):
+            print(which, bel)
+            segmk.addtag(loc, "%sLUT.SMALL" % which, bel in ('SRL16E', 'RAM32X1S'))
+            segmk.addtag(loc, "%sLUT.SRL" % which, bel in ('SRL16E', 'SRLC32E'))
+            # Only valid in D
+            if which == 'D':
+                segmk.addtag(loc, "%sLUT.RAM" % which, bel in ('RAM32X1S', 'RAM64X1S'))
+        if 0:
+            segmk.addtag(loc, "WA7USED", 0)
+            segmk.addtag(loc, "WA8USED", 0)
+            segmk.addtag(loc, "WEMUX.CE", bels != ['LUT6', 'LUT6', 'LUT6', 'LUT6'])
 
-    for i, which in enumerate('ABCD'):
-        # Theory: there is one bit for each mux positon
-        # In each config 3 muxes are in one position, other 3 are in another
-        inv = int(i == n)
-        segmk.addtag(loc, "%c5FF.MUX.A" % which, def_a ^ inv)
-        segmk.addtag(loc, "%c5FF.MUX.B" % which, 1 ^ def_a ^ inv)
 segmk.compile()
 segmk.write()
 

fuzzers/018-clbram/top.py

@@ -11,7 +11,7 @@ def slice_xy():
     ms = [int(m.group(i + 1)) for i in range(4)]
     return ((ms[0], ms[2] + 1), (ms[1], ms[3] + 1))
 
-CLBN = 4
+CLBN = 50
 SLICEX, SLICEY = slice_xy()
 # 800
 SLICEN = (SLICEY[1] - SLICEY[0]) * (SLICEX[1] - SLICEX[0])
@@ -75,10 +75,11 @@ endmodule
 ''' % (DIN_N, DOUT_N))
 
 f = open('params.csv', 'w')
-f.write('module,loc,n,def_a\n')
+f.write('module,loc,bela,belb,belc,beld\n')
 slices = gen_slicems()
 print('module roi(input clk, input [%d:0] din, output [%d:0] dout);' % (DIN_N - 1, DOUT_N - 1))
-for i in range(CLBN):
+multis = 0
+for clbi in range(CLBN):
     bel = ''
 
     # Can fit 4 per CLB
@@ -86,6 +87,7 @@ for i in range(CLBN):
     multi_bels_by = [
         'SRL16E',
         'SRLC32E',
+        'LUT6',
         ]
     # Not BELable
     multi_bels_bn = [
@@ -103,6 +105,7 @@ for i in range(CLBN):
 
     loc = next(slices)
 
+    params = ''
     cparams = ''
     # Multi module
     if random.randint(0, 3) > 0:
@@ -110,7 +113,19 @@ for i in range(CLBN):
         module = 'my_ram_N'
 
         # Pick one un-LOCable and then fill in with LOCable
-        unbel_beli = random.randint(0, 3)
+        '''
+        CRITICAL WARNING: [Constraints 18-5] Cannot loc instance '\''roi/clb_2/lutd'\'' 
+        at site SLICE_X12Y102, Instance roi/clb_2/lutd can not be placed in D6LUT 
+        of site SLICE_X12Y102 because the bel is occupied by roi/clb_2/RAM64X1S/SP(port:). 
+        This could be caused by bel constraint conflict
+
+        Hmm I guess they have to go in LUTD after all
+        Unclear to me why this is
+        '''
+        #unbel_beli = random.randint(0, 3)
+        unbel_beli = 3
+        if random.randint(0, 1):
+            unbel_beli = None
         bels = []
         for beli in range(4):
             belc = chr(ord('A') + beli)
@@ -120,21 +135,26 @@ for i in range(CLBN):
                 params += ', .N_%s(1)' % bel
             else:
                 bel = random.choice(multi_bels_by)
+                if multis == 0:
+                    # Force an all LUT6 SLICE
+                    bel = 'LUT6'
                 params += ', .%c_%s(1)' % (belc, bel)
 
             bels.append(bel)
         # Record the BELs we chose in the module (A, B, C, D)
-        cparams = ',' + (', '.join(bels))
+        cparams = ',' + (','.join(bels))
+        multis += 1
     # Greedy module
     # Don't place anything else in it
     # For solving muxes vs previous results
     else:
         module = random.choice(greedy_modules)
         params = ''
+        cparams = ',,,,'
 
     print('    %s' % module)
     print('            #(.LOC("%s")%s)' % (loc, params))
-    print('            clb_%d (.clk(clk), .din(din[  %d +: 8]), .dout(dout[  %d +: 8]));' % (i, 8 * i, 8 * i))
+    print('            clb_%d (.clk(clk), .din(din[  %d +: 8]), .dout(dout[  %d +: 8]));' % (clbi, 8 * clbi, 8 * clbi))
 
     f.write('%s,%s%s\n' % (module, loc, cparams))
 f.close()
@@ -154,15 +174,28 @@ module my_ram_N (input clk, input [7:0] din, output [7:0] dout);
     parameter LOC = "";
     parameter D_SRL16E=0;
     parameter D_SRLC32E=0;
+    parameter D_LUT6=0;
+
     parameter C_SRL16E=0;
     parameter C_SRLC32E=0;
+    parameter C_LUT6=0;
+
     parameter B_SRL16E=0;
     parameter B_SRLC32E=0;
+    parameter B_LUT6=0;
+
     parameter A_SRL16E=0;
     parameter A_SRLC32E=0;
+    parameter A_LUT6=0;
 
     parameter N_RAM32X1S=0;
     parameter N_RAM64X1S=0;
+    
+    parameter SRLINIT = 32'h00000000;
+    //parameter LUTINIT6 = 64'h0000_0000_0000_0000;
+    parameter LUTINIT6 = 64'hFFFF_FFFF_FFFF_FFFF;
+
+    wire ce = din[4];
 
     generate
         if (D_SRL16E) begin
@@ -174,23 +207,37 @@ module my_ram_N (input clk, input [7:0] din, output [7:0] dout);
                     .A1(din[1]),
                     .A2(din[2]),
                     .A3(din[3]),
-                    .CE(din[4]),
+                    .CE(ce),
-                    .CLK(din[5]),
+                    .CLK(clk),
                     .D(din[6]));
         end
         if (D_SRLC32E) begin
             (* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
             SRLC32E #(
-                    .INIT(32'h00000000),
+                    .INIT(SRLINIT),
                     .IS_CLK_INVERTED(1'b0)
                 ) lutd (
                     .Q(dout[3]),
                     .Q31(),
                     .A(din[4:0]),
-                    .CE(din[5]),
+                    .CE(ce),
-                    .CLK(din[6]),
+                    .CLK(clk),
                     .D(din[7]));
         end
+        if (D_LUT6) begin
+	        (* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
+	        LUT6_2 #(
+		        .INIT(LUTINIT6)
+	        ) lutd (
+		        .I0(din[0]),
+		        .I1(din[1]),
+		        .I2(din[2]),
+		        .I3(din[3]),
+		        .I4(din[4]),
+		        .I5(din[5]),
+		        .O5(),
+		        .O6(dout[3]));
+        end
 
         if (C_SRL16E) begin
             (* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
@@ -201,23 +248,37 @@ module my_ram_N (input clk, input [7:0] din, output [7:0] dout);
                     .A1(din[1]),
                     .A2(din[2]),
                     .A3(din[3]),
-                    .CE(din[4]),
+                    .CE(ce),
-                    .CLK(din[5]),
+                    .CLK(clk),
                     .D(din[6]));
         end
         if (C_SRLC32E) begin
             (* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
             SRLC32E #(
-                    .INIT(32'h00000000),
+                    .INIT(SRLINIT),
                     .IS_CLK_INVERTED(1'b0)
                 ) lutc (
                     .Q(dout[2]),
                     .Q31(),
                     .A(din[4:0]),
-                    .CE(din[5]),
+                    .CE(ce),
-                    .CLK(din[6]),
+                    .CLK(clk),
                     .D(din[7]));
         end
+        if (C_LUT6) begin
+	        (* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
+	        LUT6_2 #(
+		        .INIT(LUTINIT6)
+	        ) lutc (
+		        .I0(din[0]),
+		        .I1(din[1]),
+		        .I2(din[2]),
+		        .I3(din[3]),
+		        .I4(din[4]),
+		        .I5(din[5]),
+		        .O5(),
+		        .O6(dout[2]));
+        end
 
         if (B_SRL16E) begin
             (* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
@@ -228,23 +289,37 @@ module my_ram_N (input clk, input [7:0] din, output [7:0] dout);
                     .A1(din[1]),
                     .A2(din[2]),
                     .A3(din[3]),
-                    .CE(din[4]),
+                    .CE(ce),
-                    .CLK(din[5]),
+                    .CLK(clk),
                     .D(din[6]));
         end
         if (B_SRLC32E) begin
             (* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
             SRLC32E #(
-                    .INIT(32'h00000000),
+                    .INIT(SRLINIT),
                     .IS_CLK_INVERTED(1'b0)
                 ) lutb (
                     .Q(dout[1]),
                     .Q31(),
                     .A(din[4:0]),
-                    .CE(din[5]),
+                    .CE(ce),
-                    .CLK(din[6]),
+                    .CLK(clk),
                     .D(din[7]));
         end
+        if (B_LUT6) begin
+	        (* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
+	        LUT6_2 #(
+		        .INIT(LUTINIT6)
+	        ) lutb (
+		        .I0(din[0]),
+		        .I1(din[1]),
+		        .I2(din[2]),
+		        .I3(din[3]),
+		        .I4(din[4]),
+		        .I5(din[5]),
+		        .O5(),
+		        .O6(dout[1]));
+        end
 
         if (A_SRL16E) begin
             (* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
@@ -255,23 +330,37 @@ module my_ram_N (input clk, input [7:0] din, output [7:0] dout);
                     .A1(din[1]),
                     .A2(din[2]),
                     .A3(din[3]),
-                    .CE(din[4]),
+                    .CE(ce),
-                    .CLK(din[5]),
+                    .CLK(clk),
                     .D(din[6]));
         end
         if (A_SRLC32E) begin
             (* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
             SRLC32E #(
-                    .INIT(32'h00000000),
+                    .INIT(SRLINIT),
                     .IS_CLK_INVERTED(1'b0)
                 ) luta (
                     .Q(dout[0]),
                     .Q31(),
                     .A(din[4:0]),
-                    .CE(din[5]),
+                    .CE(ce),
-                    .CLK(din[6]),
+                    .CLK(clk),
                     .D(din[7]));
         end
+        if (A_LUT6) begin
+	        (* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
+	        LUT6_2 #(
+		        .INIT(LUTINIT6)
+	        ) luta (
+		        .I0(din[0]),
+		        .I1(din[1]),
+		        .I2(din[2]),
+		        .I3(din[3]),
+		        .I4(din[4]),
+		        .I5(din[5]),
+		        .O5(),
+		        .O6(dout[0]));
+        end
 
         if (N_RAM32X1S) begin
             (* LOC=LOC, KEEP, DONT_TOUCH *)
@@ -284,8 +373,8 @@ module my_ram_N (input clk, input [7:0] din, output [7:0] dout);
                     .A3(din[3]),
                     .A4(din[4]),
                     .D(din[5]),
-                    .WCLK(din[6]),
+                    .WCLK(clk),
-                    .WE(din[7]));
+                    .WE(ce));
         end
         if (N_RAM64X1S) begin
             (* LOC=LOC, KEEP, DONT_TOUCH *)
@@ -300,7 +389,7 @@ module my_ram_N (input clk, input [7:0] din, output [7:0] dout);
                     .A5(din[5]),
                     .D(din[6]),
                     .WCLK(clk),
-                    .WE(din[0]));
+                    .WE(ce));
         end
     endgenerate
 endmodule