mirror of https://github.com/openXC7/prjxray.git
clbram fuzzer main bits. Some disabled due to automated ambiguity
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
ffd77f321d
commit
1e72c82d41
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@ -0,0 +1,4 @@
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/specimen_*/
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/*.segbits
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/vivado.log
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/vivado.jou
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@ -7,27 +7,79 @@ from segmaker import segmaker
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segmk = segmaker("design.bits")
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# Can fit 4 per CLB
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# BELable
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multi_bels_by = [
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'SRL16E',
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'SRLC32E',
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]
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# Not BELable
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multi_bels_bn = [
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'RAM32X1S',
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'RAM64X1S',
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]
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# Those requiring special resources
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# Just make one per module
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greedy_modules = [
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'my_RAM128X1D',
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'my_RAM128X1S',
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'my_RAM256X1S',
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]
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print("Loading tags")
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'''
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module,loc,n,def_a
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clb_N5FFMUX,SLICE_X12Y100,3,1
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clb_N5FFMUX,SLICE_X13Y100,0,1
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clb_N5FFMUX,SLICE_X14Y100,3,1
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module,loc,bela,belb,belc,beld
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my_ram_N,SLICE_X12Y100,SRL16E,SRLC32E,SRLC32E,SRLC32E
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my_ram_N,SLICE_X12Y101,SRLC32E,SRL16E,SRL16E,SRLC32E
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my_ram_N,SLICE_X12Y102,SRLC32E,SRL16E,SRLC32E,RAM32X1S
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my_RAM256X1S,SLICE_X12Y103,,,,
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'''
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f = open('params.csv', 'r')
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f.readline()
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for l in f:
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module,loc,n,def_a = l.split(',')
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def_a = int(def_a)
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n = int(n)
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#which = chr(ord('A') + n)
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l = l.strip()
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module,loc,bela,belb,belc,beld = l.split(',')
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bels = [bela,belb,belc,beld]
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if module in greedy_modules:
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'''
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my_RAM128X1D #(.LOC("SLICE_X12Y100"))
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WA7USED
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my_RAM128X1S #(.LOC("SLICE_X12Y102"))
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WA7USED
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my_RAM256X1S #(.LOC("SLICE_X12Y103"))
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WA7USED, WA8USED
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'''
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which = 'D'
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if 0:
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segmk.addtag(loc, "WA7USED", 1)
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segmk.addtag(loc, "WA8USED", module == 'my_RAM256X1S')
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else:
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'''
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LUTD
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01_23 01_59 30_47 31_47
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SRL16E 1 1 1
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SRLC32E 1 1
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RAM32X1S 1 1 1
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RAM64X1S 1 1
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01_23: WEMUX.CE (more info needed)
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01_59: half sized memory
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30_47: SRL mode
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31_47: RAM mode
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'''
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for which, bel in zip('ABCD', bels):
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print(which, bel)
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segmk.addtag(loc, "%sLUT.SMALL" % which, bel in ('SRL16E', 'RAM32X1S'))
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segmk.addtag(loc, "%sLUT.SRL" % which, bel in ('SRL16E', 'SRLC32E'))
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# Only valid in D
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if which == 'D':
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segmk.addtag(loc, "%sLUT.RAM" % which, bel in ('RAM32X1S', 'RAM64X1S'))
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if 0:
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segmk.addtag(loc, "WA7USED", 0)
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segmk.addtag(loc, "WA8USED", 0)
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segmk.addtag(loc, "WEMUX.CE", bels != ['LUT6', 'LUT6', 'LUT6', 'LUT6'])
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for i, which in enumerate('ABCD'):
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# Theory: there is one bit for each mux positon
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# In each config 3 muxes are in one position, other 3 are in another
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inv = int(i == n)
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segmk.addtag(loc, "%c5FF.MUX.A" % which, def_a ^ inv)
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segmk.addtag(loc, "%c5FF.MUX.B" % which, 1 ^ def_a ^ inv)
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segmk.compile()
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segmk.write()
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@ -11,7 +11,7 @@ def slice_xy():
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ms = [int(m.group(i + 1)) for i in range(4)]
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return ((ms[0], ms[2] + 1), (ms[1], ms[3] + 1))
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CLBN = 4
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CLBN = 50
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SLICEX, SLICEY = slice_xy()
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# 800
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SLICEN = (SLICEY[1] - SLICEY[0]) * (SLICEX[1] - SLICEX[0])
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@ -75,10 +75,11 @@ endmodule
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''' % (DIN_N, DOUT_N))
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f = open('params.csv', 'w')
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f.write('module,loc,n,def_a\n')
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f.write('module,loc,bela,belb,belc,beld\n')
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slices = gen_slicems()
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print('module roi(input clk, input [%d:0] din, output [%d:0] dout);' % (DIN_N - 1, DOUT_N - 1))
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for i in range(CLBN):
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multis = 0
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for clbi in range(CLBN):
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bel = ''
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# Can fit 4 per CLB
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@ -86,6 +87,7 @@ for i in range(CLBN):
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multi_bels_by = [
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'SRL16E',
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'SRLC32E',
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'LUT6',
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]
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# Not BELable
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multi_bels_bn = [
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@ -103,6 +105,7 @@ for i in range(CLBN):
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loc = next(slices)
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params = ''
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cparams = ''
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# Multi module
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if random.randint(0, 3) > 0:
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@ -110,7 +113,19 @@ for i in range(CLBN):
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module = 'my_ram_N'
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# Pick one un-LOCable and then fill in with LOCable
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unbel_beli = random.randint(0, 3)
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'''
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CRITICAL WARNING: [Constraints 18-5] Cannot loc instance '\''roi/clb_2/lutd'\''
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at site SLICE_X12Y102, Instance roi/clb_2/lutd can not be placed in D6LUT
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of site SLICE_X12Y102 because the bel is occupied by roi/clb_2/RAM64X1S/SP(port:).
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This could be caused by bel constraint conflict
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Hmm I guess they have to go in LUTD after all
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Unclear to me why this is
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'''
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#unbel_beli = random.randint(0, 3)
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unbel_beli = 3
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if random.randint(0, 1):
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unbel_beli = None
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bels = []
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for beli in range(4):
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belc = chr(ord('A') + beli)
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@ -120,21 +135,26 @@ for i in range(CLBN):
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params += ', .N_%s(1)' % bel
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else:
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bel = random.choice(multi_bels_by)
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if multis == 0:
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# Force an all LUT6 SLICE
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bel = 'LUT6'
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params += ', .%c_%s(1)' % (belc, bel)
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bels.append(bel)
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# Record the BELs we chose in the module (A, B, C, D)
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cparams = ',' + (', '.join(bels))
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cparams = ',' + (','.join(bels))
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multis += 1
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# Greedy module
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# Don't place anything else in it
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# For solving muxes vs previous results
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else:
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module = random.choice(greedy_modules)
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params = ''
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cparams = ',,,,'
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print(' %s' % module)
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print(' #(.LOC("%s")%s)' % (loc, params))
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print(' clb_%d (.clk(clk), .din(din[ %d +: 8]), .dout(dout[ %d +: 8]));' % (i, 8 * i, 8 * i))
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print(' clb_%d (.clk(clk), .din(din[ %d +: 8]), .dout(dout[ %d +: 8]));' % (clbi, 8 * clbi, 8 * clbi))
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f.write('%s,%s%s\n' % (module, loc, cparams))
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f.close()
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@ -154,15 +174,28 @@ module my_ram_N (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter D_SRL16E=0;
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parameter D_SRLC32E=0;
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parameter D_LUT6=0;
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parameter C_SRL16E=0;
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parameter C_SRLC32E=0;
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parameter C_LUT6=0;
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parameter B_SRL16E=0;
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parameter B_SRLC32E=0;
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parameter B_LUT6=0;
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parameter A_SRL16E=0;
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parameter A_SRLC32E=0;
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parameter A_LUT6=0;
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parameter N_RAM32X1S=0;
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parameter N_RAM64X1S=0;
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parameter SRLINIT = 32'h00000000;
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//parameter LUTINIT6 = 64'h0000_0000_0000_0000;
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parameter LUTINIT6 = 64'hFFFF_FFFF_FFFF_FFFF;
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wire ce = din[4];
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generate
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if (D_SRL16E) begin
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@ -174,23 +207,37 @@ module my_ram_N (input clk, input [7:0] din, output [7:0] dout);
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.CE(ce),
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.CLK(clk),
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.D(din[6]));
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end
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if (D_SRLC32E) begin
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(* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
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SRLC32E #(
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.INIT(32'h00000000),
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.INIT(SRLINIT),
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.IS_CLK_INVERTED(1'b0)
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) lutd (
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.Q(dout[3]),
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.Q31(),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.CE(ce),
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.CLK(clk),
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.D(din[7]));
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end
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if (D_LUT6) begin
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(* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(LUTINIT6)
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) lutd (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(),
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.O6(dout[3]));
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end
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if (C_SRL16E) begin
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(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
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@ -201,23 +248,37 @@ module my_ram_N (input clk, input [7:0] din, output [7:0] dout);
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.CE(ce),
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.CLK(clk),
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.D(din[6]));
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end
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if (C_SRLC32E) begin
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(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
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SRLC32E #(
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.INIT(32'h00000000),
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.INIT(SRLINIT),
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.IS_CLK_INVERTED(1'b0)
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) lutc (
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.Q(dout[2]),
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.Q31(),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.CE(ce),
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.CLK(clk),
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.D(din[7]));
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end
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if (C_LUT6) begin
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(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(LUTINIT6)
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) lutc (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(),
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.O6(dout[2]));
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end
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if (B_SRL16E) begin
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(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
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@ -228,23 +289,37 @@ module my_ram_N (input clk, input [7:0] din, output [7:0] dout);
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.CE(ce),
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.CLK(clk),
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.D(din[6]));
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end
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if (B_SRLC32E) begin
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(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
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SRLC32E #(
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.INIT(32'h00000000),
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.INIT(SRLINIT),
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.IS_CLK_INVERTED(1'b0)
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) lutb (
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.Q(dout[1]),
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.Q31(),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.CE(ce),
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.CLK(clk),
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.D(din[7]));
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end
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if (B_LUT6) begin
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(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(LUTINIT6)
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) lutb (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(),
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.O6(dout[1]));
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end
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if (A_SRL16E) begin
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(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
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@ -255,23 +330,37 @@ module my_ram_N (input clk, input [7:0] din, output [7:0] dout);
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.CE(ce),
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.CLK(clk),
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.D(din[6]));
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end
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if (A_SRLC32E) begin
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(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
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SRLC32E #(
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.INIT(32'h00000000),
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.INIT(SRLINIT),
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.IS_CLK_INVERTED(1'b0)
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) luta (
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.Q(dout[0]),
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.Q31(),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.CE(ce),
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.CLK(clk),
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.D(din[7]));
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end
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if (A_LUT6) begin
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(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(LUTINIT6)
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) luta (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(),
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.O6(dout[0]));
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end
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if (N_RAM32X1S) begin
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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@ -284,8 +373,8 @@ module my_ram_N (input clk, input [7:0] din, output [7:0] dout);
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.A3(din[3]),
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.A4(din[4]),
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.D(din[5]),
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.WCLK(din[6]),
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.WE(din[7]));
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.WCLK(clk),
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.WE(ce));
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end
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if (N_RAM64X1S) begin
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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@ -300,7 +389,7 @@ module my_ram_N (input clk, input [7:0] din, output [7:0] dout);
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.A5(din[5]),
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.D(din[6]),
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.WCLK(clk),
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.WE(din[0]));
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.WE(ce));
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end
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endgenerate
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endmodule
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