mirror of https://github.com/openXC7/prjxray.git
lutcfg minitest
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
bdb216c651
commit
1dbf6181e8
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@ -0,0 +1,25 @@
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N := 3
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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all:
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bash runme.sh
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database: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
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pushdb:
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${XRAY_MERGEDDB} clbll_l seg_clblx.segbits
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${XRAY_MERGEDDB} clbll_r seg_clblx.segbits
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${XRAY_MERGEDDB} clblm_l seg_clblx.segbits
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${XRAY_MERGEDDB} clblm_r seg_clblx.segbits
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit
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.PHONY: database pushdb clean
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@ -0,0 +1,7 @@
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#!/bin/bash
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set -ex
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# rm -f vivado*.log vivado*.jou
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vivado -mode batch -source runme.tcl
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
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#${XRAY_SEGPRINT} design.bits SLICE_X16Y100 SLICE_X16Y101 SLICE_X16Y102 SLICE_X16Y103
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@ -0,0 +1,26 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -0,0 +1,253 @@
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 64;
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localparam integer DOUT_N = 8;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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module roi(input clk, input [63:0] din, output [7:0] dout);
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clb_LUT6 clb_LUT6 (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0]));
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clb_LUT6_2 clb_LUT6_2 (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 1]));
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clb_LUT7A clb_LUT7A (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 2]));
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clb_LUT7B clb_LUT7B (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 3]));
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clb_LUT7AB clb_LUT7AB (.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 4]));
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clb_LUT8 clb_LUT8 (.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 5]));
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endmodule
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module clb_LUT6 (input clk, input [7:0] din, output dout);
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(* LOC="SLICE_X16Y100", BEL="A6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_0000_0000_0001)
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) lut (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(dout));
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endmodule
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module clb_LUT6_2 (input clk, input [7:0] din, output dout);
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wire o5;
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wire o6;
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assign dout = o5 & o6;
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(* LOC="SLICE_X16Y101", BEL="A6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_0000_0000_0001)
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) lut (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(o5),
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.O6(o6));
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endmodule
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module clb_LUT7A (input clk, input [7:0] din, output dout);
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wire lutbo, lutao;
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//F7AMUX
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(* LOC="SLICE_X16Y102", BEL="F7AMUX", KEEP, DONT_TOUCH *)
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MUXF7 mux7a (.O(dout), .I0(lutbo), .I1(lutao), .S(din[6]));
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(* LOC="SLICE_X16Y102", BEL="B6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_DEAD_0000_0001)
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) lut0 (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(lutbo));
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(* LOC="SLICE_X16Y102", BEL="A6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_BEEF_0000_0001)
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) lut1 (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(lutao));
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endmodule
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module clb_LUT7B (input clk, input [7:0] din, output dout);
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wire lutdo, lutco;
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(* LOC="SLICE_X16Y103", BEL="F7BMUX", KEEP, DONT_TOUCH *)
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MUXF7 mux7b (.O(dout), .I0(lutdo), .I1(lutco), .S(din[6]));
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(* LOC="SLICE_X16Y103", BEL="D6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_DEAD_0000_0001)
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) lutd (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(lutdo));
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(* LOC="SLICE_X16Y103", BEL="C6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_BEEF_0000_0001)
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) lutc (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(lutco));
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endmodule
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module clb_LUT7AB (input clk, input [7:0] din, output dout);
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wire lutdo, lutco, lutbo, lutao;
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wire lut7bo, lut7ao;
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assign dout = lut7bo & lut7ao;
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(* LOC="SLICE_X16Y104", BEL="F7BMUX", KEEP, DONT_TOUCH *)
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MUXF7 mux7b (.O(lut7bo), .I0(lutdo), .I1(lutco), .S(din[6]));
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(* LOC="SLICE_X16Y104", BEL="F7AMUX", KEEP, DONT_TOUCH *)
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MUXF7 mux7a (.O(lut7ao), .I0(lutbo), .I1(lutao), .S(din[7]));
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(* LOC="SLICE_X16Y104", BEL="B6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_DEAD_0000_0001)
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) lut0 (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(lutbo));
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(* LOC="SLICE_X16Y104", BEL="A6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_BEEF_0000_0001)
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) lut1 (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(lutao));
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(* LOC="SLICE_X16Y104", BEL="D6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_DEAD_0000_0001)
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) lutd (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(lutdo));
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(* LOC="SLICE_X16Y104", BEL="C6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_BEEF_0000_0001)
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) lutc (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(lutco));
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endmodule
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module clb_LUT8 (input clk, input [7:0] din, output dout);
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wire lutdo, lutco, lutbo, lutao;
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wire lut7bo, lut7ao;
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wire lut8o;
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(* LOC="SLICE_X16Y105", BEL="F8MUX", KEEP, DONT_TOUCH *)
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MUXF8 mux8 (.O(dout), .I0(lut7bo), .I1(lut7ao), .S(din[7]));
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(* LOC="SLICE_X16Y105", BEL="F7BMUX", KEEP, DONT_TOUCH *)
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MUXF7 mux7b (.O(lut7bo), .I0(lutdo), .I1(lutco), .S(din[6]));
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(* LOC="SLICE_X16Y105", BEL="F7AMUX", KEEP, DONT_TOUCH *)
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MUXF7 mux7a (.O(lut7ao), .I0(lutbo), .I1(lutao), .S(din[6]));
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(* LOC="SLICE_X16Y105", BEL="D6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_DEAD_0000_0001)
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) lutd (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(lutdo));
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(* LOC="SLICE_X16Y105", BEL="C6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_BEEF_0000_0001)
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) lutc (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(lutco));
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(* LOC="SLICE_X16Y105", BEL="B6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_CAFE_0000_0001)
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) lutb (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(lutbo));
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(* LOC="SLICE_X16Y105", BEL="A6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_1CE0_0000_0001)
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) luta (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(lutao));
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endmodule
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