pcie: add to tilegrid

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>

fuzzers/005-tilegrid/Makefile

@@ -30,6 +30,11 @@ TILEGRID_TDB_DEPENDENCIES += pll/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += hclk_ioi/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 GENERATE_FULL_ARGS=
 
+ifeq (${XRAY_DATABASE}, artix7)
+# Artix7 only
+TILEGRID_TDB_DEPENDENCIES += pcie/$(BUILD_FOLDER)/segbits_tilegrid.tdb
+endif
+
 ifeq (${XRAY_DATABASE}, zynq7)
 # Zynq7 only
 TILEGRID_TDB_DEPENDENCIES += ps7_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb
@@ -130,6 +135,9 @@ hclk_cmt/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
 hclk_ioi/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
 	cd hclk_ioi && $(MAKE)
 
+pcie/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
+	cd pcie && $(MAKE)
+
 $(BUILD_FOLDER)/tilegrid_tdb.json: add_tdb.py $(TILEGRID_TDB_DEPENDENCIES)
 	python3 add_tdb.py \
 		--fn-in ${BASICDB_TILEGRID} \
@@ -170,6 +178,7 @@ clean:
 	cd clk_bufg && $(MAKE) clean
 	cd hclk_cmt && $(MAKE) clean
 	cd hclk_ioi && $(MAKE) clean
+	cd pcie && $(MAKE) clean
 
 .PHONY: database pushdb clean run
 

fuzzers/005-tilegrid/add_tdb.py

@@ -101,6 +101,7 @@ def run(fn_in, fn_out, verbose=False):
         ("clk_bufg", 30, 8),
         ("hclk_cmt", 30, 10),
         ("hclk_ioi", 42, 1),
+        ("pcie", 36, 101),
         ("clb_int", int_frames, int_words),
         ("iob_int", int_frames, int_words),
         ("bram_int", int_frames, int_words),

fuzzers/005-tilegrid/pcie/Makefile

@@ -0,0 +1,10 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+N ?= 2
+GENERATE_ARGS?="--oneval 0 --design params.csv --dframe 1c --dword 0 --dbit 16"
+include ../fuzzaddr/common.mk

fuzzers/005-tilegrid/pcie/generate.tcl

@@ -0,0 +1,35 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+source "$::env(XRAY_DIR)/utils/utils.tcl"
+
+proc run {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+    # Disable MMCM frequency etc sanity checks
+    set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}]
+    set_property IS_ENABLED 0 [get_drc_checks {PDRC-30}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-50}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-53}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-126}]
+    set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
+    set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+}
+
+run

fuzzers/005-tilegrid/pcie/top.py

@@ -0,0 +1,61 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+import os
+import random
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray.db import Database
+
+
+def gen_sites():
+    db = Database(util.get_db_root(), util.get_part())
+    grid = db.grid()
+    for tile_name in sorted(grid.tiles()):
+        loc = grid.loc_of_tilename(tile_name)
+        gridinfo = grid.gridinfo_at_loc(loc)
+
+        for site_name, site_type in gridinfo.sites.items():
+            if site_type in ['PCIE_2_1']:
+                yield tile_name, site_name
+
+
+def write_params(params):
+    pinstr = 'tile,val,site\n'
+    for tile, (site, val) in sorted(params.items()):
+        pinstr += '%s,%s,%s\n' % (tile, val, site)
+    open('params.csv', 'w').write(pinstr)
+
+
+def run():
+    print('''
+module top(input wire in, output wire out);
+    ''')
+
+    params = {}
+
+    sites = list(gen_sites())
+    for (tile_name, site_name), isone in zip(sites,
+                                             util.gen_fuzz_states(len(sites))):
+        params[tile_name] = (site_name, isone)
+
+        attr = "FALSE" if isone else "TRUE"
+        print('''
+    (* KEEP, DONT_TOUCH*)
+    PCIE_2_1 #(
+        .AER_CAP_PERMIT_ROOTERR_UPDATE("{}")
+    ) pcie ();'''.format(attr))
+
+    print("endmodule")
+    write_params(params)
+
+
+if __name__ == '__main__':
+    run()