mirror of https://github.com/openXC7/prjxray.git
071-ppips rewrite attempt using RapidWright
Signed-off-by: Hans Baier <hansfbaier@gmail.com>
This commit is contained in:
Hans Baier
parent
de5c7afcb4
commit
12c061569f
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@ -6,19 +6,12 @@
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#
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# SPDX-License-Identifier: ISC
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N := 1
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SPECIMENS := $(addprefix build/specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: $(SPECIMENS_OK)
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cp build/specimen_001/ppips_*.db build/
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pushdb:
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pushdb: build
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cp build/ppips_*.db ${XRAY_DATABASE_DIR}/$(XRAY_DATABASE)/
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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database:
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mkdir build
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./generate.py
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run:
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$(MAKE) clean
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@ -0,0 +1,21 @@
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#!/usr/bin/env python3
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import sys
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from os import environ
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import rapidwright
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from com.xilinx.rapidwright.design import Design
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from com.xilinx.rapidwright.device import PseudoPIPHelper, Device
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import com.xilinx.rapidwright.device.TileTypeEnum as TileType
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part = environ["XRAY_PART"]
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device = Device.getDevice(part)
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ppipmap = PseudoPIPHelper.getPseudoPIPMap(device)
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tiletypes = ppipmap.keys()
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for tiletype in tiletypes:
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filename = f"build/ppips_{str(tiletype.toString()).lower()}.db"
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with open(filename, 'w') as f:
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rioi = ppipmap[tiletype]
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ppipnames = [str(ph.getPseudoPIPName()) for ph in list(rioi.values())]
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for ppip in ppipnames:
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src, dest = ppip.split(str(tiletype) + ".")[-1].split("->")
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f.write(f"{tiletype}.{dest}.{src} always")
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@ -1,13 +0,0 @@
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#!/bin/bash -x
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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source ${XRAY_GENHEADER}
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${XRAY_VIVADO} -mode batch -source $FUZDIR/generate.tcl
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@ -1,401 +0,0 @@
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# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog $::env(FUZDIR)/top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports a]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports y]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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place_design
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route_design
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write_checkpoint -force design.dcp
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# write_bitstream -force design.bit
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proc write_common_ppips_db {filename tile} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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if {[get_property IS_PSEUDO $pip]} {
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set src_wire [get_wires -uphill -of_objects $pip]
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] hint"
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} elseif {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
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set src_wire [get_wires -uphill -of_objects $pip]
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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}
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close $fp
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}
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proc write_int_ppips_db {filename tile} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects [get_wires $tile/VCC_WIRE]] {
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set wire [regsub {.*/} [get_wires -downhill -of_objects $pip] ""]
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puts $fp "${tile_type}.${wire}.VCC_WIRE default"
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}
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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if {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
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set src_wire [get_wires -uphill -of_objects $pip]
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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}
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close $fp
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}
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proc write_bram_ppips_db {filename tile} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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if {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
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set src_wire [get_wires -uphill -of_objects $pip]
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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} elseif [string match "*LOGIC_OUTS*" $dst_wire] {
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# LOGIC_OUTS pips appear to be always, even thought multiple inputs to
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# the pip junction. Best guess is that the underlying hardware is
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# actually just one wire, and there is no actual junction.
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foreach src_wire [get_wires -uphill -of_objects $pip] {
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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}
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}
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close $fp
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}
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proc write_dsp_ppips_db {filename tile} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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if {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
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set src_wire [get_wires -uphill -of_objects $pip]
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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}
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close $fp
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}
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proc write_hclk_ppips_db {filename tile} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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if [string match "*HCLK_IOI_CK_IGCLK*" $dst_wire] {
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continue
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} elseif {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
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set src_wire [get_wires -uphill -of_objects $pip]
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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}
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close $fp
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}
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proc write_ioi_ppips_db {filename tile} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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if [string match "*DATAOUT*" $dst_wire] {
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continue
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} elseif {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
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set src_wire [get_wires -uphill -of_objects $pip]
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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}
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close $fp
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}
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proc write_pss_ppips_db {filename tile} {
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if {[llength $tile] != 0} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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# Skip bi-directional PIPs as they represent hard-wired PS7 connections
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# and are not routable.
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foreach pip [get_pips -of_objects $tile -filter "IS_DIRECTIONAL == 1"] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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if {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
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set src_wire [get_wires -uphill -of_objects $pip]
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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}
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close $fp
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}
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}
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proc write_gtp_channel_ppips_db {filename tile tile_suffix} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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set src_wire [get_wires -uphill -of_objects $pip]
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set num_uphill_nodes [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
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# All the "MID" GTP tiles (e.g. in the artix 200T devices) have configuration bits
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# even for nodes with only one uphill nodes connections.
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# E.g.: IBUFDS_GTPE2_1_MGTCLKOUT_MUX.IBUFDS_GTPE2_1_MGTCLKOUT
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# The above is a real PIP and should not be added to the PPIPs list.
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set mux [regexp "MUX" $dst_wire]
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set mgt_clk [regexp "MGT_CLK\[0-9\]+" $dst_wire]
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set mgtclkout [regexp "MGTCLKOUT" $dst_wire]
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if {($num_uphill_nodes != 1 && !$mgtclkout) ||
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$mux ||
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($mgt_clk && $tile_suffix != "")} {
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continue
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}
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puts $fp "${tile_type}${tile_suffix}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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close $fp
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}
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proc write_gtp_int_interface_ppips_db {filename tile tile_suffix wire_suffix} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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set src_wire [get_wires -uphill -of_objects $pip]
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if {[regexp "DELAY" $src_wire]} {
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continue
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}
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set map {}
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lappend map {GTPE2} GTPE2${wire_suffix}
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set dst_wire [string map $map $dst_wire]
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set src_wire [string map $map $src_wire]
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# Adding GTPE2_ prefix to wires only for GTP_INT_INTERFACE_[RL] and the wire is a LOGIC_OUTS type
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# The GTP_INT_INTERFACE tile does not have the GTPE2_ prefix for this wires
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set logic_outs [regexp "LOGIC_OUTS\[0-9\]+" $dst_wire]
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if {$logic_outs && $wire_suffix != ""} {
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set map {}
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lappend map {INT_INTERFACE} GTPE2_INT_INTERFACE
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set dst_wire [string map $map $dst_wire]
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set src_wire [string map $map $src_wire]
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}
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puts $fp "${tile_type}${tile_suffix}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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close $fp
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}
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proc write_pcie_ppips_db {filename tile tile_suffix} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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if {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
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set src_wire [get_wires -uphill -of_objects $pip]
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if {![regexp "PCIE" $src_wire]} {
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continue
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}
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puts $fp "${tile_type}${tile_suffix}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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}
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close $fp
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}
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proc write_pcie_int_interface_ppips_db {filename tile allows forbids} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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set src_wire [get_wires -uphill -of_objects $pip]
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set skip_wire false
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foreach wire $forbids {
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if {[regexp $wire $src_wire]} {
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set skip_wire true
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break
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}
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}
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if {$skip_wire == true} {
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continue
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}
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set skip_wire true
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foreach wire $allows {
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if {[regexp $wire $src_wire]} {
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set skip_wire false
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break
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}
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}
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if {$skip_wire == true} {
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continue
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}
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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close $fp
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}
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foreach tile_type {CLBLM_L CLBLM_R CLBLL_L CLBLL_R} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
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write_common_ppips_db "ppips_[string tolower $tile_type].db" $tile
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}
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}
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foreach tile_type {INT_L INT_R BRAM_INT_INTERFACE_L BRAM_INT_INTERFACE_R \
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DSP_INT_INTERFACE_L DSP_INT_INTERFACE_R \
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CLK_HROW_TOP_R CLK_HROW_BOT_R CLK_BUFG_TOP_R CLK_BUFG_BOT_R \
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IO_INT_INTERFACE_R IO_INT_INTERFACE_L \
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BRKH_INT HCLK_L HCLK_R HCLK_CMT \
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CMT_TOP_L_UPPER_T CMT_TOP_L_UPPER_B \
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CMT_TOP_L_LOWER_T CMT_TOP_L_LOWER_B \
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CMT_TOP_R_UPPER_T CMT_TOP_R_UPPER_B \
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CMT_TOP_R_LOWER_T CMT_TOP_R_LOWER_B \
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INT_INTERFACE_L INT_INTERFACE_R} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
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write_int_ppips_db "ppips_[string tolower $tile_type].db" $tile
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}
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}
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foreach tile_type {HCLK_IOI3} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
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write_hclk_ppips_db "ppips_[string tolower $tile_type].db" $tile
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}
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}
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foreach tile_type {RIOI3 LIOI3 LIOI3_TBYTETERM RIOI3_TBYTETERM \
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LIOI3_TBYTESRC RIOI3_TBYTESRC LIOI3_SING RIOI3_SING RIOI RIOI_SING RIOI_TBYTESRC RIOI_TBYTETERM} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
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write_ioi_ppips_db "ppips_[string tolower $tile_type].db" $tile
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}
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}
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foreach tile_type {BRAM_L BRAM_R} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
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write_bram_ppips_db "ppips_[string tolower $tile_type].db" $tile
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}
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}
|
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foreach tile_type {DSP_L DSP_R} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
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write_dsp_ppips_db "ppips_[string tolower $tile_type].db" $tile
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}
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}
|
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foreach tile_type {PSS0 PSS1 PSS2 PSS3 PSS4 INT_INTERFACE_PSS_L} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
|
||||
write_pss_ppips_db "ppips_[string tolower $tile_type].db" $tile
|
||||
}
|
||||
}
|
||||
|
||||
foreach tile_type {GTP_CHANNEL_0 GTP_CHANNEL_1 GTP_CHANNEL_2 GTP_CHANNEL_3 GTP_COMMON} {
|
||||
set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
|
||||
if {[llength $tiles] != 0} {
|
||||
set tile [lindex $tiles 0]
|
||||
write_gtp_channel_ppips_db "ppips_[string tolower $tile_type].db" $tile ""
|
||||
write_gtp_channel_ppips_db "ppips_[string tolower $tile_type]_mid_left.db" $tile "_MID_LEFT"
|
||||
write_gtp_channel_ppips_db "ppips_[string tolower $tile_type]_mid_right.db" $tile "_MID_RIGHT"
|
||||
}
|
||||
}
|
||||
|
||||
foreach tile_type {GTP_INT_INTERFACE} {
|
||||
set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
|
||||
if {[llength $tiles] != 0} {
|
||||
set tile [lindex $tiles 0]
|
||||
write_gtp_int_interface_ppips_db "ppips_[string tolower $tile_type].db" $tile "" ""
|
||||
write_gtp_int_interface_ppips_db "ppips_[string tolower $tile_type]_r.db" $tile "_R" "_R"
|
||||
write_gtp_int_interface_ppips_db "ppips_[string tolower $tile_type]_l.db" $tile "_L" "_LEFT"
|
||||
}
|
||||
}
|
||||
|
||||
foreach tile_type {PCIE_BOT PCIE_TOP} {
|
||||
set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
|
||||
if {[llength $tiles] != 0} {
|
||||
set tile [lindex $tiles 0]
|
||||
write_pcie_ppips_db "ppips_[string tolower $tile_type].db" $tile ""
|
||||
}
|
||||
}
|
||||
|
||||
foreach tile_type {PCIE_INT_INTERFACE_L PCIE_INT_INTERFACE_R} {
|
||||
set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
|
||||
if {[llength $tiles] != 0} {
|
||||
set tile [lindex $tiles 0]
|
||||
set allow_wires {"IMUX_L\[0-9\]+" "IMUX\[0-9\]+" "LOGIC_OUTS"}
|
||||
set forbid_wires {"DELAY\[0-9\]+"}
|
||||
write_pcie_int_interface_ppips_db "ppips_[string tolower $tile_type].db" $tile $allow_wires $forbid_wires
|
||||
}
|
||||
}
|
||||
|
||||
foreach tile_type {RIOB33 LIOB33 RIOB33_SING LIOB33_SING RIOB18 RIOB18_SING} {
|
||||
set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
|
||||
if {[llength $tiles] != 0} {
|
||||
set tile [lindex $tiles 0]
|
||||
write_common_ppips_db "ppips_[string tolower $tile_type].db" $tile
|
||||
}
|
||||
}
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
module top(input a, output y);
|
||||
assign y = a;
|
||||
endmodule
|
||||
Loading…
Reference in New Issue