mirror of https://github.com/openXC7/prjxray.git
docs: tileconn, tilegrid
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
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John McMaster
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Introduction
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================
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This section documents how prjxray represents FPGA fabric. Its primarily composed of two files:
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* tilegrid.json: list of tiles and how they appear in the bitstream
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* tileconn.json: how tiles are connected together
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General notes:
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* prjxray created names are generally lowercase, while Vivado created names are generally uppercase
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* _l and _r entries are generally identical, but probably represent different physical IP block layouts
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tilegrid.json
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================
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This section assumes you are already familiar with the 7 series bitstream format.
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This file contains two elements:
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* segments: each entry lists sections of the bitstream that encode part of one or more tiles
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* tiles: corres
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segments
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################
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Segments are a prjxray concept.
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Each entry has the following fields:
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* baseaddr: a tuple of (base address, inter-frame offset)
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* frames: how many frames are required to make a complete segment
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* words: number of inter-frame words requird for a complete segment
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* tiles: which tiles reference this segment
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* type: prjxray given segment type
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Sample entry:
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.. code-block:: json
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"SEG_CLBLL_L_X16Y149": {
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"baseaddr": [
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"0x00020800",
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99
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],
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"frames": 36,
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"tiles": [
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"CLBLL_L_X16Y149",
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"INT_L_X16Y149"
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],
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"type": "clbll_l",
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"words": 2
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}
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Interpreted as:
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* Segment is named SEG_CLBLL_L_X16Y149
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* Frame base address is 0x00020800
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* For each frame, skip the first 99 words loaded into FDRI
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* Since its 2 FDRI words out of possible 101, its the last 2 words
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* It spans across 36 different frame loads
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* The data in this segment is used by two different tiles: CLBLL_L_X16Y149, INT_L_X16Y149
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Historical note:
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In the original encoding, a segment was a collection of tiles that were encoded together.
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For example, a CLB is encoded along with a nearby switch.
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However, some tiles, such as BRAM, are much more complex. For example,
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the configuration and data are stored in seperate parts of the bitstream.
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The BRAM itself also spans multiple tiles and has multiple switchboxes.
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tiles
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################
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Each entry has the following fields:
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* grid_x: tile column, increasing right
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* grid_y: tile row, increasing down
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* segment: the primary segment providing bitstream configuration
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* sites: dictionary of sites name: site type contained within tile
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* type: Vivado given tile type
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Sample entry:
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.. code-block:: json
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"CLBLL_L_X16Y149": {
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"grid_x": 43,
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"grid_y": 1,
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"segment": "SEG_CLBLL_L_X16Y149",
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"sites": {
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"SLICE_X24Y149": "SLICEL",
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"SLICE_X25Y149": "SLICEL"
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},
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"type": "CLBLL_L"
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}
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Interpreted as:
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* Located at row 1, column 43
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* Is configured by segment SEG_CLBLL_L_X16Y149
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* Contains two sites, both of which are SLICEL
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* A CLBLL_L type tile
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tileconn.json
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================
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This file documents how adjacent tile pairs are connected.
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No directionality is given.
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The file contains one large list. Each entry has the following fields:
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* grid_deltas: (x, y) delta going from source to destination tile
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* tile_types: (source, destination) tile types
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* wire_pairs: list of (source tile, destination tile) wire names
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Sample entry:
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.. code-block:: json
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{
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"grid_deltas": [
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0,
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1
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],
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"tile_types": [
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"CLBLL_L",
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"HCLK_CLB"
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],
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"wire_pairs": [
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[
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"CLBLL_LL_CIN",
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"HCLK_CLB_COUT0_L"
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],
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[
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"CLBLL_L_CIN",
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"HCLK_CLB_COUT1_L"
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]
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]
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}
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Interpreted as:
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* Use when a CLBLL_L is above a HCLK_CLB (ie pointing south from CLBLL_L)
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* Connect CLBLL_L.CLBLL_LL_CIN to HCLK_CLB.HCLK_CLB_COUT0_L
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* Connect CLBLL_L.CLBLL_L_CIN to HCLK_CLB.HCLK_CLB_COUT1_L
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* A global clock tile is feeding into slice carry chain inputs
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@ -27,3 +27,9 @@ to develop a free and open Verilog to bitstream toolchain for these devices.
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:caption: Database Development Process
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db_dev_process/overview
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.. toctree::
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:maxdepth: 2
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:caption: Output File Formats
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format/tile
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